1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #define CONFIG_E500MC /* BOOKE e500mc family */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 29 #define CONFIG_FSL_IFC /* Enable IFC Support */ 30 31 #define CONFIG_FSL_LAW /* Use common FSL init code */ 32 #define CONFIG_ENV_OVERWRITE 33 34 #define CONFIG_DEEP_SLEEP 35 #if defined(CONFIG_DEEP_SLEEP) 36 #define CONFIG_SILENT_CONSOLE 37 #define CONFIG_BOARD_EARLY_INIT_F 38 #endif 39 40 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 41 42 #ifdef CONFIG_RAMBOOT_PBL 43 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 44 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 45 #define CONFIG_SPL_FLUSH_IMAGE 46 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 47 #define CONFIG_FSL_LAW /* Use common FSL init code */ 48 #define CONFIG_SYS_TEXT_BASE 0x00201000 49 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 50 #define CONFIG_SPL_PAD_TO 0x40000 51 #define CONFIG_SPL_MAX_SIZE 0x28000 52 #define RESET_VECTOR_OFFSET 0x27FFC 53 #define BOOT_PAGE_OFFSET 0x27000 54 #ifdef CONFIG_SPL_BUILD 55 #define CONFIG_SPL_SKIP_RELOCATE 56 #define CONFIG_SPL_COMMON_INIT_DDR 57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 58 #define CONFIG_SYS_NO_FLASH 59 #endif 60 61 #ifdef CONFIG_NAND 62 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 63 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 64 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 65 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 67 #define CONFIG_SPL_NAND_BOOT 68 #endif 69 70 #ifdef CONFIG_SPIFLASH 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 72 #define CONFIG_SPL_SPI_FLASH_MINIMAL 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 78 #ifndef CONFIG_SPL_BUILD 79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 80 #endif 81 #define CONFIG_SPL_SPI_BOOT 82 #endif 83 84 #ifdef CONFIG_SDCARD 85 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 86 #define CONFIG_SPL_MMC_MINIMAL 87 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 88 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 89 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 90 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 91 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 92 #ifndef CONFIG_SPL_BUILD 93 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 94 #endif 95 #define CONFIG_SPL_MMC_BOOT 96 #endif 97 98 #endif /* CONFIG_RAMBOOT_PBL */ 99 100 #ifndef CONFIG_SYS_TEXT_BASE 101 #define CONFIG_SYS_TEXT_BASE 0xeff40000 102 #endif 103 104 #ifndef CONFIG_RESET_VECTOR_ADDRESS 105 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 106 #endif 107 108 #ifndef CONFIG_SYS_NO_FLASH 109 #define CONFIG_FLASH_CFI_DRIVER 110 #define CONFIG_SYS_FLASH_CFI 111 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 112 #endif 113 114 /* PCIe Boot - Master */ 115 #define CONFIG_SRIO_PCIE_BOOT_MASTER 116 /* 117 * for slave u-boot IMAGE instored in master memory space, 118 * PHYS must be aligned based on the SIZE 119 */ 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 121 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 125 #else 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 128 #endif 129 /* 130 * for slave UCODE and ENV instored in master memory space, 131 * PHYS must be aligned based on the SIZE 132 */ 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 135 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 136 #else 137 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 139 #endif 140 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 141 /* slave core release by master*/ 142 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 143 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 144 145 /* PCIe Boot - Slave */ 146 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 148 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 149 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 150 /* Set 1M boot space for PCIe boot */ 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 152 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 153 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 154 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 155 #define CONFIG_SYS_NO_FLASH 156 #endif 157 158 #if defined(CONFIG_SPIFLASH) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_SPI_FLASH 161 #define CONFIG_ENV_SPI_BUS 0 162 #define CONFIG_ENV_SPI_CS 0 163 #define CONFIG_ENV_SPI_MAX_HZ 10000000 164 #define CONFIG_ENV_SPI_MODE 0 165 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 166 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 167 #define CONFIG_ENV_SECT_SIZE 0x10000 168 #elif defined(CONFIG_SDCARD) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_ENV_IS_IN_MMC 171 #define CONFIG_SYS_MMC_ENV_DEV 0 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_OFFSET (512 * 0x800) 174 #elif defined(CONFIG_NAND) 175 #define CONFIG_SYS_EXTRA_ENV_RELOC 176 #define CONFIG_ENV_IS_IN_NAND 177 #define CONFIG_ENV_SIZE 0x2000 178 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 179 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 180 #define CONFIG_ENV_IS_IN_REMOTE 181 #define CONFIG_ENV_ADDR 0xffe20000 182 #define CONFIG_ENV_SIZE 0x2000 183 #elif defined(CONFIG_ENV_IS_NOWHERE) 184 #define CONFIG_ENV_SIZE 0x2000 185 #else 186 #define CONFIG_ENV_IS_IN_FLASH 187 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 188 #define CONFIG_ENV_SIZE 0x2000 189 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 190 #endif 191 192 #ifndef __ASSEMBLY__ 193 unsigned long get_board_sys_clk(void); 194 unsigned long get_board_ddr_clk(void); 195 #endif 196 197 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 198 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 199 200 /* 201 * These can be toggled for performance analysis, otherwise use default. 202 */ 203 #define CONFIG_SYS_CACHE_STASHING 204 #define CONFIG_BACKSIDE_L2_CACHE 205 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 206 #define CONFIG_BTB /* toggle branch predition */ 207 #define CONFIG_DDR_ECC 208 #ifdef CONFIG_DDR_ECC 209 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 210 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 211 #endif 212 213 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 214 #define CONFIG_SYS_MEMTEST_END 0x00400000 215 #define CONFIG_SYS_ALT_MEMTEST 216 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 217 218 /* 219 * Config the L3 Cache as L3 SRAM 220 */ 221 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 222 #define CONFIG_SYS_L3_SIZE (256 << 10) 223 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 224 #ifdef CONFIG_RAMBOOT_PBL 225 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 226 #endif 227 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 228 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 229 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 230 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 231 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_DCSRBAR 0xf0000000 234 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 235 #endif 236 237 /* EEPROM */ 238 #define CONFIG_ID_EEPROM 239 #define CONFIG_SYS_I2C_EEPROM_NXID 240 #define CONFIG_SYS_EEPROM_BUS_NUM 0 241 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 242 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 245 246 /* 247 * DDR Setup 248 */ 249 #define CONFIG_VERY_BIG_RAM 250 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 251 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 252 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 253 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 254 #define CONFIG_DDR_SPD 255 #ifndef CONFIG_SYS_FSL_DDR4 256 #define CONFIG_SYS_FSL_DDR3 257 #endif 258 259 #define CONFIG_SYS_SPD_BUS_NUM 0 260 #define SPD_EEPROM_ADDRESS 0x51 261 262 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 263 264 /* 265 * IFC Definitions 266 */ 267 #define CONFIG_SYS_FLASH_BASE 0xe0000000 268 #ifdef CONFIG_PHYS_64BIT 269 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 270 #else 271 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 272 #endif 273 274 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 275 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 276 + 0x8000000) | \ 277 CSPR_PORT_SIZE_16 | \ 278 CSPR_MSEL_NOR | \ 279 CSPR_V) 280 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 281 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 282 CSPR_PORT_SIZE_16 | \ 283 CSPR_MSEL_NOR | \ 284 CSPR_V) 285 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 286 /* NOR Flash Timing Params */ 287 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 288 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 289 FTIM0_NOR_TEADC(0x5) | \ 290 FTIM0_NOR_TEAHC(0x5)) 291 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 292 FTIM1_NOR_TRAD_NOR(0x1A) |\ 293 FTIM1_NOR_TSEQRAD_NOR(0x13)) 294 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 295 FTIM2_NOR_TCH(0x4) | \ 296 FTIM2_NOR_TWPH(0x0E) | \ 297 FTIM2_NOR_TWP(0x1c)) 298 #define CONFIG_SYS_NOR_FTIM3 0x0 299 300 #define CONFIG_SYS_FLASH_QUIET_TEST 301 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 302 303 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 304 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 305 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 306 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 307 308 #define CONFIG_SYS_FLASH_EMPTY_INFO 309 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 310 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 311 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 312 #define QIXIS_BASE 0xffdf0000 313 #ifdef CONFIG_PHYS_64BIT 314 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 315 #else 316 #define QIXIS_BASE_PHYS QIXIS_BASE 317 #endif 318 #define QIXIS_LBMAP_SWITCH 0x06 319 #define QIXIS_LBMAP_MASK 0x0f 320 #define QIXIS_LBMAP_SHIFT 0 321 #define QIXIS_LBMAP_DFLTBANK 0x00 322 #define QIXIS_LBMAP_ALTBANK 0x04 323 #define QIXIS_RST_CTL_RESET 0x31 324 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 325 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 326 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 327 #define QIXIS_RST_FORCE_MEM 0x01 328 329 #define CONFIG_SYS_CSPR3_EXT (0xf) 330 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 331 | CSPR_PORT_SIZE_8 \ 332 | CSPR_MSEL_GPCM \ 333 | CSPR_V) 334 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 335 #define CONFIG_SYS_CSOR3 0x0 336 /* QIXIS Timing parameters for IFC CS3 */ 337 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 338 FTIM0_GPCM_TEADC(0x0e) | \ 339 FTIM0_GPCM_TEAHC(0x0e)) 340 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 341 FTIM1_GPCM_TRAD(0x3f)) 342 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 343 FTIM2_GPCM_TCH(0x8) | \ 344 FTIM2_GPCM_TWP(0x1f)) 345 #define CONFIG_SYS_CS3_FTIM3 0x0 346 347 #define CONFIG_NAND_FSL_IFC 348 #define CONFIG_SYS_NAND_BASE 0xff800000 349 #ifdef CONFIG_PHYS_64BIT 350 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 351 #else 352 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 353 #endif 354 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 355 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 356 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 357 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 358 | CSPR_V) 359 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 360 361 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 362 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 363 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 364 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 365 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 366 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 367 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 368 369 #define CONFIG_SYS_NAND_ONFI_DETECTION 370 371 /* ONFI NAND Flash mode0 Timing Params */ 372 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 373 FTIM0_NAND_TWP(0x18) | \ 374 FTIM0_NAND_TWCHT(0x07) | \ 375 FTIM0_NAND_TWH(0x0a)) 376 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 377 FTIM1_NAND_TWBE(0x39) | \ 378 FTIM1_NAND_TRR(0x0e) | \ 379 FTIM1_NAND_TRP(0x18)) 380 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 381 FTIM2_NAND_TREH(0x0a) | \ 382 FTIM2_NAND_TWHRE(0x1e)) 383 #define CONFIG_SYS_NAND_FTIM3 0x0 384 385 #define CONFIG_SYS_NAND_DDR_LAW 11 386 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 387 #define CONFIG_SYS_MAX_NAND_DEVICE 1 388 #define CONFIG_CMD_NAND 389 390 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 391 392 #if defined(CONFIG_NAND) 393 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 394 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 395 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 396 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 397 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 398 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 399 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 400 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 401 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 402 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 403 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 404 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 405 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 406 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 407 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 408 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 409 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 410 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 411 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 412 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 413 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 414 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 415 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 416 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 417 #else 418 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 419 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 420 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 421 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 422 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 423 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 424 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 425 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 426 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 427 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 428 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 429 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 430 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 431 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 432 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 433 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 434 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 435 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 436 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 437 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 438 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 439 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 440 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 441 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 442 #endif 443 444 #ifdef CONFIG_SPL_BUILD 445 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 446 #else 447 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 448 #endif 449 450 #if defined(CONFIG_RAMBOOT_PBL) 451 #define CONFIG_SYS_RAMBOOT 452 #endif 453 454 #define CONFIG_BOARD_EARLY_INIT_R 455 #define CONFIG_MISC_INIT_R 456 457 #define CONFIG_HWCONFIG 458 459 /* define to use L1 as initial stack */ 460 #define CONFIG_L1_INIT_RAM 461 #define CONFIG_SYS_INIT_RAM_LOCK 462 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 463 #ifdef CONFIG_PHYS_64BIT 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 466 /* The assembler doesn't like typecast */ 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 468 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 469 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 470 #else 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 474 #endif 475 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 476 477 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 478 GENERATED_GBL_DATA_SIZE) 479 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 480 481 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 482 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 483 484 /* Serial Port */ 485 #define CONFIG_CONS_INDEX 1 486 #define CONFIG_SYS_NS16550_SERIAL 487 #define CONFIG_SYS_NS16550_REG_SIZE 1 488 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 489 490 #define CONFIG_SYS_BAUDRATE_TABLE \ 491 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 492 493 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 494 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 495 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 496 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 497 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 498 499 /* Video */ 500 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 501 #define CONFIG_FSL_DIU_FB 502 #ifdef CONFIG_FSL_DIU_FB 503 #define CONFIG_FSL_DIU_CH7301 504 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 505 #define CONFIG_VIDEO 506 #define CONFIG_CMD_BMP 507 #define CONFIG_CFB_CONSOLE 508 #define CONFIG_VIDEO_SW_CURSOR 509 #define CONFIG_VGA_AS_SINGLE_DEVICE 510 #define CONFIG_VIDEO_LOGO 511 #define CONFIG_VIDEO_BMP_LOGO 512 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 513 /* 514 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 515 * disable empty flash sector detection, which is I/O-intensive. 516 */ 517 #undef CONFIG_SYS_FLASH_EMPTY_INFO 518 #endif 519 #endif 520 521 /* I2C */ 522 #define CONFIG_SYS_I2C 523 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 524 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 525 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 526 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 527 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 528 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 529 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 530 531 #define I2C_MUX_PCA_ADDR 0x77 532 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 533 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 534 #define I2C_RETIMER_ADDR 0x18 535 536 /* I2C bus multiplexer */ 537 #define I2C_MUX_CH_DEFAULT 0x8 538 #define I2C_MUX_CH_DIU 0xC 539 #define I2C_MUX_CH5 0xD 540 #define I2C_MUX_CH7 0xF 541 542 /* LDI/DVI Encoder for display */ 543 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 544 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 545 546 /* 547 * RTC configuration 548 */ 549 #define RTC 550 #define CONFIG_RTC_DS3231 1 551 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 552 553 /* 554 * eSPI - Enhanced SPI 555 */ 556 #ifndef CONFIG_SPL_BUILD 557 #endif 558 #define CONFIG_SPI_FLASH_BAR 559 #define CONFIG_SF_DEFAULT_SPEED 10000000 560 #define CONFIG_SF_DEFAULT_MODE 0 561 562 /* 563 * General PCIe 564 * Memory space is mapped 1-1, but I/O space must start from 0. 565 */ 566 #define CONFIG_PCI /* Enable PCI/PCIE */ 567 #define CONFIG_PCIE1 /* PCIE controller 1 */ 568 #define CONFIG_PCIE2 /* PCIE controller 2 */ 569 #define CONFIG_PCIE3 /* PCIE controller 3 */ 570 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 571 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 572 #define CONFIG_PCI_INDIRECT_BRIDGE 573 574 #ifdef CONFIG_PCI 575 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 576 #ifdef CONFIG_PCIE1 577 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 578 #ifdef CONFIG_PHYS_64BIT 579 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 580 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 581 #else 582 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 583 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 584 #endif 585 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 586 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 587 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 588 #ifdef CONFIG_PHYS_64BIT 589 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 590 #else 591 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 592 #endif 593 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 594 #endif 595 596 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 597 #ifdef CONFIG_PCIE2 598 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 601 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 602 #else 603 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 604 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 605 #endif 606 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 607 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 608 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 609 #ifdef CONFIG_PHYS_64BIT 610 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 611 #else 612 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 613 #endif 614 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 615 #endif 616 617 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 618 #ifdef CONFIG_PCIE3 619 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 622 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 623 #else 624 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 625 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 626 #endif 627 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 628 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 629 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 630 #ifdef CONFIG_PHYS_64BIT 631 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 632 #else 633 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 634 #endif 635 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 636 #endif 637 638 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 639 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 640 #define CONFIG_DOS_PARTITION 641 #endif /* CONFIG_PCI */ 642 643 /* 644 *SATA 645 */ 646 #define CONFIG_FSL_SATA_V2 647 #ifdef CONFIG_FSL_SATA_V2 648 #define CONFIG_LIBATA 649 #define CONFIG_FSL_SATA 650 #define CONFIG_SYS_SATA_MAX_DEVICE 1 651 #define CONFIG_SATA1 652 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 653 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 654 #define CONFIG_LBA48 655 #define CONFIG_CMD_SATA 656 #define CONFIG_DOS_PARTITION 657 #endif 658 659 /* 660 * USB 661 */ 662 #define CONFIG_HAS_FSL_DR_USB 663 664 #ifdef CONFIG_HAS_FSL_DR_USB 665 #define CONFIG_USB_EHCI 666 #define CONFIG_USB_EHCI_FSL 667 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 668 #endif 669 670 /* 671 * SDHC 672 */ 673 #define CONFIG_MMC 674 #ifdef CONFIG_MMC 675 #define CONFIG_FSL_ESDHC 676 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 677 #define CONFIG_GENERIC_MMC 678 #define CONFIG_DOS_PARTITION 679 #endif 680 681 /* Qman/Bman */ 682 #ifndef CONFIG_NOBQFMAN 683 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 684 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 685 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 686 #ifdef CONFIG_PHYS_64BIT 687 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 688 #else 689 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 690 #endif 691 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 692 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 693 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 694 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 695 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 696 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 697 CONFIG_SYS_BMAN_CENA_SIZE) 698 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 699 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 700 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 701 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 702 #ifdef CONFIG_PHYS_64BIT 703 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 704 #else 705 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 706 #endif 707 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 708 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 709 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 710 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 711 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 712 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 713 CONFIG_SYS_QMAN_CENA_SIZE) 714 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 715 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 716 717 #define CONFIG_SYS_DPAA_FMAN 718 719 #define CONFIG_QE 720 #define CONFIG_U_QE 721 /* Default address of microcode for the Linux FMan driver */ 722 #if defined(CONFIG_SPIFLASH) 723 /* 724 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 725 * env, so we got 0x110000. 726 */ 727 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 728 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 729 #define CONFIG_SYS_QE_FW_ADDR 0x130000 730 #elif defined(CONFIG_SDCARD) 731 /* 732 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 733 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 734 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 735 */ 736 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 737 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 738 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 739 #elif defined(CONFIG_NAND) 740 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 741 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 742 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 743 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 744 /* 745 * Slave has no ucode locally, it can fetch this from remote. When implementing 746 * in two corenet boards, slave's ucode could be stored in master's memory 747 * space, the address can be mapped from slave TLB->slave LAW-> 748 * slave SRIO or PCIE outbound window->master inbound window-> 749 * master LAW->the ucode address in master's memory space. 750 */ 751 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 752 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 753 #else 754 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 755 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 756 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 757 #endif 758 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 759 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 760 #endif /* CONFIG_NOBQFMAN */ 761 762 #ifdef CONFIG_SYS_DPAA_FMAN 763 #define CONFIG_FMAN_ENET 764 #define CONFIG_PHYLIB_10G 765 #define CONFIG_PHY_VITESSE 766 #define CONFIG_PHY_REALTEK 767 #define CONFIG_PHY_TERANETICS 768 #define RGMII_PHY1_ADDR 0x1 769 #define RGMII_PHY2_ADDR 0x2 770 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 771 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 772 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 773 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 774 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 775 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 776 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 777 #endif 778 779 #ifdef CONFIG_FMAN_ENET 780 #define CONFIG_MII /* MII PHY management */ 781 #define CONFIG_ETHPRIME "FM1@DTSEC4" 782 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 783 #endif 784 785 /* 786 * Dynamic MTD Partition support with mtdparts 787 */ 788 #ifndef CONFIG_SYS_NO_FLASH 789 #define CONFIG_MTD_DEVICE 790 #define CONFIG_MTD_PARTITIONS 791 #define CONFIG_CMD_MTDPARTS 792 #define CONFIG_FLASH_CFI_MTD 793 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 794 "spi0=spife110000.0" 795 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 796 "128k(dtb),96m(fs),-(user);"\ 797 "fff800000.flash:2m(uboot),9m(kernel),"\ 798 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 799 "2m(uboot),9m(kernel),128k(dtb),-(user)" 800 #endif 801 802 /* 803 * Environment 804 */ 805 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 806 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 807 808 /* 809 * Command line configuration. 810 */ 811 #define CONFIG_CMD_DATE 812 #define CONFIG_CMD_EEPROM 813 #define CONFIG_CMD_ERRATA 814 #define CONFIG_CMD_IRQ 815 #define CONFIG_CMD_REGINFO 816 817 #ifdef CONFIG_PCI 818 #define CONFIG_CMD_PCI 819 #endif 820 821 /* 822 * Miscellaneous configurable options 823 */ 824 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 825 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 826 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 827 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 828 #ifdef CONFIG_CMD_KGDB 829 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 830 #else 831 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 832 #endif 833 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 834 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 835 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 836 837 /* 838 * For booting Linux, the board info and command line data 839 * have to be in the first 64 MB of memory, since this is 840 * the maximum mapped by the Linux kernel during initialization. 841 */ 842 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 843 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 844 845 #ifdef CONFIG_CMD_KGDB 846 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 847 #endif 848 849 /* 850 * Environment Configuration 851 */ 852 #define CONFIG_ROOTPATH "/opt/nfsroot" 853 #define CONFIG_BOOTFILE "uImage" 854 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 855 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 856 #define CONFIG_BAUDRATE 115200 857 #define __USB_PHY_TYPE utmi 858 859 #define CONFIG_EXTRA_ENV_SETTINGS \ 860 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 861 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 862 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 863 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 864 "fdtfile=t1024qds/t1024qds.dtb\0" \ 865 "netdev=eth0\0" \ 866 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 867 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 868 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 869 "tftpflash=tftpboot $loadaddr $uboot && " \ 870 "protect off $ubootaddr +$filesize && " \ 871 "erase $ubootaddr +$filesize && " \ 872 "cp.b $loadaddr $ubootaddr $filesize && " \ 873 "protect on $ubootaddr +$filesize && " \ 874 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 875 "consoledev=ttyS0\0" \ 876 "ramdiskaddr=2000000\0" \ 877 "fdtaddr=d00000\0" \ 878 "bdev=sda3\0" 879 880 #define CONFIG_LINUX \ 881 "setenv bootargs root=/dev/ram rw " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "setenv ramdiskaddr 0x02000000;" \ 884 "setenv fdtaddr 0x00c00000;" \ 885 "setenv loadaddr 0x1000000;" \ 886 "bootm $loadaddr $ramdiskaddr $fdtaddr" 887 888 #define CONFIG_NFSBOOTCOMMAND \ 889 "setenv bootargs root=/dev/nfs rw " \ 890 "nfsroot=$serverip:$rootpath " \ 891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 892 "console=$consoledev,$baudrate $othbootargs;" \ 893 "tftp $loadaddr $bootfile;" \ 894 "tftp $fdtaddr $fdtfile;" \ 895 "bootm $loadaddr - $fdtaddr" 896 897 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 898 899 /* Hash command with SHA acceleration supported in hardware */ 900 #ifdef CONFIG_FSL_CAAM 901 #define CONFIG_CMD_HASH 902 #define CONFIG_SHA_HW_ACCEL 903 #endif 904 905 #include <asm/fsl_secure_boot.h> 906 907 #endif /* __T1024QDS_H */ 908