xref: /openbmc/u-boot/include/configs/T102xQDS.h (revision 4de512018ba7d57f1672be21c7459281f7c97514)
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 /*
8  * T1024/T1023 QDS board configuration file
9  */
10 
11 #ifndef __T1024QDS_H
12 #define __T1024QDS_H
13 
14 /* High Level Configuration Options */
15 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
16 #define CONFIG_MP			/* support multiple processors */
17 #define CONFIG_ENABLE_36BIT_PHYS
18 
19 #ifdef CONFIG_PHYS_64BIT
20 #define CONFIG_ADDR_MAP		1
21 #define CONFIG_SYS_NUM_ADDR_MAP	64	/* number of TLB1 entries */
22 #endif
23 
24 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
25 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
26 
27 #define CONFIG_ENV_OVERWRITE
28 
29 #define CONFIG_DEEP_SLEEP
30 
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
35 #define CONFIG_SYS_TEXT_BASE		0x00201000
36 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
37 #define CONFIG_SPL_PAD_TO		0x40000
38 #define CONFIG_SPL_MAX_SIZE		0x28000
39 #define RESET_VECTOR_OFFSET		0x27FFC
40 #define BOOT_PAGE_OFFSET		0x27000
41 #ifdef CONFIG_SPL_BUILD
42 #define CONFIG_SPL_SKIP_RELOCATE
43 #define CONFIG_SPL_COMMON_INIT_DDR
44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
45 #endif
46 
47 #ifdef CONFIG_NAND
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
52 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
54 #define CONFIG_SPL_NAND_BOOT
55 #endif
56 
57 #ifdef CONFIG_SPIFLASH
58 #define CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
59 #define CONFIG_SPL_SPI_FLASH_MINIMAL
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
64 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
65 #ifndef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
67 #endif
68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
69 #define CONFIG_SPL_SPI_BOOT
70 #endif
71 
72 #ifdef CONFIG_SDCARD
73 #define CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
74 #define CONFIG_SPL_MMC_MINIMAL
75 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
76 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
77 #define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
78 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
79 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
80 #ifndef CONFIG_SPL_BUILD
81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
82 #endif
83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
84 #define CONFIG_SPL_MMC_BOOT
85 #endif
86 
87 #endif /* CONFIG_RAMBOOT_PBL */
88 
89 #ifndef CONFIG_SYS_TEXT_BASE
90 #define CONFIG_SYS_TEXT_BASE	0xeff40000
91 #endif
92 
93 #ifndef CONFIG_RESET_VECTOR_ADDRESS
94 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
95 #endif
96 
97 #ifdef CONFIG_MTD_NOR_FLASH
98 #define CONFIG_FLASH_CFI_DRIVER
99 #define CONFIG_SYS_FLASH_CFI
100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
101 #endif
102 
103 /* PCIe Boot - Master */
104 #define CONFIG_SRIO_PCIE_BOOT_MASTER
105 /*
106  * for slave u-boot IMAGE instored in master memory space,
107  * PHYS must be aligned based on the SIZE
108  */
109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
111 #ifdef CONFIG_PHYS_64BIT
112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
114 #else
115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
117 #endif
118 /*
119  * for slave UCODE and ENV instored in master memory space,
120  * PHYS must be aligned based on the SIZE
121  */
122 #ifdef CONFIG_PHYS_64BIT
123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
125 #else
126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
128 #endif
129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
130 /* slave core release by master*/
131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
133 
134 /* PCIe Boot - Slave */
135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
137 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
138 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
139 /* Set 1M boot space for PCIe boot */
140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
141 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
142 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
144 #endif
145 
146 #if defined(CONFIG_SPIFLASH)
147 #define CONFIG_SYS_EXTRA_ENV_RELOC
148 #define CONFIG_ENV_SPI_BUS		0
149 #define CONFIG_ENV_SPI_CS		0
150 #define CONFIG_ENV_SPI_MAX_HZ		10000000
151 #define CONFIG_ENV_SPI_MODE		0
152 #define CONFIG_ENV_SIZE			0x2000		/* 8KB */
153 #define CONFIG_ENV_OFFSET		0x100000	/* 1MB */
154 #define CONFIG_ENV_SECT_SIZE		0x10000
155 #elif defined(CONFIG_SDCARD)
156 #define CONFIG_SYS_EXTRA_ENV_RELOC
157 #define CONFIG_SYS_MMC_ENV_DEV		0
158 #define CONFIG_ENV_SIZE			0x2000
159 #define CONFIG_ENV_OFFSET		(512 * 0x800)
160 #elif defined(CONFIG_NAND)
161 #define CONFIG_SYS_EXTRA_ENV_RELOC
162 #define CONFIG_ENV_SIZE			0x2000
163 #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
164 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
165 #define CONFIG_ENV_ADDR		0xffe20000
166 #define CONFIG_ENV_SIZE		0x2000
167 #elif defined(CONFIG_ENV_IS_NOWHERE)
168 #define CONFIG_ENV_SIZE		0x2000
169 #else
170 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
171 #define CONFIG_ENV_SIZE		0x2000
172 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
173 #endif
174 
175 #ifndef __ASSEMBLY__
176 unsigned long get_board_sys_clk(void);
177 unsigned long get_board_ddr_clk(void);
178 #endif
179 
180 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
181 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
182 
183 /*
184  * These can be toggled for performance analysis, otherwise use default.
185  */
186 #define CONFIG_SYS_CACHE_STASHING
187 #define CONFIG_BACKSIDE_L2_CACHE
188 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
189 #define CONFIG_BTB			/* toggle branch predition */
190 #define CONFIG_DDR_ECC
191 #ifdef CONFIG_DDR_ECC
192 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
193 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
194 #endif
195 
196 #define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
197 #define CONFIG_SYS_MEMTEST_END		0x00400000
198 #define CONFIG_SYS_ALT_MEMTEST
199 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
200 
201 /*
202  *  Config the L3 Cache as L3 SRAM
203  */
204 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
205 #define CONFIG_SYS_L3_SIZE		(256 << 10)
206 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
207 #ifdef CONFIG_RAMBOOT_PBL
208 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
209 #endif
210 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
211 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
212 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
213 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
214 
215 #ifdef CONFIG_PHYS_64BIT
216 #define CONFIG_SYS_DCSRBAR		0xf0000000
217 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
218 #endif
219 
220 /* EEPROM */
221 #define CONFIG_ID_EEPROM
222 #define CONFIG_SYS_I2C_EEPROM_NXID
223 #define CONFIG_SYS_EEPROM_BUS_NUM	0
224 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
225 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
228 
229 /*
230  * DDR Setup
231  */
232 #define CONFIG_VERY_BIG_RAM
233 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
234 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
235 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
236 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
237 #define CONFIG_DDR_SPD
238 
239 #define CONFIG_SYS_SPD_BUS_NUM	0
240 #define SPD_EEPROM_ADDRESS	0x51
241 
242 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
243 
244 /*
245  * IFC Definitions
246  */
247 #define CONFIG_SYS_FLASH_BASE	0xe0000000
248 #ifdef CONFIG_PHYS_64BIT
249 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
250 #else
251 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
252 #endif
253 
254 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
255 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
256 				+ 0x8000000) | \
257 				CSPR_PORT_SIZE_16 | \
258 				CSPR_MSEL_NOR | \
259 				CSPR_V)
260 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
261 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
262 				CSPR_PORT_SIZE_16 | \
263 				CSPR_MSEL_NOR | \
264 				CSPR_V)
265 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
266 /* NOR Flash Timing Params */
267 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
268 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
269 				FTIM0_NOR_TEADC(0x5) | \
270 				FTIM0_NOR_TEAHC(0x5))
271 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
272 				FTIM1_NOR_TRAD_NOR(0x1A) |\
273 				FTIM1_NOR_TSEQRAD_NOR(0x13))
274 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
275 				FTIM2_NOR_TCH(0x4) | \
276 				FTIM2_NOR_TWPH(0x0E) | \
277 				FTIM2_NOR_TWP(0x1c))
278 #define CONFIG_SYS_NOR_FTIM3	0x0
279 
280 #define CONFIG_SYS_FLASH_QUIET_TEST
281 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
282 
283 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
284 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
285 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
286 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
287 
288 #define CONFIG_SYS_FLASH_EMPTY_INFO
289 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
290 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
291 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
292 #define QIXIS_BASE		0xffdf0000
293 #ifdef CONFIG_PHYS_64BIT
294 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
295 #else
296 #define QIXIS_BASE_PHYS		QIXIS_BASE
297 #endif
298 #define QIXIS_LBMAP_SWITCH		0x06
299 #define QIXIS_LBMAP_MASK		0x0f
300 #define QIXIS_LBMAP_SHIFT		0
301 #define QIXIS_LBMAP_DFLTBANK		0x00
302 #define QIXIS_LBMAP_ALTBANK		0x04
303 #define QIXIS_RST_CTL_RESET		0x31
304 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
305 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
306 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
307 #define	QIXIS_RST_FORCE_MEM		0x01
308 
309 #define CONFIG_SYS_CSPR3_EXT	(0xf)
310 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
311 				| CSPR_PORT_SIZE_8 \
312 				| CSPR_MSEL_GPCM \
313 				| CSPR_V)
314 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
315 #define CONFIG_SYS_CSOR3	0x0
316 /* QIXIS Timing parameters for IFC CS3 */
317 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
318 					FTIM0_GPCM_TEADC(0x0e) | \
319 					FTIM0_GPCM_TEAHC(0x0e))
320 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
321 					FTIM1_GPCM_TRAD(0x3f))
322 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
323 					FTIM2_GPCM_TCH(0x8) | \
324 					FTIM2_GPCM_TWP(0x1f))
325 #define CONFIG_SYS_CS3_FTIM3		0x0
326 
327 #define CONFIG_NAND_FSL_IFC
328 #define CONFIG_SYS_NAND_BASE		0xff800000
329 #ifdef CONFIG_PHYS_64BIT
330 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
331 #else
332 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
333 #endif
334 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
335 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
336 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
337 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
338 				| CSPR_V)
339 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
340 
341 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
342 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
343 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
344 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
345 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
346 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
347 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
348 
349 #define CONFIG_SYS_NAND_ONFI_DETECTION
350 
351 /* ONFI NAND Flash mode0 Timing Params */
352 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
353 					FTIM0_NAND_TWP(0x18)   | \
354 					FTIM0_NAND_TWCHT(0x07) | \
355 					FTIM0_NAND_TWH(0x0a))
356 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
357 					FTIM1_NAND_TWBE(0x39)  | \
358 					FTIM1_NAND_TRR(0x0e)   | \
359 					FTIM1_NAND_TRP(0x18))
360 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
361 					FTIM2_NAND_TREH(0x0a) | \
362 					FTIM2_NAND_TWHRE(0x1e))
363 #define CONFIG_SYS_NAND_FTIM3		0x0
364 
365 #define CONFIG_SYS_NAND_DDR_LAW		11
366 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
367 #define CONFIG_SYS_MAX_NAND_DEVICE	1
368 #define CONFIG_CMD_NAND
369 
370 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
371 
372 #if defined(CONFIG_NAND)
373 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
374 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
375 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
376 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
377 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
378 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
379 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
380 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
381 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
382 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
383 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
384 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
385 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
386 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
387 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
388 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
389 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
390 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
391 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
392 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
393 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
394 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
395 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
396 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
397 #else
398 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
399 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
400 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
401 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
402 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
403 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
404 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
405 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
406 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
407 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
408 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
409 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
410 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
411 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
412 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
413 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
414 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
415 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
416 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
417 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
418 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
419 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
420 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
421 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
422 #endif
423 
424 #ifdef CONFIG_SPL_BUILD
425 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
426 #else
427 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
428 #endif
429 
430 #if defined(CONFIG_RAMBOOT_PBL)
431 #define CONFIG_SYS_RAMBOOT
432 #endif
433 
434 #define CONFIG_BOARD_EARLY_INIT_R
435 #define CONFIG_MISC_INIT_R
436 
437 #define CONFIG_HWCONFIG
438 
439 /* define to use L1 as initial stack */
440 #define CONFIG_L1_INIT_RAM
441 #define CONFIG_SYS_INIT_RAM_LOCK
442 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
443 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
446 /* The assembler doesn't like typecast */
447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
448 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
449 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
450 #else
451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
454 #endif
455 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
456 
457 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
458 					GENERATED_GBL_DATA_SIZE)
459 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
460 
461 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
462 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
463 
464 /* Serial Port */
465 #define CONFIG_CONS_INDEX	1
466 #define CONFIG_SYS_NS16550_SERIAL
467 #define CONFIG_SYS_NS16550_REG_SIZE	1
468 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
469 
470 #define CONFIG_SYS_BAUDRATE_TABLE	\
471 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
472 
473 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
474 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
475 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
476 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
477 
478 /* Video */
479 #ifdef CONFIG_ARCH_T1024		/* no DIU on T1023 */
480 #define CONFIG_FSL_DIU_FB
481 #ifdef CONFIG_FSL_DIU_FB
482 #define CONFIG_FSL_DIU_CH7301
483 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
484 #define CONFIG_VIDEO_LOGO
485 #define CONFIG_VIDEO_BMP_LOGO
486 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
487 /*
488  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
489  * disable empty flash sector detection, which is I/O-intensive.
490  */
491 #undef CONFIG_SYS_FLASH_EMPTY_INFO
492 #endif
493 #endif
494 
495 /* I2C */
496 #define CONFIG_SYS_I2C
497 #define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
498 #define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
499 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
500 #define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
501 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
502 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
503 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
504 
505 #define I2C_MUX_PCA_ADDR		0x77
506 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
507 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
508 #define I2C_RETIMER_ADDR		0x18
509 
510 /* I2C bus multiplexer */
511 #define I2C_MUX_CH_DEFAULT      0x8
512 #define I2C_MUX_CH_DIU		0xC
513 #define I2C_MUX_CH5		0xD
514 #define I2C_MUX_CH7		0xF
515 
516 /* LDI/DVI Encoder for display */
517 #define CONFIG_SYS_I2C_LDI_ADDR	 0x38
518 #define CONFIG_SYS_I2C_DVI_ADDR	 0x75
519 
520 /*
521  * RTC configuration
522  */
523 #define RTC
524 #define CONFIG_RTC_DS3231	1
525 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
526 
527 /*
528  * eSPI - Enhanced SPI
529  */
530 #ifndef CONFIG_SPL_BUILD
531 #endif
532 #define CONFIG_SPI_FLASH_BAR
533 #define CONFIG_SF_DEFAULT_SPEED	 10000000
534 #define CONFIG_SF_DEFAULT_MODE	  0
535 
536 /*
537  * General PCIe
538  * Memory space is mapped 1-1, but I/O space must start from 0.
539  */
540 #define CONFIG_PCIE1		/* PCIE controller 1 */
541 #define CONFIG_PCIE2		/* PCIE controller 2 */
542 #define CONFIG_PCIE3		/* PCIE controller 3 */
543 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
544 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
545 #define CONFIG_PCI_INDIRECT_BRIDGE
546 
547 #ifdef CONFIG_PCI
548 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
549 #ifdef CONFIG_PCIE1
550 #define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
551 #ifdef CONFIG_PHYS_64BIT
552 #define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
553 #define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
554 #else
555 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
556 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
557 #endif
558 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
559 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
560 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
561 #ifdef CONFIG_PHYS_64BIT
562 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
563 #else
564 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
565 #endif
566 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
567 #endif
568 
569 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
570 #ifdef CONFIG_PCIE2
571 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
572 #ifdef CONFIG_PHYS_64BIT
573 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
574 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
575 #else
576 #define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
577 #define CONFIG_SYS_PCIE2_MEM_PHYS	0x90000000
578 #endif
579 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
580 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
581 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
582 #ifdef CONFIG_PHYS_64BIT
583 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
584 #else
585 #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
586 #endif
587 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
588 #endif
589 
590 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
591 #ifdef CONFIG_PCIE3
592 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
593 #ifdef CONFIG_PHYS_64BIT
594 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
595 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
596 #else
597 #define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
598 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
599 #endif
600 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
601 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
602 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
603 #ifdef CONFIG_PHYS_64BIT
604 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
605 #else
606 #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
607 #endif
608 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
609 #endif
610 
611 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
612 #endif	/* CONFIG_PCI */
613 
614 /*
615  *SATA
616  */
617 #define CONFIG_FSL_SATA_V2
618 #ifdef CONFIG_FSL_SATA_V2
619 #define CONFIG_LIBATA
620 #define CONFIG_FSL_SATA
621 #define CONFIG_SYS_SATA_MAX_DEVICE	1
622 #define CONFIG_SATA1
623 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
624 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
625 #define CONFIG_LBA48
626 #endif
627 
628 /*
629  * USB
630  */
631 #define CONFIG_HAS_FSL_DR_USB
632 
633 #ifdef CONFIG_HAS_FSL_DR_USB
634 #define CONFIG_USB_EHCI_FSL
635 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
636 #endif
637 
638 /*
639  * SDHC
640  */
641 #ifdef CONFIG_MMC
642 #define CONFIG_FSL_ESDHC
643 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
644 #endif
645 
646 /* Qman/Bman */
647 #ifndef CONFIG_NOBQFMAN
648 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
649 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
650 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
651 #ifdef CONFIG_PHYS_64BIT
652 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
653 #else
654 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
655 #endif
656 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
657 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
658 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
659 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
660 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
661 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
662 					CONFIG_SYS_BMAN_CENA_SIZE)
663 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
664 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
665 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
666 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
667 #ifdef CONFIG_PHYS_64BIT
668 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
669 #else
670 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
671 #endif
672 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
673 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
674 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
675 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
676 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
677 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
678 					CONFIG_SYS_QMAN_CENA_SIZE)
679 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
680 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
681 
682 #define CONFIG_SYS_DPAA_FMAN
683 
684 #define CONFIG_QE
685 #define CONFIG_U_QE
686 /* Default address of microcode for the Linux FMan driver */
687 #if defined(CONFIG_SPIFLASH)
688 /*
689  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
690  * env, so we got 0x110000.
691  */
692 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
693 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
694 #define CONFIG_SYS_QE_FW_ADDR	0x130000
695 #elif defined(CONFIG_SDCARD)
696 /*
697  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
698  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
699  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
700  */
701 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
702 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
703 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
704 #elif defined(CONFIG_NAND)
705 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
706 #define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
707 #define CONFIG_SYS_QE_FW_ADDR		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
708 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
709 /*
710  * Slave has no ucode locally, it can fetch this from remote. When implementing
711  * in two corenet boards, slave's ucode could be stored in master's memory
712  * space, the address can be mapped from slave TLB->slave LAW->
713  * slave SRIO or PCIE outbound window->master inbound window->
714  * master LAW->the ucode address in master's memory space.
715  */
716 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
717 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
718 #else
719 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
720 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
721 #define CONFIG_SYS_QE_FW_ADDR		0xEFE00000
722 #endif
723 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
724 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
725 #endif /* CONFIG_NOBQFMAN */
726 
727 #ifdef CONFIG_SYS_DPAA_FMAN
728 #define CONFIG_FMAN_ENET
729 #define CONFIG_PHYLIB_10G
730 #define CONFIG_PHY_VITESSE
731 #define CONFIG_PHY_REALTEK
732 #define CONFIG_PHY_TERANETICS
733 #define RGMII_PHY1_ADDR		0x1
734 #define RGMII_PHY2_ADDR		0x2
735 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
736 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
737 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
738 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
739 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
740 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
741 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
742 #endif
743 
744 #ifdef CONFIG_FMAN_ENET
745 #define CONFIG_MII		/* MII PHY management */
746 #define CONFIG_ETHPRIME		"FM1@DTSEC4"
747 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
748 #endif
749 
750 /*
751  * Dynamic MTD Partition support with mtdparts
752  */
753 #ifdef CONFIG_MTD_NOR_FLASH
754 #define CONFIG_MTD_DEVICE
755 #define CONFIG_MTD_PARTITIONS
756 #define CONFIG_FLASH_CFI_MTD
757 #define MTDIDS_DEFAULT    "nor0=fe8000000.nor,nand0=fff800000.flash," \
758 			  "spi0=spife110000.0"
759 #define MTDPARTS_DEFAULT  "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
760 			  "128k(dtb),96m(fs),-(user);"\
761 			  "fff800000.flash:2m(uboot),9m(kernel),"\
762 			  "128k(dtb),96m(fs),-(user);spife110000.0:" \
763 			  "2m(uboot),9m(kernel),128k(dtb),-(user)"
764 #endif
765 
766 /*
767  * Environment
768  */
769 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
770 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
771 
772 /*
773  * Command line configuration.
774  */
775 #define CONFIG_CMD_REGINFO
776 
777 #ifdef CONFIG_PCI
778 #define CONFIG_CMD_PCI
779 #endif
780 
781 /*
782  * Miscellaneous configurable options
783  */
784 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
785 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
786 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
787 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
788 #ifdef CONFIG_CMD_KGDB
789 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
790 #else
791 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
792 #endif
793 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
794 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
795 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
796 
797 /*
798  * For booting Linux, the board info and command line data
799  * have to be in the first 64 MB of memory, since this is
800  * the maximum mapped by the Linux kernel during initialization.
801  */
802 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
803 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
804 
805 #ifdef CONFIG_CMD_KGDB
806 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
807 #endif
808 
809 /*
810  * Environment Configuration
811  */
812 #define CONFIG_ROOTPATH		"/opt/nfsroot"
813 #define CONFIG_BOOTFILE		"uImage"
814 #define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
815 #define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
816 #define __USB_PHY_TYPE		utmi
817 
818 #define	CONFIG_EXTRA_ENV_SETTINGS				\
819 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
820 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
821 	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
822 	"ramdiskfile=t1024qds/ramdisk.uboot\0"			\
823 	"fdtfile=t1024qds/t1024qds.dtb\0"			\
824 	"netdev=eth0\0"						\
825 	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
826 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
827 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
828 	"tftpflash=tftpboot $loadaddr $uboot && "		\
829 	"protect off $ubootaddr +$filesize && "			\
830 	"erase $ubootaddr +$filesize && "			\
831 	"cp.b $loadaddr $ubootaddr $filesize && "		\
832 	"protect on $ubootaddr +$filesize && "			\
833 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
834 	"consoledev=ttyS0\0"					\
835 	"ramdiskaddr=2000000\0"					\
836 	"fdtaddr=d00000\0"					\
837 	"bdev=sda3\0"
838 
839 #define CONFIG_LINUX					\
840 	"setenv bootargs root=/dev/ram rw "		\
841 	"console=$consoledev,$baudrate $othbootargs;"	\
842 	"setenv ramdiskaddr 0x02000000;"		\
843 	"setenv fdtaddr 0x00c00000;"			\
844 	"setenv loadaddr 0x1000000;"			\
845 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
846 
847 #define CONFIG_NFSBOOTCOMMAND			\
848 	"setenv bootargs root=/dev/nfs rw "	\
849 	"nfsroot=$serverip:$rootpath "		\
850 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
851 	"console=$consoledev,$baudrate $othbootargs;"	\
852 	"tftp $loadaddr $bootfile;"		\
853 	"tftp $fdtaddr $fdtfile;"		\
854 	"bootm $loadaddr - $fdtaddr"
855 
856 #define CONFIG_BOOTCOMMAND	CONFIG_LINUX
857 
858 #include <asm/fsl_secure_boot.h>
859 
860 #endif	/* __T1024QDS_H */
861