1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 #define CONFIG_DEEP_SLEEP 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 33 #define CONFIG_SPL_FLUSH_IMAGE 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 35 #define CONFIG_SYS_TEXT_BASE 0x00201000 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #define RESET_VECTOR_OFFSET 0x27FFC 40 #define BOOT_PAGE_OFFSET 0x27000 41 #ifdef CONFIG_SPL_BUILD 42 #define CONFIG_SPL_SKIP_RELOCATE 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 45 #endif 46 47 #ifdef CONFIG_NAND 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 54 #define CONFIG_SPL_NAND_BOOT 55 #endif 56 57 #ifdef CONFIG_SPIFLASH 58 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 59 #define CONFIG_SPL_SPI_FLASH_MINIMAL 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 65 #ifndef CONFIG_SPL_BUILD 66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 67 #endif 68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 69 #define CONFIG_SPL_SPI_BOOT 70 #endif 71 72 #ifdef CONFIG_SDCARD 73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 74 #define CONFIG_SPL_MMC_MINIMAL 75 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 76 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 77 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 78 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 80 #ifndef CONFIG_SPL_BUILD 81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 82 #endif 83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 84 #define CONFIG_SPL_MMC_BOOT 85 #endif 86 87 #endif /* CONFIG_RAMBOOT_PBL */ 88 89 #ifndef CONFIG_SYS_TEXT_BASE 90 #define CONFIG_SYS_TEXT_BASE 0xeff40000 91 #endif 92 93 #ifndef CONFIG_RESET_VECTOR_ADDRESS 94 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 95 #endif 96 97 #ifdef CONFIG_MTD_NOR_FLASH 98 #define CONFIG_FLASH_CFI_DRIVER 99 #define CONFIG_SYS_FLASH_CFI 100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 101 #endif 102 103 /* PCIe Boot - Master */ 104 #define CONFIG_SRIO_PCIE_BOOT_MASTER 105 /* 106 * for slave u-boot IMAGE instored in master memory space, 107 * PHYS must be aligned based on the SIZE 108 */ 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 111 #ifdef CONFIG_PHYS_64BIT 112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 114 #else 115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 117 #endif 118 /* 119 * for slave UCODE and ENV instored in master memory space, 120 * PHYS must be aligned based on the SIZE 121 */ 122 #ifdef CONFIG_PHYS_64BIT 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 125 #else 126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 128 #endif 129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 130 /* slave core release by master*/ 131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 133 134 /* PCIe Boot - Slave */ 135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 137 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 139 /* Set 1M boot space for PCIe boot */ 140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 141 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 144 #endif 145 146 #if defined(CONFIG_SPIFLASH) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_ENV_SPI_BUS 0 149 #define CONFIG_ENV_SPI_CS 0 150 #define CONFIG_ENV_SPI_MAX_HZ 10000000 151 #define CONFIG_ENV_SPI_MODE 0 152 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 153 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 154 #define CONFIG_ENV_SECT_SIZE 0x10000 155 #elif defined(CONFIG_SDCARD) 156 #define CONFIG_SYS_EXTRA_ENV_RELOC 157 #define CONFIG_SYS_MMC_ENV_DEV 0 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (512 * 0x800) 160 #elif defined(CONFIG_NAND) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 164 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 165 #define CONFIG_ENV_ADDR 0xffe20000 166 #define CONFIG_ENV_SIZE 0x2000 167 #elif defined(CONFIG_ENV_IS_NOWHERE) 168 #define CONFIG_ENV_SIZE 0x2000 169 #else 170 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 171 #define CONFIG_ENV_SIZE 0x2000 172 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 173 #endif 174 175 #ifndef __ASSEMBLY__ 176 unsigned long get_board_sys_clk(void); 177 unsigned long get_board_ddr_clk(void); 178 #endif 179 180 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 181 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 182 183 /* 184 * These can be toggled for performance analysis, otherwise use default. 185 */ 186 #define CONFIG_SYS_CACHE_STASHING 187 #define CONFIG_BACKSIDE_L2_CACHE 188 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 189 #define CONFIG_BTB /* toggle branch predition */ 190 #define CONFIG_DDR_ECC 191 #ifdef CONFIG_DDR_ECC 192 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 193 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 194 #endif 195 196 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 197 #define CONFIG_SYS_MEMTEST_END 0x00400000 198 #define CONFIG_SYS_ALT_MEMTEST 199 200 /* 201 * Config the L3 Cache as L3 SRAM 202 */ 203 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 204 #define CONFIG_SYS_L3_SIZE (256 << 10) 205 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 206 #ifdef CONFIG_RAMBOOT_PBL 207 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 208 #endif 209 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 210 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 211 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 212 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 213 214 #ifdef CONFIG_PHYS_64BIT 215 #define CONFIG_SYS_DCSRBAR 0xf0000000 216 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 217 #endif 218 219 /* EEPROM */ 220 #define CONFIG_ID_EEPROM 221 #define CONFIG_SYS_I2C_EEPROM_NXID 222 #define CONFIG_SYS_EEPROM_BUS_NUM 0 223 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 224 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 227 228 /* 229 * DDR Setup 230 */ 231 #define CONFIG_VERY_BIG_RAM 232 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 233 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 234 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 235 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 236 #define CONFIG_DDR_SPD 237 238 #define CONFIG_SYS_SPD_BUS_NUM 0 239 #define SPD_EEPROM_ADDRESS 0x51 240 241 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 242 243 /* 244 * IFC Definitions 245 */ 246 #define CONFIG_SYS_FLASH_BASE 0xe0000000 247 #ifdef CONFIG_PHYS_64BIT 248 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 249 #else 250 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 251 #endif 252 253 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 254 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 255 + 0x8000000) | \ 256 CSPR_PORT_SIZE_16 | \ 257 CSPR_MSEL_NOR | \ 258 CSPR_V) 259 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 261 CSPR_PORT_SIZE_16 | \ 262 CSPR_MSEL_NOR | \ 263 CSPR_V) 264 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 265 /* NOR Flash Timing Params */ 266 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 267 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 268 FTIM0_NOR_TEADC(0x5) | \ 269 FTIM0_NOR_TEAHC(0x5)) 270 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 271 FTIM1_NOR_TRAD_NOR(0x1A) |\ 272 FTIM1_NOR_TSEQRAD_NOR(0x13)) 273 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 274 FTIM2_NOR_TCH(0x4) | \ 275 FTIM2_NOR_TWPH(0x0E) | \ 276 FTIM2_NOR_TWP(0x1c)) 277 #define CONFIG_SYS_NOR_FTIM3 0x0 278 279 #define CONFIG_SYS_FLASH_QUIET_TEST 280 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 281 282 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 283 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 284 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 285 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 286 287 #define CONFIG_SYS_FLASH_EMPTY_INFO 288 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 289 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 290 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 291 #define QIXIS_BASE 0xffdf0000 292 #ifdef CONFIG_PHYS_64BIT 293 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 294 #else 295 #define QIXIS_BASE_PHYS QIXIS_BASE 296 #endif 297 #define QIXIS_LBMAP_SWITCH 0x06 298 #define QIXIS_LBMAP_MASK 0x0f 299 #define QIXIS_LBMAP_SHIFT 0 300 #define QIXIS_LBMAP_DFLTBANK 0x00 301 #define QIXIS_LBMAP_ALTBANK 0x04 302 #define QIXIS_RST_CTL_RESET 0x31 303 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 304 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 305 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 306 #define QIXIS_RST_FORCE_MEM 0x01 307 308 #define CONFIG_SYS_CSPR3_EXT (0xf) 309 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 310 | CSPR_PORT_SIZE_8 \ 311 | CSPR_MSEL_GPCM \ 312 | CSPR_V) 313 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 314 #define CONFIG_SYS_CSOR3 0x0 315 /* QIXIS Timing parameters for IFC CS3 */ 316 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 317 FTIM0_GPCM_TEADC(0x0e) | \ 318 FTIM0_GPCM_TEAHC(0x0e)) 319 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 320 FTIM1_GPCM_TRAD(0x3f)) 321 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 322 FTIM2_GPCM_TCH(0x8) | \ 323 FTIM2_GPCM_TWP(0x1f)) 324 #define CONFIG_SYS_CS3_FTIM3 0x0 325 326 #define CONFIG_NAND_FSL_IFC 327 #define CONFIG_SYS_NAND_BASE 0xff800000 328 #ifdef CONFIG_PHYS_64BIT 329 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 330 #else 331 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 332 #endif 333 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 334 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 335 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 336 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 337 | CSPR_V) 338 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 339 340 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 341 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 342 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 343 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 344 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 345 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 346 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 347 348 #define CONFIG_SYS_NAND_ONFI_DETECTION 349 350 /* ONFI NAND Flash mode0 Timing Params */ 351 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 352 FTIM0_NAND_TWP(0x18) | \ 353 FTIM0_NAND_TWCHT(0x07) | \ 354 FTIM0_NAND_TWH(0x0a)) 355 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 356 FTIM1_NAND_TWBE(0x39) | \ 357 FTIM1_NAND_TRR(0x0e) | \ 358 FTIM1_NAND_TRP(0x18)) 359 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 360 FTIM2_NAND_TREH(0x0a) | \ 361 FTIM2_NAND_TWHRE(0x1e)) 362 #define CONFIG_SYS_NAND_FTIM3 0x0 363 364 #define CONFIG_SYS_NAND_DDR_LAW 11 365 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 366 #define CONFIG_SYS_MAX_NAND_DEVICE 1 367 368 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 369 370 #if defined(CONFIG_NAND) 371 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 372 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 373 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 374 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 375 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 376 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 377 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 378 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 379 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 380 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 381 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 382 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 383 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 384 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 385 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 386 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 387 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 388 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 389 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 390 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 391 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 392 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 393 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 394 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 395 #else 396 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 397 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 398 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 399 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 400 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 401 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 402 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 403 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 404 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 405 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 406 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 407 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 408 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 409 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 410 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 411 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 412 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 413 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 414 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 415 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 416 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 417 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 418 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 419 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 420 #endif 421 422 #ifdef CONFIG_SPL_BUILD 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 424 #else 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 426 #endif 427 428 #if defined(CONFIG_RAMBOOT_PBL) 429 #define CONFIG_SYS_RAMBOOT 430 #endif 431 432 #define CONFIG_BOARD_EARLY_INIT_R 433 #define CONFIG_MISC_INIT_R 434 435 #define CONFIG_HWCONFIG 436 437 /* define to use L1 as initial stack */ 438 #define CONFIG_L1_INIT_RAM 439 #define CONFIG_SYS_INIT_RAM_LOCK 440 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 441 #ifdef CONFIG_PHYS_64BIT 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 444 /* The assembler doesn't like typecast */ 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 446 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 447 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 448 #else 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 452 #endif 453 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 454 455 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 456 GENERATED_GBL_DATA_SIZE) 457 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 458 459 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 460 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 461 462 /* Serial Port */ 463 #define CONFIG_CONS_INDEX 1 464 #define CONFIG_SYS_NS16550_SERIAL 465 #define CONFIG_SYS_NS16550_REG_SIZE 1 466 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 467 468 #define CONFIG_SYS_BAUDRATE_TABLE \ 469 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 470 471 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 472 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 473 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 474 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 475 476 /* Video */ 477 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 478 #define CONFIG_FSL_DIU_FB 479 #ifdef CONFIG_FSL_DIU_FB 480 #define CONFIG_FSL_DIU_CH7301 481 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 482 #define CONFIG_VIDEO_LOGO 483 #define CONFIG_VIDEO_BMP_LOGO 484 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 485 /* 486 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 487 * disable empty flash sector detection, which is I/O-intensive. 488 */ 489 #undef CONFIG_SYS_FLASH_EMPTY_INFO 490 #endif 491 #endif 492 493 /* I2C */ 494 #define CONFIG_SYS_I2C 495 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 496 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 497 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 498 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 499 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 500 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 501 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 502 503 #define I2C_MUX_PCA_ADDR 0x77 504 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 505 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 506 #define I2C_RETIMER_ADDR 0x18 507 508 /* I2C bus multiplexer */ 509 #define I2C_MUX_CH_DEFAULT 0x8 510 #define I2C_MUX_CH_DIU 0xC 511 #define I2C_MUX_CH5 0xD 512 #define I2C_MUX_CH7 0xF 513 514 /* LDI/DVI Encoder for display */ 515 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 516 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 517 518 /* 519 * RTC configuration 520 */ 521 #define RTC 522 #define CONFIG_RTC_DS3231 1 523 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 524 525 /* 526 * eSPI - Enhanced SPI 527 */ 528 #ifndef CONFIG_SPL_BUILD 529 #endif 530 #define CONFIG_SPI_FLASH_BAR 531 #define CONFIG_SF_DEFAULT_SPEED 10000000 532 #define CONFIG_SF_DEFAULT_MODE 0 533 534 /* 535 * General PCIe 536 * Memory space is mapped 1-1, but I/O space must start from 0. 537 */ 538 #define CONFIG_PCIE1 /* PCIE controller 1 */ 539 #define CONFIG_PCIE2 /* PCIE controller 2 */ 540 #define CONFIG_PCIE3 /* PCIE controller 3 */ 541 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 542 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 543 #define CONFIG_PCI_INDIRECT_BRIDGE 544 545 #ifdef CONFIG_PCI 546 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 547 #ifdef CONFIG_PCIE1 548 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 549 #ifdef CONFIG_PHYS_64BIT 550 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 551 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 552 #else 553 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 554 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 555 #endif 556 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 557 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 558 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 559 #ifdef CONFIG_PHYS_64BIT 560 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 561 #else 562 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 563 #endif 564 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 565 #endif 566 567 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 568 #ifdef CONFIG_PCIE2 569 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 570 #ifdef CONFIG_PHYS_64BIT 571 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 572 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 573 #else 574 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 575 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 576 #endif 577 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 578 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 579 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 582 #else 583 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 584 #endif 585 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 586 #endif 587 588 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 589 #ifdef CONFIG_PCIE3 590 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 591 #ifdef CONFIG_PHYS_64BIT 592 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 593 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 594 #else 595 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 596 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 597 #endif 598 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 599 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 600 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 603 #else 604 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 605 #endif 606 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 607 #endif 608 609 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 610 #endif /* CONFIG_PCI */ 611 612 /* 613 *SATA 614 */ 615 #define CONFIG_FSL_SATA_V2 616 #ifdef CONFIG_FSL_SATA_V2 617 #define CONFIG_SYS_SATA_MAX_DEVICE 1 618 #define CONFIG_SATA1 619 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 620 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 621 #define CONFIG_LBA48 622 #endif 623 624 /* 625 * USB 626 */ 627 #define CONFIG_HAS_FSL_DR_USB 628 629 #ifdef CONFIG_HAS_FSL_DR_USB 630 #define CONFIG_USB_EHCI_FSL 631 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 632 #endif 633 634 /* 635 * SDHC 636 */ 637 #ifdef CONFIG_MMC 638 #define CONFIG_FSL_ESDHC 639 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 640 #endif 641 642 /* Qman/Bman */ 643 #ifndef CONFIG_NOBQFMAN 644 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 645 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 646 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 647 #ifdef CONFIG_PHYS_64BIT 648 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 649 #else 650 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 651 #endif 652 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 653 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 654 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 655 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 656 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 657 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 658 CONFIG_SYS_BMAN_CENA_SIZE) 659 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 660 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 661 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 662 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 663 #ifdef CONFIG_PHYS_64BIT 664 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 665 #else 666 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 667 #endif 668 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 669 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 670 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 671 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 672 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 673 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 674 CONFIG_SYS_QMAN_CENA_SIZE) 675 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 676 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 677 678 #define CONFIG_SYS_DPAA_FMAN 679 680 #define CONFIG_QE 681 #define CONFIG_U_QE 682 /* Default address of microcode for the Linux FMan driver */ 683 #if defined(CONFIG_SPIFLASH) 684 /* 685 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 686 * env, so we got 0x110000. 687 */ 688 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 689 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 690 #define CONFIG_SYS_QE_FW_ADDR 0x130000 691 #elif defined(CONFIG_SDCARD) 692 /* 693 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 694 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 695 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 696 */ 697 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 698 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 699 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 700 #elif defined(CONFIG_NAND) 701 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 702 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 703 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 704 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 705 /* 706 * Slave has no ucode locally, it can fetch this from remote. When implementing 707 * in two corenet boards, slave's ucode could be stored in master's memory 708 * space, the address can be mapped from slave TLB->slave LAW-> 709 * slave SRIO or PCIE outbound window->master inbound window-> 710 * master LAW->the ucode address in master's memory space. 711 */ 712 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 713 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 714 #else 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 716 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 717 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 718 #endif 719 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 720 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 721 #endif /* CONFIG_NOBQFMAN */ 722 723 #ifdef CONFIG_SYS_DPAA_FMAN 724 #define CONFIG_FMAN_ENET 725 #define CONFIG_PHYLIB_10G 726 #define CONFIG_PHY_VITESSE 727 #define CONFIG_PHY_REALTEK 728 #define CONFIG_PHY_TERANETICS 729 #define RGMII_PHY1_ADDR 0x1 730 #define RGMII_PHY2_ADDR 0x2 731 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 732 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 733 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 734 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 735 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 736 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 737 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 738 #endif 739 740 #ifdef CONFIG_FMAN_ENET 741 #define CONFIG_MII /* MII PHY management */ 742 #define CONFIG_ETHPRIME "FM1@DTSEC4" 743 #endif 744 745 /* 746 * Dynamic MTD Partition support with mtdparts 747 */ 748 #ifdef CONFIG_MTD_NOR_FLASH 749 #define CONFIG_MTD_DEVICE 750 #define CONFIG_MTD_PARTITIONS 751 #define CONFIG_FLASH_CFI_MTD 752 #endif 753 754 /* 755 * Environment 756 */ 757 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 758 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 759 760 /* 761 * Miscellaneous configurable options 762 */ 763 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 764 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 765 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 766 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 767 768 /* 769 * For booting Linux, the board info and command line data 770 * have to be in the first 64 MB of memory, since this is 771 * the maximum mapped by the Linux kernel during initialization. 772 */ 773 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 774 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 775 776 #ifdef CONFIG_CMD_KGDB 777 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 778 #endif 779 780 /* 781 * Environment Configuration 782 */ 783 #define CONFIG_ROOTPATH "/opt/nfsroot" 784 #define CONFIG_BOOTFILE "uImage" 785 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 786 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 787 #define __USB_PHY_TYPE utmi 788 789 #define CONFIG_EXTRA_ENV_SETTINGS \ 790 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 791 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 792 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 793 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 794 "fdtfile=t1024qds/t1024qds.dtb\0" \ 795 "netdev=eth0\0" \ 796 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 797 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 798 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 799 "tftpflash=tftpboot $loadaddr $uboot && " \ 800 "protect off $ubootaddr +$filesize && " \ 801 "erase $ubootaddr +$filesize && " \ 802 "cp.b $loadaddr $ubootaddr $filesize && " \ 803 "protect on $ubootaddr +$filesize && " \ 804 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 805 "consoledev=ttyS0\0" \ 806 "ramdiskaddr=2000000\0" \ 807 "fdtaddr=d00000\0" \ 808 "bdev=sda3\0" 809 810 #define CONFIG_LINUX \ 811 "setenv bootargs root=/dev/ram rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "setenv ramdiskaddr 0x02000000;" \ 814 "setenv fdtaddr 0x00c00000;" \ 815 "setenv loadaddr 0x1000000;" \ 816 "bootm $loadaddr $ramdiskaddr $fdtaddr" 817 818 #define CONFIG_NFSBOOTCOMMAND \ 819 "setenv bootargs root=/dev/nfs rw " \ 820 "nfsroot=$serverip:$rootpath " \ 821 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 822 "console=$consoledev,$baudrate $othbootargs;" \ 823 "tftp $loadaddr $bootfile;" \ 824 "tftp $fdtaddr $fdtfile;" \ 825 "bootm $loadaddr - $fdtaddr" 826 827 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 828 829 #include <asm/fsl_secure_boot.h> 830 831 #endif /* __T1024QDS_H */ 832