1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T1024/T1023 QDS board configuration file 8 */ 9 10 #ifndef __T1024QDS_H 11 #define __T1024QDS_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_ENABLE_36BIT_PHYS 16 17 #ifdef CONFIG_PHYS_64BIT 18 #define CONFIG_ADDR_MAP 1 19 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 20 #endif 21 22 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 23 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 24 25 #define CONFIG_ENV_OVERWRITE 26 27 #define CONFIG_DEEP_SLEEP 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 33 #define CONFIG_SPL_PAD_TO 0x40000 34 #define CONFIG_SPL_MAX_SIZE 0x28000 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 #ifdef CONFIG_SPL_BUILD 38 #define CONFIG_SPL_SKIP_RELOCATE 39 #define CONFIG_SPL_COMMON_INIT_DDR 40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 41 #endif 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 48 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg 50 #define CONFIG_SPL_NAND_BOOT 51 #endif 52 53 #ifdef CONFIG_SPIFLASH 54 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 55 #define CONFIG_SPL_SPI_FLASH_MINIMAL 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 61 #ifndef CONFIG_SPL_BUILD 62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 63 #endif 64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg 65 #define CONFIG_SPL_SPI_BOOT 66 #endif 67 68 #ifdef CONFIG_SDCARD 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 70 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 72 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 73 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 75 #ifndef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 77 #endif 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg 79 #define CONFIG_SPL_MMC_BOOT 80 #endif 81 82 #endif /* CONFIG_RAMBOOT_PBL */ 83 84 #ifndef CONFIG_RESET_VECTOR_ADDRESS 85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 86 #endif 87 88 /* PCIe Boot - Master */ 89 #define CONFIG_SRIO_PCIE_BOOT_MASTER 90 /* 91 * for slave u-boot IMAGE instored in master memory space, 92 * PHYS must be aligned based on the SIZE 93 */ 94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 95 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 96 #ifdef CONFIG_PHYS_64BIT 97 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 98 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 99 #else 100 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 102 #endif 103 /* 104 * for slave UCODE and ENV instored in master memory space, 105 * PHYS must be aligned based on the SIZE 106 */ 107 #ifdef CONFIG_PHYS_64BIT 108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 109 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 110 #else 111 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 112 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 113 #endif 114 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 115 /* slave core release by master*/ 116 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 117 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 118 119 /* PCIe Boot - Slave */ 120 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 121 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 122 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 123 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 124 /* Set 1M boot space for PCIe boot */ 125 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 126 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 127 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 128 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 129 #endif 130 131 #if defined(CONFIG_SPIFLASH) 132 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 133 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 134 #define CONFIG_ENV_SECT_SIZE 0x10000 135 #elif defined(CONFIG_SDCARD) 136 #define CONFIG_SYS_MMC_ENV_DEV 0 137 #define CONFIG_ENV_SIZE 0x2000 138 #define CONFIG_ENV_OFFSET (512 * 0x800) 139 #elif defined(CONFIG_NAND) 140 #define CONFIG_ENV_SIZE 0x2000 141 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 142 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 143 #define CONFIG_ENV_ADDR 0xffe20000 144 #define CONFIG_ENV_SIZE 0x2000 145 #elif defined(CONFIG_ENV_IS_NOWHERE) 146 #define CONFIG_ENV_SIZE 0x2000 147 #else 148 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 149 #define CONFIG_ENV_SIZE 0x2000 150 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 151 #endif 152 153 #ifndef __ASSEMBLY__ 154 unsigned long get_board_sys_clk(void); 155 unsigned long get_board_ddr_clk(void); 156 #endif 157 158 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 159 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 160 161 /* 162 * These can be toggled for performance analysis, otherwise use default. 163 */ 164 #define CONFIG_SYS_CACHE_STASHING 165 #define CONFIG_BACKSIDE_L2_CACHE 166 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 167 #define CONFIG_BTB /* toggle branch predition */ 168 #define CONFIG_DDR_ECC 169 #ifdef CONFIG_DDR_ECC 170 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 171 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 172 #endif 173 174 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 175 #define CONFIG_SYS_MEMTEST_END 0x00400000 176 177 /* 178 * Config the L3 Cache as L3 SRAM 179 */ 180 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 181 #define CONFIG_SYS_L3_SIZE (256 << 10) 182 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 183 #ifdef CONFIG_RAMBOOT_PBL 184 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 185 #endif 186 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 187 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 188 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 189 190 #ifdef CONFIG_PHYS_64BIT 191 #define CONFIG_SYS_DCSRBAR 0xf0000000 192 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 193 #endif 194 195 /* EEPROM */ 196 #define CONFIG_ID_EEPROM 197 #define CONFIG_SYS_I2C_EEPROM_NXID 198 #define CONFIG_SYS_EEPROM_BUS_NUM 0 199 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 200 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 202 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 203 204 /* 205 * DDR Setup 206 */ 207 #define CONFIG_VERY_BIG_RAM 208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 209 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 210 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 211 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 212 #define CONFIG_DDR_SPD 213 214 #define CONFIG_SYS_SPD_BUS_NUM 0 215 #define SPD_EEPROM_ADDRESS 0x51 216 217 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 218 219 /* 220 * IFC Definitions 221 */ 222 #define CONFIG_SYS_FLASH_BASE 0xe0000000 223 #ifdef CONFIG_PHYS_64BIT 224 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 225 #else 226 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 227 #endif 228 229 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 230 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 231 + 0x8000000) | \ 232 CSPR_PORT_SIZE_16 | \ 233 CSPR_MSEL_NOR | \ 234 CSPR_V) 235 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 236 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 237 CSPR_PORT_SIZE_16 | \ 238 CSPR_MSEL_NOR | \ 239 CSPR_V) 240 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 241 /* NOR Flash Timing Params */ 242 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 243 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 244 FTIM0_NOR_TEADC(0x5) | \ 245 FTIM0_NOR_TEAHC(0x5)) 246 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 247 FTIM1_NOR_TRAD_NOR(0x1A) |\ 248 FTIM1_NOR_TSEQRAD_NOR(0x13)) 249 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 250 FTIM2_NOR_TCH(0x4) | \ 251 FTIM2_NOR_TWPH(0x0E) | \ 252 FTIM2_NOR_TWP(0x1c)) 253 #define CONFIG_SYS_NOR_FTIM3 0x0 254 255 #define CONFIG_SYS_FLASH_QUIET_TEST 256 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 257 258 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 259 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 260 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 261 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 262 263 #define CONFIG_SYS_FLASH_EMPTY_INFO 264 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 265 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 266 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 267 #define QIXIS_BASE 0xffdf0000 268 #ifdef CONFIG_PHYS_64BIT 269 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 270 #else 271 #define QIXIS_BASE_PHYS QIXIS_BASE 272 #endif 273 #define QIXIS_LBMAP_SWITCH 0x06 274 #define QIXIS_LBMAP_MASK 0x0f 275 #define QIXIS_LBMAP_SHIFT 0 276 #define QIXIS_LBMAP_DFLTBANK 0x00 277 #define QIXIS_LBMAP_ALTBANK 0x04 278 #define QIXIS_RST_CTL_RESET 0x31 279 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 280 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 281 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 282 #define QIXIS_RST_FORCE_MEM 0x01 283 284 #define CONFIG_SYS_CSPR3_EXT (0xf) 285 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 286 | CSPR_PORT_SIZE_8 \ 287 | CSPR_MSEL_GPCM \ 288 | CSPR_V) 289 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 290 #define CONFIG_SYS_CSOR3 0x0 291 /* QIXIS Timing parameters for IFC CS3 */ 292 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 293 FTIM0_GPCM_TEADC(0x0e) | \ 294 FTIM0_GPCM_TEAHC(0x0e)) 295 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 296 FTIM1_GPCM_TRAD(0x3f)) 297 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 298 FTIM2_GPCM_TCH(0x8) | \ 299 FTIM2_GPCM_TWP(0x1f)) 300 #define CONFIG_SYS_CS3_FTIM3 0x0 301 302 #define CONFIG_NAND_FSL_IFC 303 #define CONFIG_SYS_NAND_BASE 0xff800000 304 #ifdef CONFIG_PHYS_64BIT 305 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 306 #else 307 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 308 #endif 309 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 310 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 311 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 312 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 313 | CSPR_V) 314 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 315 316 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 317 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 318 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 319 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 320 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 321 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 322 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 323 324 #define CONFIG_SYS_NAND_ONFI_DETECTION 325 326 /* ONFI NAND Flash mode0 Timing Params */ 327 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 328 FTIM0_NAND_TWP(0x18) | \ 329 FTIM0_NAND_TWCHT(0x07) | \ 330 FTIM0_NAND_TWH(0x0a)) 331 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 332 FTIM1_NAND_TWBE(0x39) | \ 333 FTIM1_NAND_TRR(0x0e) | \ 334 FTIM1_NAND_TRP(0x18)) 335 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 336 FTIM2_NAND_TREH(0x0a) | \ 337 FTIM2_NAND_TWHRE(0x1e)) 338 #define CONFIG_SYS_NAND_FTIM3 0x0 339 340 #define CONFIG_SYS_NAND_DDR_LAW 11 341 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 342 #define CONFIG_SYS_MAX_NAND_DEVICE 1 343 344 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 345 346 #if defined(CONFIG_NAND) 347 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 348 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 349 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 350 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 351 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 352 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 353 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 354 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 355 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 356 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 357 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 358 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 359 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 360 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 361 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 362 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 363 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 364 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 365 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #else 372 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 380 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 381 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 382 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 383 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 384 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 385 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 386 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 387 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 388 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 389 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 390 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 391 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 392 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 393 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 394 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 395 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 396 #endif 397 398 #ifdef CONFIG_SPL_BUILD 399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 400 #else 401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 402 #endif 403 404 #if defined(CONFIG_RAMBOOT_PBL) 405 #define CONFIG_SYS_RAMBOOT 406 #endif 407 408 #define CONFIG_HWCONFIG 409 410 /* define to use L1 as initial stack */ 411 #define CONFIG_L1_INIT_RAM 412 #define CONFIG_SYS_INIT_RAM_LOCK 413 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 417 /* The assembler doesn't like typecast */ 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 419 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 420 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 421 #else 422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 425 #endif 426 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 427 428 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 429 GENERATED_GBL_DATA_SIZE) 430 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 431 432 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 433 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 434 435 /* Serial Port */ 436 #define CONFIG_SYS_NS16550_SERIAL 437 #define CONFIG_SYS_NS16550_REG_SIZE 1 438 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 439 440 #define CONFIG_SYS_BAUDRATE_TABLE \ 441 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 442 443 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 444 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 445 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 446 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 447 448 /* Video */ 449 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ 450 #define CONFIG_FSL_DIU_FB 451 #ifdef CONFIG_FSL_DIU_FB 452 #define CONFIG_FSL_DIU_CH7301 453 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 454 #define CONFIG_VIDEO_LOGO 455 #define CONFIG_VIDEO_BMP_LOGO 456 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 457 /* 458 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 459 * disable empty flash sector detection, which is I/O-intensive. 460 */ 461 #undef CONFIG_SYS_FLASH_EMPTY_INFO 462 #endif 463 #endif 464 465 /* I2C */ 466 #define CONFIG_SYS_I2C 467 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 468 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 469 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 470 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 471 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 472 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 473 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 474 475 #define I2C_MUX_PCA_ADDR 0x77 476 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 477 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 478 #define I2C_RETIMER_ADDR 0x18 479 480 /* I2C bus multiplexer */ 481 #define I2C_MUX_CH_DEFAULT 0x8 482 #define I2C_MUX_CH_DIU 0xC 483 #define I2C_MUX_CH5 0xD 484 #define I2C_MUX_CH7 0xF 485 486 /* LDI/DVI Encoder for display */ 487 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 488 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 489 490 /* 491 * RTC configuration 492 */ 493 #define RTC 494 #define CONFIG_RTC_DS3231 1 495 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 496 497 /* 498 * eSPI - Enhanced SPI 499 */ 500 501 /* 502 * General PCIe 503 * Memory space is mapped 1-1, but I/O space must start from 0. 504 */ 505 #define CONFIG_PCIE1 /* PCIE controller 1 */ 506 #define CONFIG_PCIE2 /* PCIE controller 2 */ 507 #define CONFIG_PCIE3 /* PCIE controller 3 */ 508 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 509 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 510 #define CONFIG_PCI_INDIRECT_BRIDGE 511 512 #ifdef CONFIG_PCI 513 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 514 #ifdef CONFIG_PCIE1 515 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 516 #ifdef CONFIG_PHYS_64BIT 517 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 518 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 519 #else 520 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 521 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 522 #endif 523 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 524 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 525 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 526 #ifdef CONFIG_PHYS_64BIT 527 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 528 #else 529 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 530 #endif 531 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 532 #endif 533 534 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 535 #ifdef CONFIG_PCIE2 536 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 537 #ifdef CONFIG_PHYS_64BIT 538 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 539 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 540 #else 541 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 542 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 543 #endif 544 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 545 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 546 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 547 #ifdef CONFIG_PHYS_64BIT 548 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 549 #else 550 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 551 #endif 552 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 553 #endif 554 555 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 556 #ifdef CONFIG_PCIE3 557 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 558 #ifdef CONFIG_PHYS_64BIT 559 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 560 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 561 #else 562 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 563 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 564 #endif 565 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 566 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 567 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 568 #ifdef CONFIG_PHYS_64BIT 569 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 570 #else 571 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 572 #endif 573 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 574 #endif 575 576 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 577 #endif /* CONFIG_PCI */ 578 579 /* 580 *SATA 581 */ 582 #define CONFIG_FSL_SATA_V2 583 #ifdef CONFIG_FSL_SATA_V2 584 #define CONFIG_SYS_SATA_MAX_DEVICE 1 585 #define CONFIG_SATA1 586 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 587 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 588 #define CONFIG_LBA48 589 #endif 590 591 /* 592 * USB 593 */ 594 #define CONFIG_HAS_FSL_DR_USB 595 596 #ifdef CONFIG_HAS_FSL_DR_USB 597 #define CONFIG_USB_EHCI_FSL 598 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 599 #endif 600 601 /* 602 * SDHC 603 */ 604 #ifdef CONFIG_MMC 605 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 606 #endif 607 608 /* Qman/Bman */ 609 #ifndef CONFIG_NOBQFMAN 610 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 611 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 612 #ifdef CONFIG_PHYS_64BIT 613 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 614 #else 615 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 616 #endif 617 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 618 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 619 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 620 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 621 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 623 CONFIG_SYS_BMAN_CENA_SIZE) 624 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 626 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 627 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 628 #ifdef CONFIG_PHYS_64BIT 629 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 630 #else 631 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 632 #endif 633 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 634 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 635 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 636 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 637 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 638 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 639 CONFIG_SYS_QMAN_CENA_SIZE) 640 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 641 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 642 643 #define CONFIG_SYS_DPAA_FMAN 644 645 #define CONFIG_QE 646 /* Default address of microcode for the Linux FMan driver */ 647 #if defined(CONFIG_SPIFLASH) 648 /* 649 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 650 * env, so we got 0x110000. 651 */ 652 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 653 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 654 #define CONFIG_SYS_QE_FW_ADDR 0x130000 655 #elif defined(CONFIG_SDCARD) 656 /* 657 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 658 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 659 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 660 */ 661 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 662 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 663 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 664 #elif defined(CONFIG_NAND) 665 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 666 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 667 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 668 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 669 /* 670 * Slave has no ucode locally, it can fetch this from remote. When implementing 671 * in two corenet boards, slave's ucode could be stored in master's memory 672 * space, the address can be mapped from slave TLB->slave LAW-> 673 * slave SRIO or PCIE outbound window->master inbound window-> 674 * master LAW->the ucode address in master's memory space. 675 */ 676 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 677 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 678 #else 679 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 680 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 681 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 682 #endif 683 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 684 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 685 #endif /* CONFIG_NOBQFMAN */ 686 687 #ifdef CONFIG_SYS_DPAA_FMAN 688 #define CONFIG_FMAN_ENET 689 #define CONFIG_PHYLIB_10G 690 #define CONFIG_PHY_VITESSE 691 #define CONFIG_PHY_REALTEK 692 #define CONFIG_PHY_TERANETICS 693 #define RGMII_PHY1_ADDR 0x1 694 #define RGMII_PHY2_ADDR 0x2 695 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 696 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 697 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 698 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 699 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 700 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 701 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 702 #endif 703 704 #ifdef CONFIG_FMAN_ENET 705 #define CONFIG_ETHPRIME "FM1@DTSEC4" 706 #endif 707 708 /* 709 * Dynamic MTD Partition support with mtdparts 710 */ 711 712 /* 713 * Environment 714 */ 715 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 716 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 717 718 /* 719 * Miscellaneous configurable options 720 */ 721 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 722 723 /* 724 * For booting Linux, the board info and command line data 725 * have to be in the first 64 MB of memory, since this is 726 * the maximum mapped by the Linux kernel during initialization. 727 */ 728 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 729 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 730 731 #ifdef CONFIG_CMD_KGDB 732 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 733 #endif 734 735 /* 736 * Environment Configuration 737 */ 738 #define CONFIG_ROOTPATH "/opt/nfsroot" 739 #define CONFIG_BOOTFILE "uImage" 740 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 741 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 742 #define __USB_PHY_TYPE utmi 743 744 #define CONFIG_EXTRA_ENV_SETTINGS \ 745 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 746 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 747 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 748 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 749 "fdtfile=t1024qds/t1024qds.dtb\0" \ 750 "netdev=eth0\0" \ 751 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 752 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 753 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 754 "tftpflash=tftpboot $loadaddr $uboot && " \ 755 "protect off $ubootaddr +$filesize && " \ 756 "erase $ubootaddr +$filesize && " \ 757 "cp.b $loadaddr $ubootaddr $filesize && " \ 758 "protect on $ubootaddr +$filesize && " \ 759 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 760 "consoledev=ttyS0\0" \ 761 "ramdiskaddr=2000000\0" \ 762 "fdtaddr=d00000\0" \ 763 "bdev=sda3\0" 764 765 #define CONFIG_LINUX \ 766 "setenv bootargs root=/dev/ram rw " \ 767 "console=$consoledev,$baudrate $othbootargs;" \ 768 "setenv ramdiskaddr 0x02000000;" \ 769 "setenv fdtaddr 0x00c00000;" \ 770 "setenv loadaddr 0x1000000;" \ 771 "bootm $loadaddr $ramdiskaddr $fdtaddr" 772 773 #define CONFIG_NFSBOOTCOMMAND \ 774 "setenv bootargs root=/dev/nfs rw " \ 775 "nfsroot=$serverip:$rootpath " \ 776 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 777 "console=$consoledev,$baudrate $othbootargs;" \ 778 "tftp $loadaddr $bootfile;" \ 779 "tftp $fdtaddr $fdtfile;" \ 780 "bootm $loadaddr - $fdtaddr" 781 782 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 783 784 #include <asm/fsl_secure_boot.h> 785 786 #endif /* __T1024QDS_H */ 787