1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 #define CONFIG_BOOKE 18 #define CONFIG_E500 /* BOOKE e500 family */ 19 #define CONFIG_E500MC /* BOOKE e500mc family */ 20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 21 #define CONFIG_MP /* support multiple processors */ 22 #define CONFIG_PHYS_64BIT 23 #define CONFIG_ENABLE_36BIT_PHYS 24 25 #ifdef CONFIG_PHYS_64BIT 26 #define CONFIG_ADDR_MAP 1 27 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 28 #endif 29 30 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 31 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 32 #define CONFIG_FSL_IFC /* Enable IFC Support */ 33 34 #define CONFIG_FSL_LAW /* Use common FSL init code */ 35 #define CONFIG_ENV_OVERWRITE 36 37 #define CONFIG_DEEP_SLEEP 38 #define CONFIG_SILENT_CONSOLE 39 40 #ifdef CONFIG_RAMBOOT_PBL 41 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 42 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 43 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 44 #define CONFIG_SPL_ENV_SUPPORT 45 #define CONFIG_SPL_SERIAL_SUPPORT 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_SPL_LIBGENERIC_SUPPORT 49 #define CONFIG_SPL_LIBCOMMON_SUPPORT 50 #define CONFIG_SPL_I2C_SUPPORT 51 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 #define CONFIG_SYS_TEXT_BASE 0x00201000 54 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 55 #define CONFIG_SPL_PAD_TO 0x40000 56 #define CONFIG_SPL_MAX_SIZE 0x28000 57 #define RESET_VECTOR_OFFSET 0x27FFC 58 #define BOOT_PAGE_OFFSET 0x27000 59 #ifdef CONFIG_SPL_BUILD 60 #define CONFIG_SPL_SKIP_RELOCATE 61 #define CONFIG_SPL_COMMON_INIT_DDR 62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 63 #define CONFIG_SYS_NO_FLASH 64 #endif 65 66 #ifdef CONFIG_NAND 67 #define CONFIG_SPL_NAND_SUPPORT 68 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 69 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 70 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 71 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 72 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 73 #define CONFIG_SPL_NAND_BOOT 74 #endif 75 76 #ifdef CONFIG_SPIFLASH 77 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 78 #define CONFIG_SPL_SPI_SUPPORT 79 #define CONFIG_SPL_SPI_FLASH_SUPPORT 80 #define CONFIG_SPL_SPI_FLASH_MINIMAL 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #define CONFIG_SPL_SPI_BOOT 90 #endif 91 92 #ifdef CONFIG_SDCARD 93 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 94 #define CONFIG_SPL_MMC_SUPPORT 95 #define CONFIG_SPL_MMC_MINIMAL 96 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 97 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 98 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 99 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 100 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 101 #ifndef CONFIG_SPL_BUILD 102 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 103 #endif 104 #define CONFIG_SPL_MMC_BOOT 105 #endif 106 107 #endif /* CONFIG_RAMBOOT_PBL */ 108 109 #ifndef CONFIG_SYS_TEXT_BASE 110 #define CONFIG_SYS_TEXT_BASE 0xeff40000 111 #endif 112 113 #ifndef CONFIG_RESET_VECTOR_ADDRESS 114 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 115 #endif 116 117 #ifndef CONFIG_SYS_NO_FLASH 118 #define CONFIG_FLASH_CFI_DRIVER 119 #define CONFIG_SYS_FLASH_CFI 120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 121 #endif 122 123 /* PCIe Boot - Master */ 124 #define CONFIG_SRIO_PCIE_BOOT_MASTER 125 /* 126 * for slave u-boot IMAGE instored in master memory space, 127 * PHYS must be aligned based on the SIZE 128 */ 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 134 #else 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 137 #endif 138 /* 139 * for slave UCODE and ENV instored in master memory space, 140 * PHYS must be aligned based on the SIZE 141 */ 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 145 #else 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 148 #endif 149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 150 /* slave core release by master*/ 151 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 152 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 153 154 /* PCIe Boot - Slave */ 155 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 158 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 159 /* Set 1M boot space for PCIe boot */ 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 162 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 163 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 164 #define CONFIG_SYS_NO_FLASH 165 #endif 166 167 #if defined(CONFIG_SPIFLASH) 168 #define CONFIG_SYS_EXTRA_ENV_RELOC 169 #define CONFIG_ENV_IS_IN_SPI_FLASH 170 #define CONFIG_ENV_SPI_BUS 0 171 #define CONFIG_ENV_SPI_CS 0 172 #define CONFIG_ENV_SPI_MAX_HZ 10000000 173 #define CONFIG_ENV_SPI_MODE 0 174 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 175 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 176 #define CONFIG_ENV_SECT_SIZE 0x10000 177 #elif defined(CONFIG_SDCARD) 178 #define CONFIG_SYS_EXTRA_ENV_RELOC 179 #define CONFIG_ENV_IS_IN_MMC 180 #define CONFIG_SYS_MMC_ENV_DEV 0 181 #define CONFIG_ENV_SIZE 0x2000 182 #define CONFIG_ENV_OFFSET (512 * 0x800) 183 #elif defined(CONFIG_NAND) 184 #define CONFIG_SYS_EXTRA_ENV_RELOC 185 #define CONFIG_ENV_IS_IN_NAND 186 #define CONFIG_ENV_SIZE 0x2000 187 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 188 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 189 #define CONFIG_ENV_IS_IN_REMOTE 190 #define CONFIG_ENV_ADDR 0xffe20000 191 #define CONFIG_ENV_SIZE 0x2000 192 #elif defined(CONFIG_ENV_IS_NOWHERE) 193 #define CONFIG_ENV_SIZE 0x2000 194 #else 195 #define CONFIG_ENV_IS_IN_FLASH 196 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 197 #define CONFIG_ENV_SIZE 0x2000 198 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 199 #endif 200 201 202 #ifndef __ASSEMBLY__ 203 unsigned long get_board_sys_clk(void); 204 unsigned long get_board_ddr_clk(void); 205 #endif 206 207 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 208 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 209 210 /* 211 * These can be toggled for performance analysis, otherwise use default. 212 */ 213 #define CONFIG_SYS_CACHE_STASHING 214 #define CONFIG_BACKSIDE_L2_CACHE 215 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 216 #define CONFIG_BTB /* toggle branch predition */ 217 #define CONFIG_DDR_ECC 218 #ifdef CONFIG_DDR_ECC 219 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 220 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 221 #endif 222 223 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 224 #define CONFIG_SYS_MEMTEST_END 0x00400000 225 #define CONFIG_SYS_ALT_MEMTEST 226 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 227 228 /* 229 * Config the L3 Cache as L3 SRAM 230 */ 231 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 232 #define CONFIG_SYS_L3_SIZE (256 << 10) 233 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 234 #ifdef CONFIG_RAMBOOT_PBL 235 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 236 #endif 237 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 238 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 239 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 240 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 241 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_DCSRBAR 0xf0000000 244 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 245 #endif 246 247 /* EEPROM */ 248 #define CONFIG_ID_EEPROM 249 #define CONFIG_SYS_I2C_EEPROM_NXID 250 #define CONFIG_SYS_EEPROM_BUS_NUM 0 251 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 252 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 255 256 /* 257 * DDR Setup 258 */ 259 #define CONFIG_VERY_BIG_RAM 260 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 261 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 262 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 263 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 264 #define CONFIG_DDR_SPD 265 #ifndef CONFIG_SYS_FSL_DDR4 266 #define CONFIG_SYS_FSL_DDR3 267 #endif 268 269 #define CONFIG_SYS_SPD_BUS_NUM 0 270 #define SPD_EEPROM_ADDRESS 0x51 271 272 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 273 274 /* 275 * IFC Definitions 276 */ 277 #define CONFIG_SYS_FLASH_BASE 0xe0000000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 280 #else 281 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 282 #endif 283 284 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 285 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 286 + 0x8000000) | \ 287 CSPR_PORT_SIZE_16 | \ 288 CSPR_MSEL_NOR | \ 289 CSPR_V) 290 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 291 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 292 CSPR_PORT_SIZE_16 | \ 293 CSPR_MSEL_NOR | \ 294 CSPR_V) 295 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 296 /* NOR Flash Timing Params */ 297 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 298 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 299 FTIM0_NOR_TEADC(0x5) | \ 300 FTIM0_NOR_TEAHC(0x5)) 301 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 302 FTIM1_NOR_TRAD_NOR(0x1A) |\ 303 FTIM1_NOR_TSEQRAD_NOR(0x13)) 304 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 305 FTIM2_NOR_TCH(0x4) | \ 306 FTIM2_NOR_TWPH(0x0E) | \ 307 FTIM2_NOR_TWP(0x1c)) 308 #define CONFIG_SYS_NOR_FTIM3 0x0 309 310 #define CONFIG_SYS_FLASH_QUIET_TEST 311 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 312 313 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 314 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 315 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 316 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 317 318 #define CONFIG_SYS_FLASH_EMPTY_INFO 319 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 320 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 321 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 322 #define QIXIS_BASE 0xffdf0000 323 #ifdef CONFIG_PHYS_64BIT 324 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 325 #else 326 #define QIXIS_BASE_PHYS QIXIS_BASE 327 #endif 328 #define QIXIS_LBMAP_SWITCH 0x06 329 #define QIXIS_LBMAP_MASK 0x0f 330 #define QIXIS_LBMAP_SHIFT 0 331 #define QIXIS_LBMAP_DFLTBANK 0x00 332 #define QIXIS_LBMAP_ALTBANK 0x04 333 #define QIXIS_RST_CTL_RESET 0x31 334 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 335 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 336 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 337 #define QIXIS_RST_FORCE_MEM 0x01 338 339 #define CONFIG_SYS_CSPR3_EXT (0xf) 340 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 341 | CSPR_PORT_SIZE_8 \ 342 | CSPR_MSEL_GPCM \ 343 | CSPR_V) 344 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 345 #define CONFIG_SYS_CSOR3 0x0 346 /* QIXIS Timing parameters for IFC CS3 */ 347 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 348 FTIM0_GPCM_TEADC(0x0e) | \ 349 FTIM0_GPCM_TEAHC(0x0e)) 350 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 351 FTIM1_GPCM_TRAD(0x3f)) 352 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 353 FTIM2_GPCM_TCH(0x8) | \ 354 FTIM2_GPCM_TWP(0x1f)) 355 #define CONFIG_SYS_CS3_FTIM3 0x0 356 357 #define CONFIG_NAND_FSL_IFC 358 #define CONFIG_SYS_NAND_BASE 0xff800000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 361 #else 362 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 363 #endif 364 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 365 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 366 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 367 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 368 | CSPR_V) 369 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 370 371 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 372 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 373 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 374 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 375 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 376 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 377 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 378 379 #define CONFIG_SYS_NAND_ONFI_DETECTION 380 381 /* ONFI NAND Flash mode0 Timing Params */ 382 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 383 FTIM0_NAND_TWP(0x18) | \ 384 FTIM0_NAND_TWCHT(0x07) | \ 385 FTIM0_NAND_TWH(0x0a)) 386 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 387 FTIM1_NAND_TWBE(0x39) | \ 388 FTIM1_NAND_TRR(0x0e) | \ 389 FTIM1_NAND_TRP(0x18)) 390 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 391 FTIM2_NAND_TREH(0x0a) | \ 392 FTIM2_NAND_TWHRE(0x1e)) 393 #define CONFIG_SYS_NAND_FTIM3 0x0 394 395 #define CONFIG_SYS_NAND_DDR_LAW 11 396 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 397 #define CONFIG_SYS_MAX_NAND_DEVICE 1 398 #define CONFIG_MTD_NAND_VERIFY_WRITE 399 #define CONFIG_CMD_NAND 400 401 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 402 403 #if defined(CONFIG_NAND) 404 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 405 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 406 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 407 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 408 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 409 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 410 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 411 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 412 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 413 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 414 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 415 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 416 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 417 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 418 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 419 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 420 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 421 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 422 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 423 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 424 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 425 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 426 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 427 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 428 #else 429 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 430 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 431 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 432 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 433 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 434 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 435 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 436 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 437 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 438 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 439 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 440 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 441 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 442 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 443 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 444 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 445 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 446 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 447 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 448 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 449 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 450 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 451 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 452 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 453 #endif 454 455 #ifdef CONFIG_SPL_BUILD 456 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 457 #else 458 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 459 #endif 460 461 #if defined(CONFIG_RAMBOOT_PBL) 462 #define CONFIG_SYS_RAMBOOT 463 #endif 464 465 #define CONFIG_BOARD_EARLY_INIT_R 466 #define CONFIG_MISC_INIT_R 467 468 #define CONFIG_HWCONFIG 469 470 /* define to use L1 as initial stack */ 471 #define CONFIG_L1_INIT_RAM 472 #define CONFIG_SYS_INIT_RAM_LOCK 473 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 477 /* The assembler doesn't like typecast */ 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 479 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 480 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 481 #else 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 485 #endif 486 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 487 488 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 489 GENERATED_GBL_DATA_SIZE) 490 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 491 492 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 493 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 494 495 /* Serial Port */ 496 #define CONFIG_CONS_INDEX 1 497 #define CONFIG_SYS_NS16550 498 #define CONFIG_SYS_NS16550_SERIAL 499 #define CONFIG_SYS_NS16550_REG_SIZE 1 500 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 501 502 #define CONFIG_SYS_BAUDRATE_TABLE \ 503 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 504 505 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 506 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 507 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 508 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 509 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 510 511 /* Use the HUSH parser */ 512 #define CONFIG_SYS_HUSH_PARSER 513 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 514 515 /* Video */ 516 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 517 #define CONFIG_FSL_DIU_FB 518 #ifdef CONFIG_FSL_DIU_FB 519 #define CONFIG_FSL_DIU_CH7301 520 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 521 #define CONFIG_VIDEO 522 #define CONFIG_CMD_BMP 523 #define CONFIG_CFB_CONSOLE 524 #define CONFIG_VIDEO_SW_CURSOR 525 #define CONFIG_VGA_AS_SINGLE_DEVICE 526 #define CONFIG_VIDEO_LOGO 527 #define CONFIG_VIDEO_BMP_LOGO 528 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 529 /* 530 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 531 * disable empty flash sector detection, which is I/O-intensive. 532 */ 533 #undef CONFIG_SYS_FLASH_EMPTY_INFO 534 #endif 535 #endif 536 537 /* pass open firmware flat tree */ 538 #define CONFIG_OF_LIBFDT 539 #define CONFIG_OF_BOARD_SETUP 540 #define CONFIG_OF_STDOUT_VIA_ALIAS 541 542 /* new uImage format support */ 543 #define CONFIG_FIT 544 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 545 546 /* I2C */ 547 #define CONFIG_SYS_I2C 548 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 549 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 550 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 551 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 552 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 553 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 554 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 555 556 #define I2C_MUX_PCA_ADDR 0x77 557 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 558 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 559 #define I2C_RETIMER_ADDR 0x18 560 561 /* I2C bus multiplexer */ 562 #define I2C_MUX_CH_DEFAULT 0x8 563 #define I2C_MUX_CH_DIU 0xC 564 #define I2C_MUX_CH5 0xD 565 #define I2C_MUX_CH7 0xF 566 567 /* LDI/DVI Encoder for display */ 568 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 569 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 570 571 /* 572 * RTC configuration 573 */ 574 #define RTC 575 #define CONFIG_RTC_DS3231 1 576 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 577 578 /* 579 * eSPI - Enhanced SPI 580 */ 581 #define CONFIG_FSL_ESPI 582 #define CONFIG_SPI_FLASH 583 #define CONFIG_SPI_FLASH_STMICRO 584 #ifndef CONFIG_SPL_BUILD 585 #define CONFIG_SPI_FLASH_SST 586 #define CONFIG_SPI_FLASH_EON 587 #endif 588 #define CONFIG_CMD_SF 589 #define CONFIG_SPI_FLASH_BAR 590 #define CONFIG_SF_DEFAULT_SPEED 10000000 591 #define CONFIG_SF_DEFAULT_MODE 0 592 593 /* 594 * General PCIe 595 * Memory space is mapped 1-1, but I/O space must start from 0. 596 */ 597 #define CONFIG_PCI /* Enable PCI/PCIE */ 598 #define CONFIG_PCIE1 /* PCIE controler 1 */ 599 #define CONFIG_PCIE2 /* PCIE controler 2 */ 600 #define CONFIG_PCIE3 /* PCIE controler 3 */ 601 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 602 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 603 #define CONFIG_PCI_INDIRECT_BRIDGE 604 605 #ifdef CONFIG_PCI 606 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 607 #ifdef CONFIG_PCIE1 608 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 609 #ifdef CONFIG_PHYS_64BIT 610 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 611 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 612 #else 613 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 614 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 615 #endif 616 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 617 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 618 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 619 #ifdef CONFIG_PHYS_64BIT 620 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 621 #else 622 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 623 #endif 624 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 625 #endif 626 627 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 628 #ifdef CONFIG_PCIE2 629 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 630 #ifdef CONFIG_PHYS_64BIT 631 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 632 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 633 #else 634 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 635 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 636 #endif 637 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 638 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 639 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 640 #ifdef CONFIG_PHYS_64BIT 641 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 642 #else 643 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 644 #endif 645 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 646 #endif 647 648 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 649 #ifdef CONFIG_PCIE3 650 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 651 #ifdef CONFIG_PHYS_64BIT 652 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 653 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 654 #else 655 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 656 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 657 #endif 658 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 659 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 660 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 661 #ifdef CONFIG_PHYS_64BIT 662 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 663 #else 664 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 665 #endif 666 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 667 #endif 668 669 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 670 #define CONFIG_E1000 671 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 672 #define CONFIG_DOS_PARTITION 673 #endif /* CONFIG_PCI */ 674 675 /* 676 *SATA 677 */ 678 #define CONFIG_FSL_SATA_V2 679 #ifdef CONFIG_FSL_SATA_V2 680 #define CONFIG_LIBATA 681 #define CONFIG_FSL_SATA 682 #define CONFIG_SYS_SATA_MAX_DEVICE 1 683 #define CONFIG_SATA1 684 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 685 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 686 #define CONFIG_LBA48 687 #define CONFIG_CMD_SATA 688 #define CONFIG_DOS_PARTITION 689 #define CONFIG_CMD_EXT2 690 #endif 691 692 /* 693 * USB 694 */ 695 #define CONFIG_HAS_FSL_DR_USB 696 697 #ifdef CONFIG_HAS_FSL_DR_USB 698 #define CONFIG_USB_EHCI 699 #define CONFIG_CMD_USB 700 #define CONFIG_USB_STORAGE 701 #define CONFIG_USB_EHCI_FSL 702 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 703 #define CONFIG_CMD_EXT2 704 #endif 705 706 /* 707 * SDHC 708 */ 709 #define CONFIG_MMC 710 #ifdef CONFIG_MMC 711 #define CONFIG_FSL_ESDHC 712 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 713 #define CONFIG_CMD_MMC 714 #define CONFIG_GENERIC_MMC 715 #define CONFIG_CMD_EXT2 716 #define CONFIG_CMD_FAT 717 #define CONFIG_DOS_PARTITION 718 #endif 719 720 /* Qman/Bman */ 721 #ifndef CONFIG_NOBQFMAN 722 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 723 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 724 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 725 #ifdef CONFIG_PHYS_64BIT 726 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 727 #else 728 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 729 #endif 730 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 731 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 732 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 733 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 734 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 735 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 736 CONFIG_SYS_BMAN_CENA_SIZE) 737 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 738 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 739 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 740 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 741 #ifdef CONFIG_PHYS_64BIT 742 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 743 #else 744 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 745 #endif 746 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 747 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 748 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 749 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 750 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 751 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 752 CONFIG_SYS_QMAN_CENA_SIZE) 753 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 754 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 755 756 #define CONFIG_SYS_DPAA_FMAN 757 758 #define CONFIG_QE 759 #define CONFIG_U_QE 760 /* Default address of microcode for the Linux FMan driver */ 761 #if defined(CONFIG_SPIFLASH) 762 /* 763 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 764 * env, so we got 0x110000. 765 */ 766 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 767 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 768 #define CONFIG_SYS_QE_FW_ADDR 0x130000 769 #elif defined(CONFIG_SDCARD) 770 /* 771 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 772 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 773 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 774 */ 775 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 776 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 777 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 778 #elif defined(CONFIG_NAND) 779 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 780 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 781 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 782 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 783 /* 784 * Slave has no ucode locally, it can fetch this from remote. When implementing 785 * in two corenet boards, slave's ucode could be stored in master's memory 786 * space, the address can be mapped from slave TLB->slave LAW-> 787 * slave SRIO or PCIE outbound window->master inbound window-> 788 * master LAW->the ucode address in master's memory space. 789 */ 790 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 791 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 792 #else 793 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 794 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 795 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 796 #endif 797 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 798 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 799 #endif /* CONFIG_NOBQFMAN */ 800 801 #ifdef CONFIG_SYS_DPAA_FMAN 802 #define CONFIG_FMAN_ENET 803 #define CONFIG_PHYLIB_10G 804 #define CONFIG_PHY_VITESSE 805 #define CONFIG_PHY_REALTEK 806 #define CONFIG_PHY_TERANETICS 807 #define RGMII_PHY1_ADDR 0x1 808 #define RGMII_PHY2_ADDR 0x2 809 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 810 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 811 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 812 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 813 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 814 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 815 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 816 #endif 817 818 #ifdef CONFIG_FMAN_ENET 819 #define CONFIG_MII /* MII PHY management */ 820 #define CONFIG_ETHPRIME "FM1@DTSEC4" 821 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 822 #endif 823 824 /* 825 * Dynamic MTD Partition support with mtdparts 826 */ 827 #ifndef CONFIG_SYS_NO_FLASH 828 #define CONFIG_MTD_DEVICE 829 #define CONFIG_MTD_PARTITIONS 830 #define CONFIG_CMD_MTDPARTS 831 #define CONFIG_FLASH_CFI_MTD 832 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 833 "spi0=spife110000.0" 834 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 835 "128k(dtb),96m(fs),-(user);"\ 836 "fff800000.flash:2m(uboot),9m(kernel),"\ 837 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 838 "2m(uboot),9m(kernel),128k(dtb),-(user)" 839 #endif 840 841 /* 842 * Environment 843 */ 844 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 845 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 846 847 /* 848 * Command line configuration. 849 */ 850 #include <config_cmd_default.h> 851 852 #define CONFIG_CMD_DATE 853 #define CONFIG_CMD_DHCP 854 #define CONFIG_CMD_EEPROM 855 #define CONFIG_CMD_ELF 856 #define CONFIG_CMD_ERRATA 857 #define CONFIG_CMD_GREPENV 858 #define CONFIG_CMD_IRQ 859 #define CONFIG_CMD_I2C 860 #define CONFIG_CMD_MII 861 #define CONFIG_CMD_PING 862 #define CONFIG_CMD_REGINFO 863 #define CONFIG_CMD_SETEXPR 864 865 #ifdef CONFIG_PCI 866 #define CONFIG_CMD_PCI 867 #define CONFIG_CMD_NET 868 #endif 869 870 /* 871 * Miscellaneous configurable options 872 */ 873 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 874 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 875 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 876 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 877 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 878 #ifdef CONFIG_CMD_KGDB 879 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 880 #else 881 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 882 #endif 883 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 884 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 885 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 886 887 /* 888 * For booting Linux, the board info and command line data 889 * have to be in the first 64 MB of memory, since this is 890 * the maximum mapped by the Linux kernel during initialization. 891 */ 892 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 893 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 894 895 #ifdef CONFIG_CMD_KGDB 896 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 897 #endif 898 899 /* 900 * Environment Configuration 901 */ 902 #define CONFIG_ROOTPATH "/opt/nfsroot" 903 #define CONFIG_BOOTFILE "uImage" 904 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 905 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 906 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 907 #define CONFIG_BAUDRATE 115200 908 #define __USB_PHY_TYPE utmi 909 910 911 #define CONFIG_EXTRA_ENV_SETTINGS \ 912 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 913 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 914 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 915 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 916 "fdtfile=t1024qds/t1024qds.dtb\0" \ 917 "netdev=eth0\0" \ 918 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 919 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 920 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 921 "tftpflash=tftpboot $loadaddr $uboot && " \ 922 "protect off $ubootaddr +$filesize && " \ 923 "erase $ubootaddr +$filesize && " \ 924 "cp.b $loadaddr $ubootaddr $filesize && " \ 925 "protect on $ubootaddr +$filesize && " \ 926 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 927 "consoledev=ttyS0\0" \ 928 "ramdiskaddr=2000000\0" \ 929 "fdtaddr=d00000\0" \ 930 "bdev=sda3\0" 931 932 #define CONFIG_LINUX \ 933 "setenv bootargs root=/dev/ram rw " \ 934 "console=$consoledev,$baudrate $othbootargs;" \ 935 "setenv ramdiskaddr 0x02000000;" \ 936 "setenv fdtaddr 0x00c00000;" \ 937 "setenv loadaddr 0x1000000;" \ 938 "bootm $loadaddr $ramdiskaddr $fdtaddr" 939 940 #define CONFIG_NFSBOOTCOMMAND \ 941 "setenv bootargs root=/dev/nfs rw " \ 942 "nfsroot=$serverip:$rootpath " \ 943 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 944 "console=$consoledev,$baudrate $othbootargs;" \ 945 "tftp $loadaddr $bootfile;" \ 946 "tftp $fdtaddr $fdtfile;" \ 947 "bootm $loadaddr - $fdtaddr" 948 949 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 950 951 #ifdef CONFIG_SECURE_BOOT 952 #include <asm/fsl_secure_boot.h> 953 #endif 954 955 #endif /* __T1024QDS_H */ 956