1d1712369SKumar Gala /* 2d621da00SJerry Huang * Copyright 2009-2011 Freescale Semiconductor, Inc. 3d1712369SKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5d1712369SKumar Gala */ 6d1712369SKumar Gala 7d1712369SKumar Gala /* 8d1712369SKumar Gala * P4080 DS board configuration file 93e978f5dSScott Wood * Also supports P4040 DS 10d1712369SKumar Gala */ 11d1712369SKumar Gala #define CONFIG_P4080DS 12d1712369SKumar Gala #define CONFIG_PHYS_64BIT 13d1712369SKumar Gala #define CONFIG_PPC_P4080 14d1712369SKumar Gala 15c6d33901SKumar Gala #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 16c6d33901SKumar Gala 17c6d33901SKumar Gala #define CONFIG_MMC 18c6d33901SKumar Gala #define CONFIG_PCIE3 19c6d33901SKumar Gala 20*70672a29SShaohui Xie #define CONFIG_CMD_SATA 21*70672a29SShaohui Xie #define CONFIG_SATA_SIL 22*70672a29SShaohui Xie #define CONFIG_SYS_SATA_MAX_DEVICE 2 23*70672a29SShaohui Xie #define CONFIG_LIBATA 24*70672a29SShaohui Xie #define CONFIG_LBA48 25*70672a29SShaohui Xie 2611860d88STimur Tabi #define CONFIG_SYS_SRIO 2711860d88STimur Tabi #define CONFIG_SRIO1 /* SRIO port 1 */ 2811860d88STimur Tabi #define CONFIG_SRIO2 /* SRIO port 2 */ 29c8b28152SLiu Gang #define CONFIG_SRIO_PCIE_BOOT_MASTER 300ce8437fSKumar Gala #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ 310ce8437fSKumar Gala 32d1712369SKumar Gala #include "corenet_ds.h" 33