1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2d1712369SKumar Gala /* 3d621da00SJerry Huang * Copyright 2009-2011 Freescale Semiconductor, Inc. 4d1712369SKumar Gala */ 5d1712369SKumar Gala 6d1712369SKumar Gala /* 7d1712369SKumar Gala * P4080 DS board configuration file 83e978f5dSScott Wood * Also supports P4040 DS 9d1712369SKumar Gala */ 10c6d33901SKumar Gala #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 11c6d33901SKumar Gala 12c6d33901SKumar Gala #define CONFIG_PCIE3 13c6d33901SKumar Gala 1470672a29SShaohui Xie #define CONFIG_SYS_SATA_MAX_DEVICE 2 1570672a29SShaohui Xie #define CONFIG_LBA48 1670672a29SShaohui Xie 1711860d88STimur Tabi #define CONFIG_SYS_SRIO 1811860d88STimur Tabi #define CONFIG_SRIO1 /* SRIO port 1 */ 1911860d88STimur Tabi #define CONFIG_SRIO2 /* SRIO port 2 */ 20c8b28152SLiu Gang #define CONFIG_SRIO_PCIE_BOOT_MASTER 210ce8437fSKumar Gala #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ 220ce8437fSKumar Gala 23d1712369SKumar Gala #include "corenet_ds.h" 24