1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e02aea61SKumar Gala /* 3e02aea61SKumar Gala * Copyright 2010-2011 Freescale Semiconductor, Inc. 4e02aea61SKumar Gala */ 5e02aea61SKumar Gala 6e02aea61SKumar Gala /* 7e02aea61SKumar Gala * P3041 DS board configuration file 8e02aea61SKumar Gala * 9e02aea61SKumar Gala */ 10c6d33901SKumar Gala #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 11c6d33901SKumar Gala 12c6d33901SKumar Gala #define CONFIG_NAND_FSL_ELBC 139760b274SZang Roy-R61911 #define CONFIG_FSL_SATA_V2 14c6d33901SKumar Gala #define CONFIG_PCIE3 15e02aea61SKumar Gala #define CONFIG_PCIE4 164d28db8aSKumar Gala #define CONFIG_SYS_DPAA_RMAN 17e02aea61SKumar Gala 1811860d88STimur Tabi #define CONFIG_SYS_SRIO 1911860d88STimur Tabi #define CONFIG_SRIO1 /* SRIO port 1 */ 2011860d88STimur Tabi #define CONFIG_SRIO2 /* SRIO port 2 */ 21c8b28152SLiu Gang #define CONFIG_SRIO_PCIE_BOOT_MASTER 22e02aea61SKumar Gala #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 23e02aea61SKumar Gala 24e02aea61SKumar Gala #include "corenet_ds.h" 25