1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * P2041 RDB board configuration file 8 * Also supports P2040 RDB 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 15 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 17 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 18 #endif 19 20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 21 /* Set 1M boot space */ 22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 30 31 #ifndef CONFIG_RESET_VECTOR_ADDRESS 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 33 #endif 34 35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 36 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 37 #define CONFIG_PCIE1 /* PCIE controller 1 */ 38 #define CONFIG_PCIE2 /* PCIE controller 2 */ 39 #define CONFIG_PCIE3 /* PCIE controller 3 */ 40 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 41 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 #define CONFIG_SRIO2 /* SRIO port 2 */ 46 #define CONFIG_SRIO_PCIE_BOOT_MASTER 47 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 48 49 #define CONFIG_ENV_OVERWRITE 50 51 #if defined(CONFIG_SPIFLASH) 52 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 53 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 54 #define CONFIG_ENV_SECT_SIZE 0x10000 55 #elif defined(CONFIG_SDCARD) 56 #define CONFIG_FSL_FIXED_MMC_LOCATION 57 #define CONFIG_SYS_MMC_ENV_DEV 0 58 #define CONFIG_ENV_SIZE 0x2000 59 #define CONFIG_ENV_OFFSET (512 * 1658) 60 #elif defined(CONFIG_NAND) 61 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 62 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 63 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 64 #define CONFIG_ENV_ADDR 0xffe20000 65 #define CONFIG_ENV_SIZE 0x2000 66 #elif defined(CONFIG_ENV_IS_NOWHERE) 67 #define CONFIG_ENV_SIZE 0x2000 68 #else 69 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 70 - CONFIG_ENV_SECT_SIZE) 71 #define CONFIG_ENV_SIZE 0x2000 72 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 73 #endif 74 75 #ifndef __ASSEMBLY__ 76 unsigned long get_board_sys_clk(unsigned long dummy); 77 #endif 78 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 79 80 /* 81 * These can be toggled for performance analysis, otherwise use default. 82 */ 83 #define CONFIG_SYS_CACHE_STASHING 84 #define CONFIG_BACKSIDE_L2_CACHE 85 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 86 #define CONFIG_BTB /* toggle branch predition */ 87 88 #define CONFIG_ENABLE_36BIT_PHYS 89 90 #ifdef CONFIG_PHYS_64BIT 91 #define CONFIG_ADDR_MAP 92 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 93 #endif 94 95 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 99 /* 100 * Config the L3 Cache as L3 SRAM 101 */ 102 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 103 #ifdef CONFIG_PHYS_64BIT 104 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 105 CONFIG_RAMBOOT_TEXT_BASE) 106 #else 107 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 108 #endif 109 #define CONFIG_SYS_L3_SIZE (1024 << 10) 110 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 111 112 #ifdef CONFIG_PHYS_64BIT 113 #define CONFIG_SYS_DCSRBAR 0xf0000000 114 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 115 #endif 116 117 /* EEPROM */ 118 #define CONFIG_ID_EEPROM 119 #define CONFIG_SYS_I2C_EEPROM_NXID 120 #define CONFIG_SYS_EEPROM_BUS_NUM 0 121 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 123 124 /* 125 * DDR Setup 126 */ 127 #define CONFIG_VERY_BIG_RAM 128 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 129 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 130 131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 132 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 133 134 #define CONFIG_DDR_SPD 135 136 #define CONFIG_SYS_SPD_BUS_NUM 0 137 #define SPD_EEPROM_ADDRESS 0x52 138 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 139 140 /* 141 * Local Bus Definitions 142 */ 143 144 /* Set the local bus clock 1/8 of platform clock */ 145 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 146 147 /* 148 * This board doesn't have a promjet connector. 149 * However, it uses commone corenet board LAW and TLB. 150 * It is necessary to use the same start address with proper offset. 151 */ 152 #define CONFIG_SYS_FLASH_BASE 0xe0000000 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 155 #else 156 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 157 #endif 158 159 #define CONFIG_SYS_FLASH_BR_PRELIM \ 160 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 161 BR_PS_16 | BR_V) 162 #define CONFIG_SYS_FLASH_OR_PRELIM \ 163 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 164 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 165 166 #define CONFIG_FSL_CPLD 167 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 168 #ifdef CONFIG_PHYS_64BIT 169 #define CPLD_BASE_PHYS 0xfffdf0000ull 170 #else 171 #define CPLD_BASE_PHYS CPLD_BASE 172 #endif 173 174 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 175 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 176 177 #define PIXIS_LBMAP_SWITCH 7 178 #define PIXIS_LBMAP_MASK 0xf0 179 #define PIXIS_LBMAP_SHIFT 4 180 #define PIXIS_LBMAP_ALTBANK 0x40 181 182 #define CONFIG_SYS_FLASH_QUIET_TEST 183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 184 185 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 186 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 189 190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 191 192 #if defined(CONFIG_RAMBOOT_PBL) 193 #define CONFIG_SYS_RAMBOOT 194 #endif 195 196 #define CONFIG_NAND_FSL_ELBC 197 /* Nand Flash */ 198 #ifdef CONFIG_NAND_FSL_ELBC 199 #define CONFIG_SYS_NAND_BASE 0xffa00000 200 #ifdef CONFIG_PHYS_64BIT 201 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 202 #else 203 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 204 #endif 205 206 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 207 #define CONFIG_SYS_MAX_NAND_DEVICE 1 208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 209 210 /* NAND flash config */ 211 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 212 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 213 | BR_PS_8 /* Port Size = 8 bit */ \ 214 | BR_MS_FCM /* MSEL = FCM */ \ 215 | BR_V) /* valid */ 216 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 217 | OR_FCM_PGS /* Large Page*/ \ 218 | OR_FCM_CSCT \ 219 | OR_FCM_CST \ 220 | OR_FCM_CHT \ 221 | OR_FCM_SCY_1 \ 222 | OR_FCM_TRLX \ 223 | OR_FCM_EHTR) 224 225 #ifdef CONFIG_NAND 226 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 227 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 228 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 229 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 230 #else 231 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 232 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 233 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 234 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 235 #endif 236 #else 237 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 238 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 239 #endif /* CONFIG_NAND_FSL_ELBC */ 240 241 #define CONFIG_SYS_FLASH_EMPTY_INFO 242 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 243 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 244 245 #define CONFIG_HWCONFIG 246 247 /* define to use L1 as initial stack */ 248 #define CONFIG_L1_INIT_RAM 249 #define CONFIG_SYS_INIT_RAM_LOCK 250 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 251 #ifdef CONFIG_PHYS_64BIT 252 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 254 /* The assembler doesn't like typecast */ 255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 256 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 257 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 258 #else 259 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 260 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 261 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 262 #endif 263 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 264 265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 266 GENERATED_GBL_DATA_SIZE) 267 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 268 269 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 270 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 271 272 /* Serial Port - controlled on board with jumper J8 273 * open - index 2 274 * shorted - index 1 275 */ 276 #define CONFIG_SYS_NS16550_SERIAL 277 #define CONFIG_SYS_NS16550_REG_SIZE 1 278 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 279 280 #define CONFIG_SYS_BAUDRATE_TABLE \ 281 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 282 283 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 284 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 285 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 286 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 287 288 /* I2C */ 289 #define CONFIG_SYS_I2C 290 #define CONFIG_SYS_I2C_FSL 291 #define CONFIG_SYS_FSL_I2C_SPEED 400000 292 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 293 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 294 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 295 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 296 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 297 298 /* 299 * RapidIO 300 */ 301 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 302 #ifdef CONFIG_PHYS_64BIT 303 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 304 #else 305 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 306 #endif 307 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 308 309 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 310 #ifdef CONFIG_PHYS_64BIT 311 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 312 #else 313 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 314 #endif 315 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 316 317 /* 318 * for slave u-boot IMAGE instored in master memory space, 319 * PHYS must be aligned based on the SIZE 320 */ 321 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 322 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 323 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 324 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 325 /* 326 * for slave UCODE and ENV instored in master memory space, 327 * PHYS must be aligned based on the SIZE 328 */ 329 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 330 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 331 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 332 333 /* slave core release by master*/ 334 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 335 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 336 337 /* 338 * SRIO_PCIE_BOOT - SLAVE 339 */ 340 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 341 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 342 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 343 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 344 #endif 345 346 /* 347 * eSPI - Enhanced SPI 348 */ 349 350 /* 351 * General PCI 352 * Memory space is mapped 1-1, but I/O space must start from 0. 353 */ 354 355 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 356 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 359 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 360 #else 361 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 362 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 363 #endif 364 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 365 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 366 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 367 #ifdef CONFIG_PHYS_64BIT 368 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 369 #else 370 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 371 #endif 372 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 373 374 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 375 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 376 #ifdef CONFIG_PHYS_64BIT 377 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 378 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 379 #else 380 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 381 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 382 #endif 383 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 384 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 385 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 386 #ifdef CONFIG_PHYS_64BIT 387 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 388 #else 389 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 390 #endif 391 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 392 393 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 394 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 395 #ifdef CONFIG_PHYS_64BIT 396 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 397 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 398 #else 399 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 400 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 401 #endif 402 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 403 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 404 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 407 #else 408 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 409 #endif 410 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 411 412 /* Qman/Bman */ 413 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 414 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 417 #else 418 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 419 #endif 420 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 421 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 422 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 423 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 424 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 425 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 426 CONFIG_SYS_BMAN_CENA_SIZE) 427 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 428 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 429 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 430 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 433 #else 434 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 435 #endif 436 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 437 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 438 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 439 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 440 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 441 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 442 CONFIG_SYS_QMAN_CENA_SIZE) 443 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 444 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 445 446 #define CONFIG_SYS_DPAA_FMAN 447 #define CONFIG_SYS_DPAA_PME 448 /* Default address of microcode for the Linux Fman driver */ 449 #if defined(CONFIG_SPIFLASH) 450 /* 451 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 452 * env, so we got 0x110000. 453 */ 454 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 455 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 456 #elif defined(CONFIG_SDCARD) 457 /* 458 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 459 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 460 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 461 */ 462 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 463 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 464 #elif defined(CONFIG_NAND) 465 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 466 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 467 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 468 /* 469 * Slave has no ucode locally, it can fetch this from remote. When implementing 470 * in two corenet boards, slave's ucode could be stored in master's memory 471 * space, the address can be mapped from slave TLB->slave LAW-> 472 * slave SRIO or PCIE outbound window->master inbound window-> 473 * master LAW->the ucode address in master's memory space. 474 */ 475 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 476 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 477 #else 478 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 479 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 480 #endif 481 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 482 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 483 484 #ifdef CONFIG_SYS_DPAA_FMAN 485 #define CONFIG_FMAN_ENET 486 #define CONFIG_PHYLIB_10G 487 #define CONFIG_PHY_VITESSE 488 #define CONFIG_PHY_TERANETICS 489 #endif 490 491 #ifdef CONFIG_PCI 492 #define CONFIG_PCI_INDIRECT_BRIDGE 493 494 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 495 #endif /* CONFIG_PCI */ 496 497 /* SATA */ 498 #define CONFIG_FSL_SATA_V2 499 500 #ifdef CONFIG_FSL_SATA_V2 501 #define CONFIG_SYS_SATA_MAX_DEVICE 2 502 #define CONFIG_SATA1 503 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 504 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 505 #define CONFIG_SATA2 506 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 507 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 508 509 #define CONFIG_LBA48 510 #endif 511 512 #ifdef CONFIG_FMAN_ENET 513 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 514 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 515 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 516 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 517 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 518 519 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 520 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 521 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 522 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 523 524 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 525 526 #define CONFIG_SYS_TBIPA_VALUE 8 527 #define CONFIG_ETHPRIME "FM1@DTSEC1" 528 #endif 529 530 /* 531 * Environment 532 */ 533 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 534 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 535 536 /* 537 * Command line configuration. 538 */ 539 540 /* 541 * USB 542 */ 543 #define CONFIG_HAS_FSL_DR_USB 544 #define CONFIG_HAS_FSL_MPH_USB 545 546 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 547 #define CONFIG_USB_EHCI_FSL 548 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 549 #endif 550 551 #ifdef CONFIG_MMC 552 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 553 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 554 #endif 555 556 /* 557 * Miscellaneous configurable options 558 */ 559 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 560 561 /* 562 * For booting Linux, the board info and command line data 563 * have to be in the first 64 MB of memory, since this is 564 * the maximum mapped by the Linux kernel during initialization. 565 */ 566 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 567 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 568 569 #ifdef CONFIG_CMD_KGDB 570 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 571 #endif 572 573 /* 574 * Environment Configuration 575 */ 576 #define CONFIG_ROOTPATH "/opt/nfsroot" 577 #define CONFIG_BOOTFILE "uImage" 578 #define CONFIG_UBOOTPATH u-boot.bin 579 580 /* default location for tftp and bootm */ 581 #define CONFIG_LOADADDR 1000000 582 583 #define __USB_PHY_TYPE utmi 584 585 #define CONFIG_EXTRA_ENV_SETTINGS \ 586 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 587 "bank_intlv=cs0_cs1\0" \ 588 "netdev=eth0\0" \ 589 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 590 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 591 "tftpflash=tftpboot $loadaddr $uboot && " \ 592 "protect off $ubootaddr +$filesize && " \ 593 "erase $ubootaddr +$filesize && " \ 594 "cp.b $loadaddr $ubootaddr $filesize && " \ 595 "protect on $ubootaddr +$filesize && " \ 596 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 597 "consoledev=ttyS0\0" \ 598 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 599 "usb_dr_mode=host\0" \ 600 "ramdiskaddr=2000000\0" \ 601 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 602 "fdtaddr=1e00000\0" \ 603 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 604 "bdev=sda3\0" 605 606 #define CONFIG_HDBOOT \ 607 "setenv bootargs root=/dev/$bdev rw " \ 608 "console=$consoledev,$baudrate $othbootargs;" \ 609 "tftp $loadaddr $bootfile;" \ 610 "tftp $fdtaddr $fdtfile;" \ 611 "bootm $loadaddr - $fdtaddr" 612 613 #define CONFIG_NFSBOOTCOMMAND \ 614 "setenv bootargs root=/dev/nfs rw " \ 615 "nfsroot=$serverip:$rootpath " \ 616 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 617 "console=$consoledev,$baudrate $othbootargs;" \ 618 "tftp $loadaddr $bootfile;" \ 619 "tftp $fdtaddr $fdtfile;" \ 620 "bootm $loadaddr - $fdtaddr" 621 622 #define CONFIG_RAMBOOTCOMMAND \ 623 "setenv bootargs root=/dev/ram rw " \ 624 "console=$consoledev,$baudrate $othbootargs;" \ 625 "tftp $ramdiskaddr $ramdiskfile;" \ 626 "tftp $loadaddr $bootfile;" \ 627 "tftp $fdtaddr $fdtfile;" \ 628 "bootm $loadaddr $ramdiskaddr $fdtaddr" 629 630 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 631 632 #include <asm/fsl_secure_boot.h> 633 634 #endif /* __CONFIG_H */ 635