1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * P2041 RDB board configuration file 8 * Also supports P2040 RDB 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 15 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 17 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 18 #endif 19 20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 21 /* Set 1M boot space */ 22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 30 31 #ifndef CONFIG_RESET_VECTOR_ADDRESS 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 33 #endif 34 35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 36 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 37 #define CONFIG_PCIE1 /* PCIE controller 1 */ 38 #define CONFIG_PCIE2 /* PCIE controller 2 */ 39 #define CONFIG_PCIE3 /* PCIE controller 3 */ 40 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 41 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 #define CONFIG_SRIO2 /* SRIO port 2 */ 46 #define CONFIG_SRIO_PCIE_BOOT_MASTER 47 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 48 49 #define CONFIG_ENV_OVERWRITE 50 51 #ifndef CONFIG_MTD_NOR_FLASH 52 #else 53 #define CONFIG_FLASH_CFI_DRIVER 54 #define CONFIG_SYS_FLASH_CFI 55 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 56 #endif 57 58 #if defined(CONFIG_SPIFLASH) 59 #define CONFIG_SYS_EXTRA_ENV_RELOC 60 #define CONFIG_ENV_SPI_BUS 0 61 #define CONFIG_ENV_SPI_CS 0 62 #define CONFIG_ENV_SPI_MAX_HZ 10000000 63 #define CONFIG_ENV_SPI_MODE 0 64 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 65 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 66 #define CONFIG_ENV_SECT_SIZE 0x10000 67 #elif defined(CONFIG_SDCARD) 68 #define CONFIG_SYS_EXTRA_ENV_RELOC 69 #define CONFIG_FSL_FIXED_MMC_LOCATION 70 #define CONFIG_SYS_MMC_ENV_DEV 0 71 #define CONFIG_ENV_SIZE 0x2000 72 #define CONFIG_ENV_OFFSET (512 * 1658) 73 #elif defined(CONFIG_NAND) 74 #define CONFIG_SYS_EXTRA_ENV_RELOC 75 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 76 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 77 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 78 #define CONFIG_ENV_ADDR 0xffe20000 79 #define CONFIG_ENV_SIZE 0x2000 80 #elif defined(CONFIG_ENV_IS_NOWHERE) 81 #define CONFIG_ENV_SIZE 0x2000 82 #else 83 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 84 - CONFIG_ENV_SECT_SIZE) 85 #define CONFIG_ENV_SIZE 0x2000 86 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 87 #endif 88 89 #ifndef __ASSEMBLY__ 90 unsigned long get_board_sys_clk(unsigned long dummy); 91 #endif 92 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 93 94 /* 95 * These can be toggled for performance analysis, otherwise use default. 96 */ 97 #define CONFIG_SYS_CACHE_STASHING 98 #define CONFIG_BACKSIDE_L2_CACHE 99 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 100 #define CONFIG_BTB /* toggle branch predition */ 101 102 #define CONFIG_ENABLE_36BIT_PHYS 103 104 #ifdef CONFIG_PHYS_64BIT 105 #define CONFIG_ADDR_MAP 106 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 107 #endif 108 109 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 110 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 111 #define CONFIG_SYS_MEMTEST_END 0x00400000 112 113 /* 114 * Config the L3 Cache as L3 SRAM 115 */ 116 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 117 #ifdef CONFIG_PHYS_64BIT 118 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 119 CONFIG_RAMBOOT_TEXT_BASE) 120 #else 121 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 122 #endif 123 #define CONFIG_SYS_L3_SIZE (1024 << 10) 124 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 125 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SYS_DCSRBAR 0xf0000000 128 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 129 #endif 130 131 /* EEPROM */ 132 #define CONFIG_ID_EEPROM 133 #define CONFIG_SYS_I2C_EEPROM_NXID 134 #define CONFIG_SYS_EEPROM_BUS_NUM 0 135 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 136 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 137 138 /* 139 * DDR Setup 140 */ 141 #define CONFIG_VERY_BIG_RAM 142 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 143 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 144 145 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 146 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 147 148 #define CONFIG_DDR_SPD 149 150 #define CONFIG_SYS_SPD_BUS_NUM 0 151 #define SPD_EEPROM_ADDRESS 0x52 152 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 153 154 /* 155 * Local Bus Definitions 156 */ 157 158 /* Set the local bus clock 1/8 of platform clock */ 159 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 160 161 /* 162 * This board doesn't have a promjet connector. 163 * However, it uses commone corenet board LAW and TLB. 164 * It is necessary to use the same start address with proper offset. 165 */ 166 #define CONFIG_SYS_FLASH_BASE 0xe0000000 167 #ifdef CONFIG_PHYS_64BIT 168 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 169 #else 170 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 171 #endif 172 173 #define CONFIG_SYS_FLASH_BR_PRELIM \ 174 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 175 BR_PS_16 | BR_V) 176 #define CONFIG_SYS_FLASH_OR_PRELIM \ 177 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 178 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 179 180 #define CONFIG_FSL_CPLD 181 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 182 #ifdef CONFIG_PHYS_64BIT 183 #define CPLD_BASE_PHYS 0xfffdf0000ull 184 #else 185 #define CPLD_BASE_PHYS CPLD_BASE 186 #endif 187 188 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 189 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 190 191 #define PIXIS_LBMAP_SWITCH 7 192 #define PIXIS_LBMAP_MASK 0xf0 193 #define PIXIS_LBMAP_SHIFT 4 194 #define PIXIS_LBMAP_ALTBANK 0x40 195 196 #define CONFIG_SYS_FLASH_QUIET_TEST 197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 198 199 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 200 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 203 204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 205 206 #if defined(CONFIG_RAMBOOT_PBL) 207 #define CONFIG_SYS_RAMBOOT 208 #endif 209 210 #define CONFIG_NAND_FSL_ELBC 211 /* Nand Flash */ 212 #ifdef CONFIG_NAND_FSL_ELBC 213 #define CONFIG_SYS_NAND_BASE 0xffa00000 214 #ifdef CONFIG_PHYS_64BIT 215 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 216 #else 217 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 218 #endif 219 220 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 221 #define CONFIG_SYS_MAX_NAND_DEVICE 1 222 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 223 224 /* NAND flash config */ 225 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 226 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 227 | BR_PS_8 /* Port Size = 8 bit */ \ 228 | BR_MS_FCM /* MSEL = FCM */ \ 229 | BR_V) /* valid */ 230 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 231 | OR_FCM_PGS /* Large Page*/ \ 232 | OR_FCM_CSCT \ 233 | OR_FCM_CST \ 234 | OR_FCM_CHT \ 235 | OR_FCM_SCY_1 \ 236 | OR_FCM_TRLX \ 237 | OR_FCM_EHTR) 238 239 #ifdef CONFIG_NAND 240 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 241 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 242 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 243 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 244 #else 245 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 246 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 247 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 248 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 249 #endif 250 #else 251 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 252 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 253 #endif /* CONFIG_NAND_FSL_ELBC */ 254 255 #define CONFIG_SYS_FLASH_EMPTY_INFO 256 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 257 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 258 259 #define CONFIG_HWCONFIG 260 261 /* define to use L1 as initial stack */ 262 #define CONFIG_L1_INIT_RAM 263 #define CONFIG_SYS_INIT_RAM_LOCK 264 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 265 #ifdef CONFIG_PHYS_64BIT 266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 267 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 268 /* The assembler doesn't like typecast */ 269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 270 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 271 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 272 #else 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 276 #endif 277 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 278 279 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 280 GENERATED_GBL_DATA_SIZE) 281 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 282 283 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 284 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 285 286 /* Serial Port - controlled on board with jumper J8 287 * open - index 2 288 * shorted - index 1 289 */ 290 #define CONFIG_SYS_NS16550_SERIAL 291 #define CONFIG_SYS_NS16550_REG_SIZE 1 292 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 293 294 #define CONFIG_SYS_BAUDRATE_TABLE \ 295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 296 297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 299 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 300 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 301 302 /* I2C */ 303 #define CONFIG_SYS_I2C 304 #define CONFIG_SYS_I2C_FSL 305 #define CONFIG_SYS_FSL_I2C_SPEED 400000 306 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 307 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 308 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 309 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 310 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 311 312 /* 313 * RapidIO 314 */ 315 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 316 #ifdef CONFIG_PHYS_64BIT 317 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 318 #else 319 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 320 #endif 321 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 322 323 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 326 #else 327 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 328 #endif 329 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 330 331 /* 332 * for slave u-boot IMAGE instored in master memory space, 333 * PHYS must be aligned based on the SIZE 334 */ 335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 336 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 337 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 338 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 339 /* 340 * for slave UCODE and ENV instored in master memory space, 341 * PHYS must be aligned based on the SIZE 342 */ 343 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 344 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 345 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 346 347 /* slave core release by master*/ 348 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 349 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 350 351 /* 352 * SRIO_PCIE_BOOT - SLAVE 353 */ 354 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 355 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 356 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 357 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 358 #endif 359 360 /* 361 * eSPI - Enhanced SPI 362 */ 363 #define CONFIG_SF_DEFAULT_SPEED 10000000 364 #define CONFIG_SF_DEFAULT_MODE 0 365 366 /* 367 * General PCI 368 * Memory space is mapped 1-1, but I/O space must start from 0. 369 */ 370 371 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 372 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 373 #ifdef CONFIG_PHYS_64BIT 374 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 375 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 376 #else 377 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 378 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 379 #endif 380 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 381 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 382 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 383 #ifdef CONFIG_PHYS_64BIT 384 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 385 #else 386 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 387 #endif 388 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 389 390 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 391 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 392 #ifdef CONFIG_PHYS_64BIT 393 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 394 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 395 #else 396 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 397 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 398 #endif 399 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 400 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 401 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 404 #else 405 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 406 #endif 407 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 408 409 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 410 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 411 #ifdef CONFIG_PHYS_64BIT 412 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 413 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 414 #else 415 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 416 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 417 #endif 418 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 419 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 420 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 423 #else 424 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 425 #endif 426 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 427 428 /* Qman/Bman */ 429 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 430 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 433 #else 434 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 435 #endif 436 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 437 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 438 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 439 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 440 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 441 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 442 CONFIG_SYS_BMAN_CENA_SIZE) 443 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 444 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 445 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 446 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 449 #else 450 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 451 #endif 452 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 453 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 454 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 455 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 456 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 457 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 458 CONFIG_SYS_QMAN_CENA_SIZE) 459 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 460 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 461 462 #define CONFIG_SYS_DPAA_FMAN 463 #define CONFIG_SYS_DPAA_PME 464 /* Default address of microcode for the Linux Fman driver */ 465 #if defined(CONFIG_SPIFLASH) 466 /* 467 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 468 * env, so we got 0x110000. 469 */ 470 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 471 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 472 #elif defined(CONFIG_SDCARD) 473 /* 474 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 475 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 476 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 477 */ 478 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 479 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 480 #elif defined(CONFIG_NAND) 481 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 482 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 483 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 484 /* 485 * Slave has no ucode locally, it can fetch this from remote. When implementing 486 * in two corenet boards, slave's ucode could be stored in master's memory 487 * space, the address can be mapped from slave TLB->slave LAW-> 488 * slave SRIO or PCIE outbound window->master inbound window-> 489 * master LAW->the ucode address in master's memory space. 490 */ 491 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 492 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 493 #else 494 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 495 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 496 #endif 497 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 498 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 499 500 #ifdef CONFIG_SYS_DPAA_FMAN 501 #define CONFIG_FMAN_ENET 502 #define CONFIG_PHYLIB_10G 503 #define CONFIG_PHY_VITESSE 504 #define CONFIG_PHY_TERANETICS 505 #endif 506 507 #ifdef CONFIG_PCI 508 #define CONFIG_PCI_INDIRECT_BRIDGE 509 510 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 511 #endif /* CONFIG_PCI */ 512 513 /* SATA */ 514 #define CONFIG_FSL_SATA_V2 515 516 #ifdef CONFIG_FSL_SATA_V2 517 #define CONFIG_SYS_SATA_MAX_DEVICE 2 518 #define CONFIG_SATA1 519 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 520 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 521 #define CONFIG_SATA2 522 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 523 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 524 525 #define CONFIG_LBA48 526 #endif 527 528 #ifdef CONFIG_FMAN_ENET 529 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 530 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 531 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 532 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 533 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 534 535 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 536 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 537 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 538 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 539 540 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 541 542 #define CONFIG_SYS_TBIPA_VALUE 8 543 #define CONFIG_ETHPRIME "FM1@DTSEC1" 544 #endif 545 546 /* 547 * Environment 548 */ 549 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 550 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 551 552 /* 553 * Command line configuration. 554 */ 555 556 /* 557 * USB 558 */ 559 #define CONFIG_HAS_FSL_DR_USB 560 #define CONFIG_HAS_FSL_MPH_USB 561 562 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 563 #define CONFIG_USB_EHCI_FSL 564 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 565 #endif 566 567 #ifdef CONFIG_MMC 568 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 569 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 570 #endif 571 572 /* 573 * Miscellaneous configurable options 574 */ 575 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 576 577 /* 578 * For booting Linux, the board info and command line data 579 * have to be in the first 64 MB of memory, since this is 580 * the maximum mapped by the Linux kernel during initialization. 581 */ 582 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 583 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 584 585 #ifdef CONFIG_CMD_KGDB 586 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 587 #endif 588 589 /* 590 * Environment Configuration 591 */ 592 #define CONFIG_ROOTPATH "/opt/nfsroot" 593 #define CONFIG_BOOTFILE "uImage" 594 #define CONFIG_UBOOTPATH u-boot.bin 595 596 /* default location for tftp and bootm */ 597 #define CONFIG_LOADADDR 1000000 598 599 #define __USB_PHY_TYPE utmi 600 601 #define CONFIG_EXTRA_ENV_SETTINGS \ 602 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 603 "bank_intlv=cs0_cs1\0" \ 604 "netdev=eth0\0" \ 605 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 606 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 607 "tftpflash=tftpboot $loadaddr $uboot && " \ 608 "protect off $ubootaddr +$filesize && " \ 609 "erase $ubootaddr +$filesize && " \ 610 "cp.b $loadaddr $ubootaddr $filesize && " \ 611 "protect on $ubootaddr +$filesize && " \ 612 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 613 "consoledev=ttyS0\0" \ 614 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 615 "usb_dr_mode=host\0" \ 616 "ramdiskaddr=2000000\0" \ 617 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 618 "fdtaddr=1e00000\0" \ 619 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 620 "bdev=sda3\0" 621 622 #define CONFIG_HDBOOT \ 623 "setenv bootargs root=/dev/$bdev rw " \ 624 "console=$consoledev,$baudrate $othbootargs;" \ 625 "tftp $loadaddr $bootfile;" \ 626 "tftp $fdtaddr $fdtfile;" \ 627 "bootm $loadaddr - $fdtaddr" 628 629 #define CONFIG_NFSBOOTCOMMAND \ 630 "setenv bootargs root=/dev/nfs rw " \ 631 "nfsroot=$serverip:$rootpath " \ 632 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 633 "console=$consoledev,$baudrate $othbootargs;" \ 634 "tftp $loadaddr $bootfile;" \ 635 "tftp $fdtaddr $fdtfile;" \ 636 "bootm $loadaddr - $fdtaddr" 637 638 #define CONFIG_RAMBOOTCOMMAND \ 639 "setenv bootargs root=/dev/ram rw " \ 640 "console=$consoledev,$baudrate $othbootargs;" \ 641 "tftp $ramdiskaddr $ramdiskfile;" \ 642 "tftp $loadaddr $bootfile;" \ 643 "tftp $fdtaddr $fdtfile;" \ 644 "bootm $loadaddr $ramdiskaddr $fdtaddr" 645 646 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 647 648 #include <asm/fsl_secure_boot.h> 649 650 #endif /* __CONFIG_H */ 651