1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #endif 28 29 /* High Level Configuration Options */ 30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 31 #define CONFIG_MP /* support multiple processors */ 32 33 #ifndef CONFIG_SYS_TEXT_BASE 34 #define CONFIG_SYS_TEXT_BASE 0xeff40000 35 #endif 36 37 #ifndef CONFIG_RESET_VECTOR_ADDRESS 38 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 43 #define CONFIG_PCIE1 /* PCIE controller 1 */ 44 #define CONFIG_PCIE2 /* PCIE controller 2 */ 45 #define CONFIG_PCIE3 /* PCIE controller 3 */ 46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 48 49 #define CONFIG_SYS_SRIO 50 #define CONFIG_SRIO1 /* SRIO port 1 */ 51 #define CONFIG_SRIO2 /* SRIO port 2 */ 52 #define CONFIG_SRIO_PCIE_BOOT_MASTER 53 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 54 55 #define CONFIG_ENV_OVERWRITE 56 57 #ifndef CONFIG_MTD_NOR_FLASH 58 #else 59 #define CONFIG_FLASH_CFI_DRIVER 60 #define CONFIG_SYS_FLASH_CFI 61 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 62 #endif 63 64 #if defined(CONFIG_SPIFLASH) 65 #define CONFIG_SYS_EXTRA_ENV_RELOC 66 #define CONFIG_ENV_SPI_BUS 0 67 #define CONFIG_ENV_SPI_CS 0 68 #define CONFIG_ENV_SPI_MAX_HZ 10000000 69 #define CONFIG_ENV_SPI_MODE 0 70 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 71 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 72 #define CONFIG_ENV_SECT_SIZE 0x10000 73 #elif defined(CONFIG_SDCARD) 74 #define CONFIG_SYS_EXTRA_ENV_RELOC 75 #define CONFIG_FSL_FIXED_MMC_LOCATION 76 #define CONFIG_SYS_MMC_ENV_DEV 0 77 #define CONFIG_ENV_SIZE 0x2000 78 #define CONFIG_ENV_OFFSET (512 * 1658) 79 #elif defined(CONFIG_NAND) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 82 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 83 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 84 #define CONFIG_ENV_ADDR 0xffe20000 85 #define CONFIG_ENV_SIZE 0x2000 86 #elif defined(CONFIG_ENV_IS_NOWHERE) 87 #define CONFIG_ENV_SIZE 0x2000 88 #else 89 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 90 - CONFIG_ENV_SECT_SIZE) 91 #define CONFIG_ENV_SIZE 0x2000 92 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 93 #endif 94 95 #ifndef __ASSEMBLY__ 96 unsigned long get_board_sys_clk(unsigned long dummy); 97 #endif 98 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 99 100 /* 101 * These can be toggled for performance analysis, otherwise use default. 102 */ 103 #define CONFIG_SYS_CACHE_STASHING 104 #define CONFIG_BACKSIDE_L2_CACHE 105 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 106 #define CONFIG_BTB /* toggle branch predition */ 107 108 #define CONFIG_ENABLE_36BIT_PHYS 109 110 #ifdef CONFIG_PHYS_64BIT 111 #define CONFIG_ADDR_MAP 112 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 113 #endif 114 115 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 116 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 117 #define CONFIG_SYS_MEMTEST_END 0x00400000 118 #define CONFIG_SYS_ALT_MEMTEST 119 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 120 121 /* 122 * Config the L3 Cache as L3 SRAM 123 */ 124 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 125 #ifdef CONFIG_PHYS_64BIT 126 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 127 CONFIG_RAMBOOT_TEXT_BASE) 128 #else 129 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 130 #endif 131 #define CONFIG_SYS_L3_SIZE (1024 << 10) 132 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 133 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SYS_DCSRBAR 0xf0000000 136 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 137 #endif 138 139 /* EEPROM */ 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_SYS_EEPROM_BUS_NUM 0 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 146 /* 147 * DDR Setup 148 */ 149 #define CONFIG_VERY_BIG_RAM 150 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 151 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 152 153 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 154 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 155 156 #define CONFIG_DDR_SPD 157 158 #define CONFIG_SYS_SPD_BUS_NUM 0 159 #define SPD_EEPROM_ADDRESS 0x52 160 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 161 162 /* 163 * Local Bus Definitions 164 */ 165 166 /* Set the local bus clock 1/8 of platform clock */ 167 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 168 169 /* 170 * This board doesn't have a promjet connector. 171 * However, it uses commone corenet board LAW and TLB. 172 * It is necessary to use the same start address with proper offset. 173 */ 174 #define CONFIG_SYS_FLASH_BASE 0xe0000000 175 #ifdef CONFIG_PHYS_64BIT 176 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 177 #else 178 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 179 #endif 180 181 #define CONFIG_SYS_FLASH_BR_PRELIM \ 182 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 183 BR_PS_16 | BR_V) 184 #define CONFIG_SYS_FLASH_OR_PRELIM \ 185 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 186 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 187 188 #define CONFIG_FSL_CPLD 189 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 190 #ifdef CONFIG_PHYS_64BIT 191 #define CPLD_BASE_PHYS 0xfffdf0000ull 192 #else 193 #define CPLD_BASE_PHYS CPLD_BASE 194 #endif 195 196 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 197 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 198 199 #define PIXIS_LBMAP_SWITCH 7 200 #define PIXIS_LBMAP_MASK 0xf0 201 #define PIXIS_LBMAP_SHIFT 4 202 #define PIXIS_LBMAP_ALTBANK 0x40 203 204 #define CONFIG_SYS_FLASH_QUIET_TEST 205 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 206 207 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 208 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 209 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 210 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 211 212 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 213 214 #if defined(CONFIG_RAMBOOT_PBL) 215 #define CONFIG_SYS_RAMBOOT 216 #endif 217 218 #define CONFIG_NAND_FSL_ELBC 219 /* Nand Flash */ 220 #ifdef CONFIG_NAND_FSL_ELBC 221 #define CONFIG_SYS_NAND_BASE 0xffa00000 222 #ifdef CONFIG_PHYS_64BIT 223 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 224 #else 225 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 226 #endif 227 228 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 229 #define CONFIG_SYS_MAX_NAND_DEVICE 1 230 #define CONFIG_CMD_NAND 231 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 232 233 /* NAND flash config */ 234 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 235 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 236 | BR_PS_8 /* Port Size = 8 bit */ \ 237 | BR_MS_FCM /* MSEL = FCM */ \ 238 | BR_V) /* valid */ 239 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 240 | OR_FCM_PGS /* Large Page*/ \ 241 | OR_FCM_CSCT \ 242 | OR_FCM_CST \ 243 | OR_FCM_CHT \ 244 | OR_FCM_SCY_1 \ 245 | OR_FCM_TRLX \ 246 | OR_FCM_EHTR) 247 248 #ifdef CONFIG_NAND 249 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 250 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 251 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 252 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 253 #else 254 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 255 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 256 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 257 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 258 #endif 259 #else 260 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 261 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 262 #endif /* CONFIG_NAND_FSL_ELBC */ 263 264 #define CONFIG_SYS_FLASH_EMPTY_INFO 265 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 266 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 267 268 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 269 #define CONFIG_MISC_INIT_R 270 271 #define CONFIG_HWCONFIG 272 273 /* define to use L1 as initial stack */ 274 #define CONFIG_L1_INIT_RAM 275 #define CONFIG_SYS_INIT_RAM_LOCK 276 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 277 #ifdef CONFIG_PHYS_64BIT 278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 280 /* The assembler doesn't like typecast */ 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 282 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 283 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 284 #else 285 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 288 #endif 289 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 290 291 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 292 GENERATED_GBL_DATA_SIZE) 293 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 294 295 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 296 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 297 298 /* Serial Port - controlled on board with jumper J8 299 * open - index 2 300 * shorted - index 1 301 */ 302 #define CONFIG_CONS_INDEX 1 303 #define CONFIG_SYS_NS16550_SERIAL 304 #define CONFIG_SYS_NS16550_REG_SIZE 1 305 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 306 307 #define CONFIG_SYS_BAUDRATE_TABLE \ 308 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 309 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 312 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 313 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 314 315 /* I2C */ 316 #define CONFIG_SYS_I2C 317 #define CONFIG_SYS_I2C_FSL 318 #define CONFIG_SYS_FSL_I2C_SPEED 400000 319 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 320 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 321 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 322 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 323 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 324 325 /* 326 * RapidIO 327 */ 328 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 331 #else 332 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 333 #endif 334 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 335 336 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 337 #ifdef CONFIG_PHYS_64BIT 338 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 339 #else 340 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 341 #endif 342 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 343 344 /* 345 * for slave u-boot IMAGE instored in master memory space, 346 * PHYS must be aligned based on the SIZE 347 */ 348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 352 /* 353 * for slave UCODE and ENV instored in master memory space, 354 * PHYS must be aligned based on the SIZE 355 */ 356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 359 360 /* slave core release by master*/ 361 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 362 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 363 364 /* 365 * SRIO_PCIE_BOOT - SLAVE 366 */ 367 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 368 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 370 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 371 #endif 372 373 /* 374 * eSPI - Enhanced SPI 375 */ 376 #define CONFIG_SF_DEFAULT_SPEED 10000000 377 #define CONFIG_SF_DEFAULT_MODE 0 378 379 /* 380 * General PCI 381 * Memory space is mapped 1-1, but I/O space must start from 0. 382 */ 383 384 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 385 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 386 #ifdef CONFIG_PHYS_64BIT 387 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 388 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 389 #else 390 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 391 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 392 #endif 393 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 394 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 395 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 396 #ifdef CONFIG_PHYS_64BIT 397 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 398 #else 399 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 400 #endif 401 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 402 403 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 404 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 407 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 408 #else 409 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 410 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 411 #endif 412 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 413 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 414 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 417 #else 418 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 419 #endif 420 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 421 422 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 423 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 426 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 427 #else 428 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 429 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 430 #endif 431 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 432 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 433 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 436 #else 437 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 438 #endif 439 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 440 441 /* Qman/Bman */ 442 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 443 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 444 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 447 #else 448 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 449 #endif 450 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 451 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 452 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 453 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 454 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 455 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 456 CONFIG_SYS_BMAN_CENA_SIZE) 457 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 458 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 459 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 460 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 463 #else 464 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 465 #endif 466 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 467 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 468 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 469 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 470 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 471 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 472 CONFIG_SYS_QMAN_CENA_SIZE) 473 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 474 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 475 476 #define CONFIG_SYS_DPAA_FMAN 477 #define CONFIG_SYS_DPAA_PME 478 /* Default address of microcode for the Linux Fman driver */ 479 #if defined(CONFIG_SPIFLASH) 480 /* 481 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 482 * env, so we got 0x110000. 483 */ 484 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 485 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 486 #elif defined(CONFIG_SDCARD) 487 /* 488 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 489 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 490 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 491 */ 492 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 493 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 494 #elif defined(CONFIG_NAND) 495 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 496 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 497 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 498 /* 499 * Slave has no ucode locally, it can fetch this from remote. When implementing 500 * in two corenet boards, slave's ucode could be stored in master's memory 501 * space, the address can be mapped from slave TLB->slave LAW-> 502 * slave SRIO or PCIE outbound window->master inbound window-> 503 * master LAW->the ucode address in master's memory space. 504 */ 505 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 506 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 507 #else 508 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 509 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 510 #endif 511 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 512 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 513 514 #ifdef CONFIG_SYS_DPAA_FMAN 515 #define CONFIG_FMAN_ENET 516 #define CONFIG_PHYLIB_10G 517 #define CONFIG_PHY_VITESSE 518 #define CONFIG_PHY_TERANETICS 519 #endif 520 521 #ifdef CONFIG_PCI 522 #define CONFIG_PCI_INDIRECT_BRIDGE 523 524 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 525 #endif /* CONFIG_PCI */ 526 527 /* SATA */ 528 #define CONFIG_FSL_SATA_V2 529 530 #ifdef CONFIG_FSL_SATA_V2 531 #define CONFIG_FSL_SATA 532 #define CONFIG_LIBATA 533 534 #define CONFIG_SYS_SATA_MAX_DEVICE 2 535 #define CONFIG_SATA1 536 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 537 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 538 #define CONFIG_SATA2 539 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 540 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 541 542 #define CONFIG_LBA48 543 #endif 544 545 #ifdef CONFIG_FMAN_ENET 546 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 547 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 548 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 549 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 550 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 551 552 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 553 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 554 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 555 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 556 557 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 558 559 #define CONFIG_SYS_TBIPA_VALUE 8 560 #define CONFIG_MII /* MII PHY management */ 561 #define CONFIG_ETHPRIME "FM1@DTSEC1" 562 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 563 #endif 564 565 /* 566 * Environment 567 */ 568 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 569 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 570 571 /* 572 * Command line configuration. 573 */ 574 575 #ifdef CONFIG_PCI 576 #define CONFIG_CMD_PCI 577 #endif 578 579 /* 580 * USB 581 */ 582 #define CONFIG_HAS_FSL_DR_USB 583 #define CONFIG_HAS_FSL_MPH_USB 584 585 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 586 #define CONFIG_USB_EHCI_FSL 587 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 588 #endif 589 590 #ifdef CONFIG_MMC 591 #define CONFIG_FSL_ESDHC 592 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 593 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 594 #endif 595 596 /* 597 * Miscellaneous configurable options 598 */ 599 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 600 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 601 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 602 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 603 #ifdef CONFIG_CMD_KGDB 604 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 605 #else 606 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 607 #endif 608 /* Print Buffer Size */ 609 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 610 sizeof(CONFIG_SYS_PROMPT)+16) 611 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 612 /* Boot Argument Buffer Size */ 613 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 614 615 /* 616 * For booting Linux, the board info and command line data 617 * have to be in the first 64 MB of memory, since this is 618 * the maximum mapped by the Linux kernel during initialization. 619 */ 620 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 621 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 622 623 #ifdef CONFIG_CMD_KGDB 624 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 625 #endif 626 627 /* 628 * Environment Configuration 629 */ 630 #define CONFIG_ROOTPATH "/opt/nfsroot" 631 #define CONFIG_BOOTFILE "uImage" 632 #define CONFIG_UBOOTPATH u-boot.bin 633 634 /* default location for tftp and bootm */ 635 #define CONFIG_LOADADDR 1000000 636 637 #define __USB_PHY_TYPE utmi 638 639 #define CONFIG_EXTRA_ENV_SETTINGS \ 640 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 641 "bank_intlv=cs0_cs1\0" \ 642 "netdev=eth0\0" \ 643 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 644 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 645 "tftpflash=tftpboot $loadaddr $uboot && " \ 646 "protect off $ubootaddr +$filesize && " \ 647 "erase $ubootaddr +$filesize && " \ 648 "cp.b $loadaddr $ubootaddr $filesize && " \ 649 "protect on $ubootaddr +$filesize && " \ 650 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 651 "consoledev=ttyS0\0" \ 652 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 653 "usb_dr_mode=host\0" \ 654 "ramdiskaddr=2000000\0" \ 655 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 656 "fdtaddr=1e00000\0" \ 657 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 658 "bdev=sda3\0" 659 660 #define CONFIG_HDBOOT \ 661 "setenv bootargs root=/dev/$bdev rw " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "tftp $loadaddr $bootfile;" \ 664 "tftp $fdtaddr $fdtfile;" \ 665 "bootm $loadaddr - $fdtaddr" 666 667 #define CONFIG_NFSBOOTCOMMAND \ 668 "setenv bootargs root=/dev/nfs rw " \ 669 "nfsroot=$serverip:$rootpath " \ 670 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 671 "console=$consoledev,$baudrate $othbootargs;" \ 672 "tftp $loadaddr $bootfile;" \ 673 "tftp $fdtaddr $fdtfile;" \ 674 "bootm $loadaddr - $fdtaddr" 675 676 #define CONFIG_RAMBOOTCOMMAND \ 677 "setenv bootargs root=/dev/ram rw " \ 678 "console=$consoledev,$baudrate $othbootargs;" \ 679 "tftp $ramdiskaddr $ramdiskfile;" \ 680 "tftp $loadaddr $bootfile;" \ 681 "tftp $fdtaddr $fdtfile;" \ 682 "bootm $loadaddr $ramdiskaddr $fdtaddr" 683 684 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 685 686 #include <asm/fsl_secure_boot.h> 687 688 #endif /* __CONFIG_H */ 689