1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P2041 RDB board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #define CONFIG_P2041RDB 31 #define CONFIG_PHYS_64BIT 32 #define CONFIG_PPC_P2041 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 45 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 46 #define CONFIG_MP /* support multiple processors */ 47 48 #ifndef CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_TEXT_BASE 0xeff80000 50 #endif 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 54 #endif 55 56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 57 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 58 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 59 #define CONFIG_PCI /* Enable PCI/PCIE */ 60 #define CONFIG_PCIE1 /* PCIE controler 1 */ 61 #define CONFIG_PCIE2 /* PCIE controler 2 */ 62 #define CONFIG_PCIE3 /* PCIE controler 3 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_SYS_SRIO 67 #define CONFIG_SRIO1 /* SRIO port 1 */ 68 #define CONFIG_SRIO2 /* SRIO port 2 */ 69 70 #define CONFIG_FSL_LAW /* Use common FSL init code */ 71 72 #define CONFIG_ENV_OVERWRITE 73 74 #ifdef CONFIG_SYS_NO_FLASH 75 #define CONFIG_ENV_IS_NOWHERE 76 #else 77 #define CONFIG_FLASH_CFI_DRIVER 78 #define CONFIG_SYS_FLASH_CFI 79 #endif 80 81 #if defined(CONFIG_SPIFLASH) 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_ENV_IS_IN_SPI_FLASH 84 #define CONFIG_ENV_SPI_BUS 0 85 #define CONFIG_ENV_SPI_CS 0 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 87 #define CONFIG_ENV_SPI_MODE 0 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 90 #define CONFIG_ENV_SECT_SIZE 0x10000 91 #elif defined(CONFIG_SDCARD) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1097) 97 #else 98 #define CONFIG_ENV_IS_IN_FLASH 99 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 100 - CONFIG_ENV_SECT_SIZE) 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 103 #endif 104 105 #ifndef __ASSEMBLY__ 106 unsigned long get_board_sys_clk(unsigned long dummy); 107 #endif 108 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 109 110 /* 111 * These can be toggled for performance analysis, otherwise use default. 112 */ 113 #define CONFIG_SYS_CACHE_STASHING 114 #define CONFIG_BACKSIDE_L2_CACHE 115 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 116 #define CONFIG_BTB /* toggle branch predition */ 117 118 #define CONFIG_ENABLE_36BIT_PHYS 119 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_ADDR_MAP 122 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 123 #endif 124 125 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 126 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 127 #define CONFIG_SYS_MEMTEST_END 0x00400000 128 #define CONFIG_SYS_ALT_MEMTEST 129 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 130 131 /* 132 * Config the L3 Cache as L3 SRAM 133 */ 134 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 137 CONFIG_RAMBOOT_TEXT_BASE) 138 #else 139 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 140 #endif 141 #define CONFIG_SYS_L3_SIZE (1024 << 10) 142 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 143 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_SYS_DCSRBAR 0xf0000000 146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 147 #endif 148 149 /* EEPROM */ 150 #define CONFIG_ID_EEPROM 151 #define CONFIG_SYS_I2C_EEPROM_NXID 152 #define CONFIG_SYS_EEPROM_BUS_NUM 0 153 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 155 156 /* 157 * DDR Setup 158 */ 159 #define CONFIG_VERY_BIG_RAM 160 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 161 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 162 163 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 164 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 165 166 #define CONFIG_DDR_SPD 167 #define CONFIG_FSL_DDR3 168 169 #define CONFIG_SYS_SPD_BUS_NUM 0 170 #define SPD_EEPROM_ADDRESS 0x52 171 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 172 173 /* 174 * Local Bus Definitions 175 */ 176 177 /* Set the local bus clock 1/8 of platform clock */ 178 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 179 180 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ 181 #ifdef CONFIG_PHYS_64BIT 182 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 183 #else 184 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 185 #endif 186 187 #define CONFIG_SYS_BR0_PRELIM \ 188 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 189 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 190 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 191 192 #define CONFIG_FSL_CPLD 193 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define CPLD_BASE_PHYS 0xfffdf0000ull 196 #else 197 #define CPLD_BASE_PHYS CPLD_BASE 198 #endif 199 200 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 201 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 202 203 #define PIXIS_LBMAP_SWITCH 7 204 #define PIXIS_LBMAP_MASK 0xf0 205 #define PIXIS_LBMAP_SHIFT 4 206 #define PIXIS_LBMAP_ALTBANK 0x40 207 208 #define CONFIG_SYS_FLASH_QUIET_TEST 209 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 210 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 213 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 215 216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 217 218 #if defined(CONFIG_RAMBOOT_PBL) 219 #define CONFIG_SYS_RAMBOOT 220 #endif 221 222 #define CONFIG_SYS_FLASH_EMPTY_INFO 223 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 224 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 225 226 #define CONFIG_BOARD_EARLY_INIT_F 227 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 228 #define CONFIG_MISC_INIT_R 229 230 #define CONFIG_HWCONFIG 231 232 /* define to use L1 as initial stack */ 233 #define CONFIG_L1_INIT_RAM 234 #define CONFIG_SYS_INIT_RAM_LOCK 235 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 236 #ifdef CONFIG_PHYS_64BIT 237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 238 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 239 /* The assembler doesn't like typecast */ 240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 241 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 242 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 243 #else 244 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 245 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 246 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 247 #endif 248 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 249 250 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 251 GENERATED_GBL_DATA_SIZE) 252 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 253 254 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 255 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 256 257 /* Serial Port - controlled on board with jumper J8 258 * open - index 2 259 * shorted - index 1 260 */ 261 #define CONFIG_CONS_INDEX 1 262 #define CONFIG_SYS_NS16550 263 #define CONFIG_SYS_NS16550_SERIAL 264 #define CONFIG_SYS_NS16550_REG_SIZE 1 265 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 266 267 #define CONFIG_SYS_BAUDRATE_TABLE \ 268 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 269 270 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 271 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 272 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 273 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 274 275 /* Use the HUSH parser */ 276 #define CONFIG_SYS_HUSH_PARSER 277 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 278 279 /* pass open firmware flat tree */ 280 #define CONFIG_OF_LIBFDT 281 #define CONFIG_OF_BOARD_SETUP 282 #define CONFIG_OF_STDOUT_VIA_ALIAS 283 284 /* new uImage format support */ 285 #define CONFIG_FIT 286 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 287 288 /* I2C */ 289 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 290 #define CONFIG_HARD_I2C /* I2C with hardware support */ 291 #define CONFIG_I2C_MULTI_BUS 292 #define CONFIG_I2C_CMD_TREE 293 #define CONFIG_SYS_I2C_SPEED 400000 294 #define CONFIG_SYS_I2C_SLAVE 0x7F 295 #define CONFIG_SYS_I2C_OFFSET 0x118000 296 #define CONFIG_SYS_I2C2_OFFSET 0x118100 297 298 /* 299 * RapidIO 300 */ 301 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 302 #ifdef CONFIG_PHYS_64BIT 303 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 304 #else 305 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 306 #endif 307 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 308 309 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 310 #ifdef CONFIG_PHYS_64BIT 311 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 312 #else 313 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 314 #endif 315 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 316 317 /* 318 * eSPI - Enhanced SPI 319 */ 320 #define CONFIG_FSL_ESPI 321 #define CONFIG_SPI_FLASH 322 #define CONFIG_SPI_FLASH_SPANSION 323 #define CONFIG_CMD_SF 324 #define CONFIG_SF_DEFAULT_SPEED 10000000 325 #define CONFIG_SF_DEFAULT_MODE 0 326 327 /* 328 * General PCI 329 * Memory space is mapped 1-1, but I/O space must start from 0. 330 */ 331 332 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 333 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 334 #ifdef CONFIG_PHYS_64BIT 335 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 336 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 337 #else 338 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 339 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 340 #endif 341 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 342 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 343 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 344 #ifdef CONFIG_PHYS_64BIT 345 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 346 #else 347 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 348 #endif 349 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 350 351 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 352 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 355 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 356 #else 357 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 358 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 359 #endif 360 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 361 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 362 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 365 #else 366 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 367 #endif 368 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 369 370 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 371 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 372 #ifdef CONFIG_PHYS_64BIT 373 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 374 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 375 #else 376 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 377 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 378 #endif 379 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 380 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 381 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 382 #ifdef CONFIG_PHYS_64BIT 383 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 384 #else 385 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 386 #endif 387 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 388 389 /* Qman/Bman */ 390 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 391 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 392 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 393 #ifdef CONFIG_PHYS_64BIT 394 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 395 #else 396 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 397 #endif 398 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 399 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 400 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 401 #ifdef CONFIG_PHYS_64BIT 402 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 403 #else 404 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 405 #endif 406 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 407 408 #define CONFIG_SYS_DPAA_FMAN 409 #define CONFIG_SYS_DPAA_PME 410 /* Default address of microcode for the Linux Fman driver */ 411 #if defined(CONFIG_SPIFLASH) 412 /* 413 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 414 * env, so we got 0x110000. 415 */ 416 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 417 #elif defined(CONFIG_SDCARD) 418 /* 419 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 420 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 421 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 422 */ 423 #define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) 424 #elif defined(CONFIG_NAND) 425 #define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 426 #else 427 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 428 #endif 429 #define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 430 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) 431 432 #ifdef CONFIG_SYS_DPAA_FMAN 433 #define CONFIG_FMAN_ENET 434 #define CONFIG_PHYLIB_10G 435 #define CONFIG_PHY_VITESSE 436 #define CONFIG_PHY_TERANETICS 437 #endif 438 439 #ifdef CONFIG_PCI 440 #define CONFIG_NET_MULTI 441 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 442 #define CONFIG_E1000 443 444 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 445 #define CONFIG_DOS_PARTITION 446 #endif /* CONFIG_PCI */ 447 448 /* SATA */ 449 #define CONFIG_FSL_SATA_V2 450 #ifdef CONFIG_FSL_SATA_V2 451 #define CONFIG_LIBATA 452 #define CONFIG_FSL_SATA 453 454 #define CONFIG_SYS_SATA_MAX_DEVICE 2 455 #define CONFIG_SATA1 456 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 457 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 458 #define CONFIG_SATA2 459 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 460 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 461 462 #define CONFIG_LBA48 463 #define CONFIG_CMD_SATA 464 #define CONFIG_DOS_PARTITION 465 #define CONFIG_CMD_EXT2 466 #endif 467 468 #ifdef CONFIG_FMAN_ENET 469 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 470 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 471 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 472 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 473 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 474 475 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 476 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 477 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 478 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 479 480 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 481 482 #define CONFIG_SYS_TBIPA_VALUE 8 483 #define CONFIG_MII /* MII PHY management */ 484 #define CONFIG_ETHPRIME "FM1@DTSEC1" 485 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 486 #endif 487 488 /* 489 * Environment 490 */ 491 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 492 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 493 494 /* 495 * Command line configuration. 496 */ 497 #include <config_cmd_default.h> 498 499 #define CONFIG_CMD_DHCP 500 #define CONFIG_CMD_ELF 501 #define CONFIG_CMD_ERRATA 502 #define CONFIG_CMD_GREPENV 503 #define CONFIG_CMD_IRQ 504 #define CONFIG_CMD_I2C 505 #define CONFIG_CMD_MII 506 #define CONFIG_CMD_PING 507 #define CONFIG_CMD_SETEXPR 508 509 #ifdef CONFIG_PCI 510 #define CONFIG_CMD_PCI 511 #define CONFIG_CMD_NET 512 #endif 513 514 /* 515 * USB 516 */ 517 #define CONFIG_CMD_USB 518 #define CONFIG_USB_STORAGE 519 #define CONFIG_USB_EHCI 520 #define CONFIG_USB_EHCI_FSL 521 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 522 #define CONFIG_CMD_EXT2 523 524 #define CONFIG_MMC 525 526 #ifdef CONFIG_MMC 527 #define CONFIG_FSL_ESDHC 528 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 529 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 530 #define CONFIG_CMD_MMC 531 #define CONFIG_GENERIC_MMC 532 #define CONFIG_CMD_EXT2 533 #define CONFIG_CMD_FAT 534 #define CONFIG_DOS_PARTITION 535 #endif 536 537 /* 538 * Miscellaneous configurable options 539 */ 540 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 541 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 542 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 543 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 544 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 545 #ifdef CONFIG_CMD_KGDB 546 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 547 #else 548 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 549 #endif 550 /* Print Buffer Size */ 551 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 552 sizeof(CONFIG_SYS_PROMPT)+16) 553 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 554 /* Boot Argument Buffer Size */ 555 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 556 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ 557 558 /* 559 * For booting Linux, the board info and command line data 560 * have to be in the first 64 MB of memory, since this is 561 * the maximum mapped by the Linux kernel during initialization. 562 */ 563 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 564 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 565 566 #ifdef CONFIG_CMD_KGDB 567 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 568 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 569 #endif 570 571 /* 572 * Environment Configuration 573 */ 574 #define CONFIG_ROOTPATH /opt/nfsroot 575 #define CONFIG_BOOTFILE uImage 576 #define CONFIG_UBOOTPATH u-boot.bin 577 578 /* default location for tftp and bootm */ 579 #define CONFIG_LOADADDR 1000000 580 581 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 582 583 #define CONFIG_BAUDRATE 115200 584 585 #define __USB_PHY_TYPE utmi 586 587 #define CONFIG_EXTRA_ENV_SETTINGS \ 588 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 589 "bank_intlv=cs0_cs1\0" \ 590 "netdev=eth0\0" \ 591 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 592 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 593 "tftpflash=tftpboot $loadaddr $uboot && " \ 594 "protect off $ubootaddr +$filesize && " \ 595 "erase $ubootaddr +$filesize && " \ 596 "cp.b $loadaddr $ubootaddr $filesize && " \ 597 "protect on $ubootaddr +$filesize && " \ 598 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 599 "consoledev=ttyS0\0" \ 600 "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ 601 "usb_dr_mode=host\0" \ 602 "ramdiskaddr=2000000\0" \ 603 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 604 "fdtaddr=c00000\0" \ 605 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 606 "bdev=sda3\0" \ 607 "c=ffe\0" 608 609 #define CONFIG_HDBOOT \ 610 "setenv bootargs root=/dev/$bdev rw " \ 611 "console=$consoledev,$baudrate $othbootargs;" \ 612 "tftp $loadaddr $bootfile;" \ 613 "tftp $fdtaddr $fdtfile;" \ 614 "bootm $loadaddr - $fdtaddr" 615 616 #define CONFIG_NFSBOOTCOMMAND \ 617 "setenv bootargs root=/dev/nfs rw " \ 618 "nfsroot=$serverip:$rootpath " \ 619 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 620 "console=$consoledev,$baudrate $othbootargs;" \ 621 "tftp $loadaddr $bootfile;" \ 622 "tftp $fdtaddr $fdtfile;" \ 623 "bootm $loadaddr - $fdtaddr" 624 625 #define CONFIG_RAMBOOTCOMMAND \ 626 "setenv bootargs root=/dev/ram rw " \ 627 "console=$consoledev,$baudrate $othbootargs;" \ 628 "tftp $ramdiskaddr $ramdiskfile;" \ 629 "tftp $loadaddr $bootfile;" \ 630 "tftp $fdtaddr $fdtfile;" \ 631 "bootm $loadaddr $ramdiskaddr $fdtaddr" 632 633 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 634 635 #ifdef CONFIG_SECURE_BOOT 636 #include <asm/fsl_secure_boot.h> 637 #endif 638 639 #endif /* __CONFIG_H */ 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