1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * P2041 RDB board configuration file 8 * Also supports P2040 RDB 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 15 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 17 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 18 #endif 19 20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 21 /* Set 1M boot space */ 22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 30 31 #ifndef CONFIG_RESET_VECTOR_ADDRESS 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 33 #endif 34 35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 36 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 37 #define CONFIG_PCIE1 /* PCIE controller 1 */ 38 #define CONFIG_PCIE2 /* PCIE controller 2 */ 39 #define CONFIG_PCIE3 /* PCIE controller 3 */ 40 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 41 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 #define CONFIG_SRIO2 /* SRIO port 2 */ 46 #define CONFIG_SRIO_PCIE_BOOT_MASTER 47 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 48 49 #define CONFIG_ENV_OVERWRITE 50 51 #if defined(CONFIG_SPIFLASH) 52 #define CONFIG_ENV_SPI_BUS 0 53 #define CONFIG_ENV_SPI_CS 0 54 #define CONFIG_ENV_SPI_MAX_HZ 10000000 55 #define CONFIG_ENV_SPI_MODE 0 56 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 57 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 58 #define CONFIG_ENV_SECT_SIZE 0x10000 59 #elif defined(CONFIG_SDCARD) 60 #define CONFIG_FSL_FIXED_MMC_LOCATION 61 #define CONFIG_SYS_MMC_ENV_DEV 0 62 #define CONFIG_ENV_SIZE 0x2000 63 #define CONFIG_ENV_OFFSET (512 * 1658) 64 #elif defined(CONFIG_NAND) 65 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 66 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 67 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 68 #define CONFIG_ENV_ADDR 0xffe20000 69 #define CONFIG_ENV_SIZE 0x2000 70 #elif defined(CONFIG_ENV_IS_NOWHERE) 71 #define CONFIG_ENV_SIZE 0x2000 72 #else 73 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 74 - CONFIG_ENV_SECT_SIZE) 75 #define CONFIG_ENV_SIZE 0x2000 76 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 77 #endif 78 79 #ifndef __ASSEMBLY__ 80 unsigned long get_board_sys_clk(unsigned long dummy); 81 #endif 82 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 83 84 /* 85 * These can be toggled for performance analysis, otherwise use default. 86 */ 87 #define CONFIG_SYS_CACHE_STASHING 88 #define CONFIG_BACKSIDE_L2_CACHE 89 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 90 #define CONFIG_BTB /* toggle branch predition */ 91 92 #define CONFIG_ENABLE_36BIT_PHYS 93 94 #ifdef CONFIG_PHYS_64BIT 95 #define CONFIG_ADDR_MAP 96 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 97 #endif 98 99 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 100 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 101 #define CONFIG_SYS_MEMTEST_END 0x00400000 102 103 /* 104 * Config the L3 Cache as L3 SRAM 105 */ 106 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 107 #ifdef CONFIG_PHYS_64BIT 108 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 109 CONFIG_RAMBOOT_TEXT_BASE) 110 #else 111 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 112 #endif 113 #define CONFIG_SYS_L3_SIZE (1024 << 10) 114 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 115 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_DCSRBAR 0xf0000000 118 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 119 #endif 120 121 /* EEPROM */ 122 #define CONFIG_ID_EEPROM 123 #define CONFIG_SYS_I2C_EEPROM_NXID 124 #define CONFIG_SYS_EEPROM_BUS_NUM 0 125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_VERY_BIG_RAM 132 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 134 135 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 136 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 137 138 #define CONFIG_DDR_SPD 139 140 #define CONFIG_SYS_SPD_BUS_NUM 0 141 #define SPD_EEPROM_ADDRESS 0x52 142 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 143 144 /* 145 * Local Bus Definitions 146 */ 147 148 /* Set the local bus clock 1/8 of platform clock */ 149 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 150 151 /* 152 * This board doesn't have a promjet connector. 153 * However, it uses commone corenet board LAW and TLB. 154 * It is necessary to use the same start address with proper offset. 155 */ 156 #define CONFIG_SYS_FLASH_BASE 0xe0000000 157 #ifdef CONFIG_PHYS_64BIT 158 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 159 #else 160 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 161 #endif 162 163 #define CONFIG_SYS_FLASH_BR_PRELIM \ 164 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 165 BR_PS_16 | BR_V) 166 #define CONFIG_SYS_FLASH_OR_PRELIM \ 167 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 168 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 169 170 #define CONFIG_FSL_CPLD 171 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 172 #ifdef CONFIG_PHYS_64BIT 173 #define CPLD_BASE_PHYS 0xfffdf0000ull 174 #else 175 #define CPLD_BASE_PHYS CPLD_BASE 176 #endif 177 178 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 179 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 180 181 #define PIXIS_LBMAP_SWITCH 7 182 #define PIXIS_LBMAP_MASK 0xf0 183 #define PIXIS_LBMAP_SHIFT 4 184 #define PIXIS_LBMAP_ALTBANK 0x40 185 186 #define CONFIG_SYS_FLASH_QUIET_TEST 187 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 188 189 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 190 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 191 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 193 194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 195 196 #if defined(CONFIG_RAMBOOT_PBL) 197 #define CONFIG_SYS_RAMBOOT 198 #endif 199 200 #define CONFIG_NAND_FSL_ELBC 201 /* Nand Flash */ 202 #ifdef CONFIG_NAND_FSL_ELBC 203 #define CONFIG_SYS_NAND_BASE 0xffa00000 204 #ifdef CONFIG_PHYS_64BIT 205 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 206 #else 207 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 208 #endif 209 210 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 211 #define CONFIG_SYS_MAX_NAND_DEVICE 1 212 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 213 214 /* NAND flash config */ 215 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 216 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 217 | BR_PS_8 /* Port Size = 8 bit */ \ 218 | BR_MS_FCM /* MSEL = FCM */ \ 219 | BR_V) /* valid */ 220 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 221 | OR_FCM_PGS /* Large Page*/ \ 222 | OR_FCM_CSCT \ 223 | OR_FCM_CST \ 224 | OR_FCM_CHT \ 225 | OR_FCM_SCY_1 \ 226 | OR_FCM_TRLX \ 227 | OR_FCM_EHTR) 228 229 #ifdef CONFIG_NAND 230 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 231 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 232 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 233 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 234 #else 235 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 236 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 237 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 238 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 239 #endif 240 #else 241 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 242 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 243 #endif /* CONFIG_NAND_FSL_ELBC */ 244 245 #define CONFIG_SYS_FLASH_EMPTY_INFO 246 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 247 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 248 249 #define CONFIG_HWCONFIG 250 251 /* define to use L1 as initial stack */ 252 #define CONFIG_L1_INIT_RAM 253 #define CONFIG_SYS_INIT_RAM_LOCK 254 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 255 #ifdef CONFIG_PHYS_64BIT 256 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 257 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 258 /* The assembler doesn't like typecast */ 259 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 260 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 261 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 262 #else 263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 264 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 265 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 266 #endif 267 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 268 269 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 270 GENERATED_GBL_DATA_SIZE) 271 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 272 273 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 274 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 275 276 /* Serial Port - controlled on board with jumper J8 277 * open - index 2 278 * shorted - index 1 279 */ 280 #define CONFIG_SYS_NS16550_SERIAL 281 #define CONFIG_SYS_NS16550_REG_SIZE 1 282 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 283 284 #define CONFIG_SYS_BAUDRATE_TABLE \ 285 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 286 287 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 288 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 289 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 290 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 291 292 /* I2C */ 293 #define CONFIG_SYS_I2C 294 #define CONFIG_SYS_I2C_FSL 295 #define CONFIG_SYS_FSL_I2C_SPEED 400000 296 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 297 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 298 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 299 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 300 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 301 302 /* 303 * RapidIO 304 */ 305 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 306 #ifdef CONFIG_PHYS_64BIT 307 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 308 #else 309 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 310 #endif 311 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 312 313 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 316 #else 317 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 318 #endif 319 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 320 321 /* 322 * for slave u-boot IMAGE instored in master memory space, 323 * PHYS must be aligned based on the SIZE 324 */ 325 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 326 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 327 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 328 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 329 /* 330 * for slave UCODE and ENV instored in master memory space, 331 * PHYS must be aligned based on the SIZE 332 */ 333 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 334 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 335 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 336 337 /* slave core release by master*/ 338 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 339 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 340 341 /* 342 * SRIO_PCIE_BOOT - SLAVE 343 */ 344 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 345 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 346 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 347 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 348 #endif 349 350 /* 351 * eSPI - Enhanced SPI 352 */ 353 #define CONFIG_SF_DEFAULT_SPEED 10000000 354 #define CONFIG_SF_DEFAULT_MODE 0 355 356 /* 357 * General PCI 358 * Memory space is mapped 1-1, but I/O space must start from 0. 359 */ 360 361 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 362 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 365 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 366 #else 367 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 368 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 369 #endif 370 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 371 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 372 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 373 #ifdef CONFIG_PHYS_64BIT 374 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 375 #else 376 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 377 #endif 378 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 379 380 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 381 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 382 #ifdef CONFIG_PHYS_64BIT 383 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 384 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 385 #else 386 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 387 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 388 #endif 389 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 390 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 391 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 392 #ifdef CONFIG_PHYS_64BIT 393 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 394 #else 395 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 396 #endif 397 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 398 399 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 400 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 401 #ifdef CONFIG_PHYS_64BIT 402 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 403 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 404 #else 405 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 406 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 407 #endif 408 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 409 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 410 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 411 #ifdef CONFIG_PHYS_64BIT 412 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 413 #else 414 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 415 #endif 416 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 417 418 /* Qman/Bman */ 419 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 420 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 423 #else 424 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 425 #endif 426 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 427 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 428 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 429 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 430 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 431 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 432 CONFIG_SYS_BMAN_CENA_SIZE) 433 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 434 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 435 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 436 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 439 #else 440 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 441 #endif 442 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 443 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 444 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 445 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 446 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 447 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 448 CONFIG_SYS_QMAN_CENA_SIZE) 449 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 450 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 451 452 #define CONFIG_SYS_DPAA_FMAN 453 #define CONFIG_SYS_DPAA_PME 454 /* Default address of microcode for the Linux Fman driver */ 455 #if defined(CONFIG_SPIFLASH) 456 /* 457 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 458 * env, so we got 0x110000. 459 */ 460 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 461 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 462 #elif defined(CONFIG_SDCARD) 463 /* 464 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 465 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 466 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 467 */ 468 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 469 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 470 #elif defined(CONFIG_NAND) 471 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 472 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 473 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 474 /* 475 * Slave has no ucode locally, it can fetch this from remote. When implementing 476 * in two corenet boards, slave's ucode could be stored in master's memory 477 * space, the address can be mapped from slave TLB->slave LAW-> 478 * slave SRIO or PCIE outbound window->master inbound window-> 479 * master LAW->the ucode address in master's memory space. 480 */ 481 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 482 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 483 #else 484 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 485 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 486 #endif 487 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 488 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 489 490 #ifdef CONFIG_SYS_DPAA_FMAN 491 #define CONFIG_FMAN_ENET 492 #define CONFIG_PHYLIB_10G 493 #define CONFIG_PHY_VITESSE 494 #define CONFIG_PHY_TERANETICS 495 #endif 496 497 #ifdef CONFIG_PCI 498 #define CONFIG_PCI_INDIRECT_BRIDGE 499 500 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 501 #endif /* CONFIG_PCI */ 502 503 /* SATA */ 504 #define CONFIG_FSL_SATA_V2 505 506 #ifdef CONFIG_FSL_SATA_V2 507 #define CONFIG_SYS_SATA_MAX_DEVICE 2 508 #define CONFIG_SATA1 509 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 510 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 511 #define CONFIG_SATA2 512 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 513 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 514 515 #define CONFIG_LBA48 516 #endif 517 518 #ifdef CONFIG_FMAN_ENET 519 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 520 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 521 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 522 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 523 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 524 525 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 526 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 527 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 528 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 529 530 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 531 532 #define CONFIG_SYS_TBIPA_VALUE 8 533 #define CONFIG_ETHPRIME "FM1@DTSEC1" 534 #endif 535 536 /* 537 * Environment 538 */ 539 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 540 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 541 542 /* 543 * Command line configuration. 544 */ 545 546 /* 547 * USB 548 */ 549 #define CONFIG_HAS_FSL_DR_USB 550 #define CONFIG_HAS_FSL_MPH_USB 551 552 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 553 #define CONFIG_USB_EHCI_FSL 554 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 555 #endif 556 557 #ifdef CONFIG_MMC 558 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 559 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 560 #endif 561 562 /* 563 * Miscellaneous configurable options 564 */ 565 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 566 567 /* 568 * For booting Linux, the board info and command line data 569 * have to be in the first 64 MB of memory, since this is 570 * the maximum mapped by the Linux kernel during initialization. 571 */ 572 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 573 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 574 575 #ifdef CONFIG_CMD_KGDB 576 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 577 #endif 578 579 /* 580 * Environment Configuration 581 */ 582 #define CONFIG_ROOTPATH "/opt/nfsroot" 583 #define CONFIG_BOOTFILE "uImage" 584 #define CONFIG_UBOOTPATH u-boot.bin 585 586 /* default location for tftp and bootm */ 587 #define CONFIG_LOADADDR 1000000 588 589 #define __USB_PHY_TYPE utmi 590 591 #define CONFIG_EXTRA_ENV_SETTINGS \ 592 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 593 "bank_intlv=cs0_cs1\0" \ 594 "netdev=eth0\0" \ 595 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 596 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 597 "tftpflash=tftpboot $loadaddr $uboot && " \ 598 "protect off $ubootaddr +$filesize && " \ 599 "erase $ubootaddr +$filesize && " \ 600 "cp.b $loadaddr $ubootaddr $filesize && " \ 601 "protect on $ubootaddr +$filesize && " \ 602 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 603 "consoledev=ttyS0\0" \ 604 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 605 "usb_dr_mode=host\0" \ 606 "ramdiskaddr=2000000\0" \ 607 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 608 "fdtaddr=1e00000\0" \ 609 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 610 "bdev=sda3\0" 611 612 #define CONFIG_HDBOOT \ 613 "setenv bootargs root=/dev/$bdev rw " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "tftp $loadaddr $bootfile;" \ 616 "tftp $fdtaddr $fdtfile;" \ 617 "bootm $loadaddr - $fdtaddr" 618 619 #define CONFIG_NFSBOOTCOMMAND \ 620 "setenv bootargs root=/dev/nfs rw " \ 621 "nfsroot=$serverip:$rootpath " \ 622 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 623 "console=$consoledev,$baudrate $othbootargs;" \ 624 "tftp $loadaddr $bootfile;" \ 625 "tftp $fdtaddr $fdtfile;" \ 626 "bootm $loadaddr - $fdtaddr" 627 628 #define CONFIG_RAMBOOTCOMMAND \ 629 "setenv bootargs root=/dev/ram rw " \ 630 "console=$consoledev,$baudrate $othbootargs;" \ 631 "tftp $ramdiskaddr $ramdiskfile;" \ 632 "tftp $loadaddr $bootfile;" \ 633 "tftp $fdtaddr $fdtfile;" \ 634 "bootm $loadaddr $ramdiskaddr $fdtaddr" 635 636 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 637 638 #include <asm/fsl_secure_boot.h> 639 640 #endif /* __CONFIG_H */ 641