1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #define CONFIG_SYS_NO_FLASH 28 #endif 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 32 #define CONFIG_E500 /* BOOKE e500 family */ 33 #define CONFIG_E500MC /* BOOKE e500mc family */ 34 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 35 #define CONFIG_MP /* support multiple processors */ 36 37 #ifndef CONFIG_SYS_TEXT_BASE 38 #define CONFIG_SYS_TEXT_BASE 0xeff40000 39 #endif 40 41 #ifndef CONFIG_RESET_VECTOR_ADDRESS 42 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 43 #endif 44 45 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 46 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 47 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 48 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 49 #define CONFIG_PCIE1 /* PCIE controller 1 */ 50 #define CONFIG_PCIE2 /* PCIE controller 2 */ 51 #define CONFIG_PCIE3 /* PCIE controller 3 */ 52 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 53 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 54 55 #define CONFIG_SYS_SRIO 56 #define CONFIG_SRIO1 /* SRIO port 1 */ 57 #define CONFIG_SRIO2 /* SRIO port 2 */ 58 #define CONFIG_SRIO_PCIE_BOOT_MASTER 59 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 60 61 #define CONFIG_ENV_OVERWRITE 62 63 #ifdef CONFIG_SYS_NO_FLASH 64 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 65 #define CONFIG_ENV_IS_NOWHERE 66 #endif 67 #else 68 #define CONFIG_FLASH_CFI_DRIVER 69 #define CONFIG_SYS_FLASH_CFI 70 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 71 #endif 72 73 #if defined(CONFIG_SPIFLASH) 74 #define CONFIG_SYS_EXTRA_ENV_RELOC 75 #define CONFIG_ENV_IS_IN_SPI_FLASH 76 #define CONFIG_ENV_SPI_BUS 0 77 #define CONFIG_ENV_SPI_CS 0 78 #define CONFIG_ENV_SPI_MAX_HZ 10000000 79 #define CONFIG_ENV_SPI_MODE 0 80 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 81 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 82 #define CONFIG_ENV_SECT_SIZE 0x10000 83 #elif defined(CONFIG_SDCARD) 84 #define CONFIG_SYS_EXTRA_ENV_RELOC 85 #define CONFIG_ENV_IS_IN_MMC 86 #define CONFIG_FSL_FIXED_MMC_LOCATION 87 #define CONFIG_SYS_MMC_ENV_DEV 0 88 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_OFFSET (512 * 1658) 90 #elif defined(CONFIG_NAND) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_NAND 93 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 94 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 95 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 96 #define CONFIG_ENV_IS_IN_REMOTE 97 #define CONFIG_ENV_ADDR 0xffe20000 98 #define CONFIG_ENV_SIZE 0x2000 99 #elif defined(CONFIG_ENV_IS_NOWHERE) 100 #define CONFIG_ENV_SIZE 0x2000 101 #else 102 #define CONFIG_ENV_IS_IN_FLASH 103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 104 - CONFIG_ENV_SECT_SIZE) 105 #define CONFIG_ENV_SIZE 0x2000 106 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 107 #endif 108 109 #ifndef __ASSEMBLY__ 110 unsigned long get_board_sys_clk(unsigned long dummy); 111 #endif 112 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 113 114 /* 115 * These can be toggled for performance analysis, otherwise use default. 116 */ 117 #define CONFIG_SYS_CACHE_STASHING 118 #define CONFIG_BACKSIDE_L2_CACHE 119 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 120 #define CONFIG_BTB /* toggle branch predition */ 121 122 #define CONFIG_ENABLE_36BIT_PHYS 123 124 #ifdef CONFIG_PHYS_64BIT 125 #define CONFIG_ADDR_MAP 126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 127 #endif 128 129 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 130 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 131 #define CONFIG_SYS_MEMTEST_END 0x00400000 132 #define CONFIG_SYS_ALT_MEMTEST 133 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 134 135 /* 136 * Config the L3 Cache as L3 SRAM 137 */ 138 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 141 CONFIG_RAMBOOT_TEXT_BASE) 142 #else 143 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 144 #endif 145 #define CONFIG_SYS_L3_SIZE (1024 << 10) 146 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 147 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_DCSRBAR 0xf0000000 150 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 151 #endif 152 153 /* EEPROM */ 154 #define CONFIG_ID_EEPROM 155 #define CONFIG_SYS_I2C_EEPROM_NXID 156 #define CONFIG_SYS_EEPROM_BUS_NUM 0 157 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 158 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 159 160 /* 161 * DDR Setup 162 */ 163 #define CONFIG_VERY_BIG_RAM 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 166 167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 169 170 #define CONFIG_DDR_SPD 171 #define CONFIG_SYS_FSL_DDR3 172 173 #define CONFIG_SYS_SPD_BUS_NUM 0 174 #define SPD_EEPROM_ADDRESS 0x52 175 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 176 177 /* 178 * Local Bus Definitions 179 */ 180 181 /* Set the local bus clock 1/8 of platform clock */ 182 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 183 184 /* 185 * This board doesn't have a promjet connector. 186 * However, it uses commone corenet board LAW and TLB. 187 * It is necessary to use the same start address with proper offset. 188 */ 189 #define CONFIG_SYS_FLASH_BASE 0xe0000000 190 #ifdef CONFIG_PHYS_64BIT 191 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 192 #else 193 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 194 #endif 195 196 #define CONFIG_SYS_FLASH_BR_PRELIM \ 197 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 198 BR_PS_16 | BR_V) 199 #define CONFIG_SYS_FLASH_OR_PRELIM \ 200 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 201 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 202 203 #define CONFIG_FSL_CPLD 204 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 205 #ifdef CONFIG_PHYS_64BIT 206 #define CPLD_BASE_PHYS 0xfffdf0000ull 207 #else 208 #define CPLD_BASE_PHYS CPLD_BASE 209 #endif 210 211 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 212 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 213 214 #define PIXIS_LBMAP_SWITCH 7 215 #define PIXIS_LBMAP_MASK 0xf0 216 #define PIXIS_LBMAP_SHIFT 4 217 #define PIXIS_LBMAP_ALTBANK 0x40 218 219 #define CONFIG_SYS_FLASH_QUIET_TEST 220 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 221 222 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 224 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 225 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 226 227 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 228 229 #if defined(CONFIG_RAMBOOT_PBL) 230 #define CONFIG_SYS_RAMBOOT 231 #endif 232 233 #define CONFIG_NAND_FSL_ELBC 234 /* Nand Flash */ 235 #ifdef CONFIG_NAND_FSL_ELBC 236 #define CONFIG_SYS_NAND_BASE 0xffa00000 237 #ifdef CONFIG_PHYS_64BIT 238 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 239 #else 240 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 241 #endif 242 243 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 244 #define CONFIG_SYS_MAX_NAND_DEVICE 1 245 #define CONFIG_CMD_NAND 246 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 247 248 /* NAND flash config */ 249 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 250 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 251 | BR_PS_8 /* Port Size = 8 bit */ \ 252 | BR_MS_FCM /* MSEL = FCM */ \ 253 | BR_V) /* valid */ 254 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 255 | OR_FCM_PGS /* Large Page*/ \ 256 | OR_FCM_CSCT \ 257 | OR_FCM_CST \ 258 | OR_FCM_CHT \ 259 | OR_FCM_SCY_1 \ 260 | OR_FCM_TRLX \ 261 | OR_FCM_EHTR) 262 263 #ifdef CONFIG_NAND 264 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 265 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 266 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 267 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 268 #else 269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 271 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 272 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 273 #endif 274 #else 275 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 276 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 277 #endif /* CONFIG_NAND_FSL_ELBC */ 278 279 #define CONFIG_SYS_FLASH_EMPTY_INFO 280 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 281 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 282 283 #define CONFIG_BOARD_EARLY_INIT_F 284 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 285 #define CONFIG_MISC_INIT_R 286 287 #define CONFIG_HWCONFIG 288 289 /* define to use L1 as initial stack */ 290 #define CONFIG_L1_INIT_RAM 291 #define CONFIG_SYS_INIT_RAM_LOCK 292 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 296 /* The assembler doesn't like typecast */ 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 298 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 299 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 300 #else 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 304 #endif 305 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 306 307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 308 GENERATED_GBL_DATA_SIZE) 309 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 310 311 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 312 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 313 314 /* Serial Port - controlled on board with jumper J8 315 * open - index 2 316 * shorted - index 1 317 */ 318 #define CONFIG_CONS_INDEX 1 319 #define CONFIG_SYS_NS16550_SERIAL 320 #define CONFIG_SYS_NS16550_REG_SIZE 1 321 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 322 323 #define CONFIG_SYS_BAUDRATE_TABLE \ 324 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 325 326 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 327 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 328 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 329 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 330 331 /* I2C */ 332 #define CONFIG_SYS_I2C 333 #define CONFIG_SYS_I2C_FSL 334 #define CONFIG_SYS_FSL_I2C_SPEED 400000 335 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 336 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 337 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 338 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 339 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 340 341 /* 342 * RapidIO 343 */ 344 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 345 #ifdef CONFIG_PHYS_64BIT 346 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 347 #else 348 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 349 #endif 350 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 351 352 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 355 #else 356 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 357 #endif 358 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 359 360 /* 361 * for slave u-boot IMAGE instored in master memory space, 362 * PHYS must be aligned based on the SIZE 363 */ 364 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 365 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 368 /* 369 * for slave UCODE and ENV instored in master memory space, 370 * PHYS must be aligned based on the SIZE 371 */ 372 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 373 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 375 376 /* slave core release by master*/ 377 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 378 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 379 380 /* 381 * SRIO_PCIE_BOOT - SLAVE 382 */ 383 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 384 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 385 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 386 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 387 #endif 388 389 /* 390 * eSPI - Enhanced SPI 391 */ 392 #define CONFIG_SF_DEFAULT_SPEED 10000000 393 #define CONFIG_SF_DEFAULT_MODE 0 394 395 /* 396 * General PCI 397 * Memory space is mapped 1-1, but I/O space must start from 0. 398 */ 399 400 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 401 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 404 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 405 #else 406 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 407 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 408 #endif 409 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 410 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 411 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 412 #ifdef CONFIG_PHYS_64BIT 413 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 414 #else 415 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 416 #endif 417 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 418 419 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 420 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 423 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 424 #else 425 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 426 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 427 #endif 428 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 429 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 430 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 433 #else 434 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 435 #endif 436 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 437 438 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 439 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 440 #ifdef CONFIG_PHYS_64BIT 441 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 442 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 443 #else 444 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 445 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 446 #endif 447 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 448 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 449 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 452 #else 453 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 454 #endif 455 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 456 457 /* Qman/Bman */ 458 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 459 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 460 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 463 #else 464 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 465 #endif 466 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 467 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 468 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 469 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 470 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 471 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 472 CONFIG_SYS_BMAN_CENA_SIZE) 473 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 474 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 475 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 476 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 479 #else 480 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 481 #endif 482 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 483 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 484 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 485 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 486 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 487 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 488 CONFIG_SYS_QMAN_CENA_SIZE) 489 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 490 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 491 492 #define CONFIG_SYS_DPAA_FMAN 493 #define CONFIG_SYS_DPAA_PME 494 /* Default address of microcode for the Linux Fman driver */ 495 #if defined(CONFIG_SPIFLASH) 496 /* 497 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 498 * env, so we got 0x110000. 499 */ 500 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 501 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 502 #elif defined(CONFIG_SDCARD) 503 /* 504 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 505 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 506 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 507 */ 508 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 509 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 510 #elif defined(CONFIG_NAND) 511 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 512 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 513 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 514 /* 515 * Slave has no ucode locally, it can fetch this from remote. When implementing 516 * in two corenet boards, slave's ucode could be stored in master's memory 517 * space, the address can be mapped from slave TLB->slave LAW-> 518 * slave SRIO or PCIE outbound window->master inbound window-> 519 * master LAW->the ucode address in master's memory space. 520 */ 521 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 522 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 523 #else 524 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 525 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 526 #endif 527 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 528 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 529 530 #ifdef CONFIG_SYS_DPAA_FMAN 531 #define CONFIG_FMAN_ENET 532 #define CONFIG_PHYLIB_10G 533 #define CONFIG_PHY_VITESSE 534 #define CONFIG_PHY_TERANETICS 535 #endif 536 537 #ifdef CONFIG_PCI 538 #define CONFIG_PCI_INDIRECT_BRIDGE 539 540 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 541 #define CONFIG_DOS_PARTITION 542 #endif /* CONFIG_PCI */ 543 544 /* SATA */ 545 #define CONFIG_FSL_SATA_V2 546 547 #ifdef CONFIG_FSL_SATA_V2 548 #define CONFIG_FSL_SATA 549 #define CONFIG_LIBATA 550 551 #define CONFIG_SYS_SATA_MAX_DEVICE 2 552 #define CONFIG_SATA1 553 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 554 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 555 #define CONFIG_SATA2 556 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 557 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 558 559 #define CONFIG_LBA48 560 #define CONFIG_CMD_SATA 561 #define CONFIG_DOS_PARTITION 562 #endif 563 564 #ifdef CONFIG_FMAN_ENET 565 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 566 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 567 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 568 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 569 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 570 571 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 572 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 573 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 574 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 575 576 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 577 578 #define CONFIG_SYS_TBIPA_VALUE 8 579 #define CONFIG_MII /* MII PHY management */ 580 #define CONFIG_ETHPRIME "FM1@DTSEC1" 581 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 582 #endif 583 584 /* 585 * Environment 586 */ 587 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 588 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 589 590 /* 591 * Command line configuration. 592 */ 593 #define CONFIG_CMD_ERRATA 594 #define CONFIG_CMD_IRQ 595 596 #ifdef CONFIG_PCI 597 #define CONFIG_CMD_PCI 598 #endif 599 600 /* 601 * USB 602 */ 603 #define CONFIG_HAS_FSL_DR_USB 604 #define CONFIG_HAS_FSL_MPH_USB 605 606 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 607 #define CONFIG_USB_EHCI 608 #define CONFIG_USB_EHCI_FSL 609 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 610 #endif 611 612 #define CONFIG_MMC 613 614 #ifdef CONFIG_MMC 615 #define CONFIG_FSL_ESDHC 616 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 617 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 618 #define CONFIG_GENERIC_MMC 619 #define CONFIG_DOS_PARTITION 620 #endif 621 622 /* Hash command with SHA acceleration supported in hardware */ 623 #ifdef CONFIG_FSL_CAAM 624 #define CONFIG_CMD_HASH 625 #define CONFIG_SHA_HW_ACCEL 626 #endif 627 628 /* 629 * Miscellaneous configurable options 630 */ 631 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 632 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 633 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 634 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 635 #ifdef CONFIG_CMD_KGDB 636 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 637 #else 638 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 639 #endif 640 /* Print Buffer Size */ 641 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 642 sizeof(CONFIG_SYS_PROMPT)+16) 643 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 644 /* Boot Argument Buffer Size */ 645 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 646 647 /* 648 * For booting Linux, the board info and command line data 649 * have to be in the first 64 MB of memory, since this is 650 * the maximum mapped by the Linux kernel during initialization. 651 */ 652 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 653 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 654 655 #ifdef CONFIG_CMD_KGDB 656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 657 #endif 658 659 /* 660 * Environment Configuration 661 */ 662 #define CONFIG_ROOTPATH "/opt/nfsroot" 663 #define CONFIG_BOOTFILE "uImage" 664 #define CONFIG_UBOOTPATH u-boot.bin 665 666 /* default location for tftp and bootm */ 667 #define CONFIG_LOADADDR 1000000 668 669 670 #define CONFIG_BAUDRATE 115200 671 672 #define __USB_PHY_TYPE utmi 673 674 #define CONFIG_EXTRA_ENV_SETTINGS \ 675 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 676 "bank_intlv=cs0_cs1\0" \ 677 "netdev=eth0\0" \ 678 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 679 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 680 "tftpflash=tftpboot $loadaddr $uboot && " \ 681 "protect off $ubootaddr +$filesize && " \ 682 "erase $ubootaddr +$filesize && " \ 683 "cp.b $loadaddr $ubootaddr $filesize && " \ 684 "protect on $ubootaddr +$filesize && " \ 685 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 686 "consoledev=ttyS0\0" \ 687 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 688 "usb_dr_mode=host\0" \ 689 "ramdiskaddr=2000000\0" \ 690 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 691 "fdtaddr=1e00000\0" \ 692 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 693 "bdev=sda3\0" 694 695 #define CONFIG_HDBOOT \ 696 "setenv bootargs root=/dev/$bdev rw " \ 697 "console=$consoledev,$baudrate $othbootargs;" \ 698 "tftp $loadaddr $bootfile;" \ 699 "tftp $fdtaddr $fdtfile;" \ 700 "bootm $loadaddr - $fdtaddr" 701 702 #define CONFIG_NFSBOOTCOMMAND \ 703 "setenv bootargs root=/dev/nfs rw " \ 704 "nfsroot=$serverip:$rootpath " \ 705 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 706 "console=$consoledev,$baudrate $othbootargs;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr - $fdtaddr" 710 711 #define CONFIG_RAMBOOTCOMMAND \ 712 "setenv bootargs root=/dev/ram rw " \ 713 "console=$consoledev,$baudrate $othbootargs;" \ 714 "tftp $ramdiskaddr $ramdiskfile;" \ 715 "tftp $loadaddr $bootfile;" \ 716 "tftp $fdtaddr $fdtfile;" \ 717 "bootm $loadaddr $ramdiskaddr $fdtaddr" 718 719 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 720 721 #include <asm/fsl_secure_boot.h> 722 723 #endif /* __CONFIG_H */ 724