1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P2041 RDB board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #define CONFIG_P2041RDB 31 #define CONFIG_PHYS_64BIT 32 #define CONFIG_PPC_P2041 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 45 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 46 #define CONFIG_MP /* support multiple processors */ 47 48 #ifndef CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_TEXT_BASE 0xeff80000 50 #endif 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 54 #endif 55 56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 57 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 58 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 59 #define CONFIG_PCI /* Enable PCI/PCIE */ 60 #define CONFIG_PCIE1 /* PCIE controler 1 */ 61 #define CONFIG_PCIE2 /* PCIE controler 2 */ 62 #define CONFIG_PCIE3 /* PCIE controler 3 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_SYS_SRIO 67 #define CONFIG_SRIO1 /* SRIO port 1 */ 68 #define CONFIG_SRIO2 /* SRIO port 2 */ 69 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 70 71 #define CONFIG_FSL_LAW /* Use common FSL init code */ 72 73 #define CONFIG_ENV_OVERWRITE 74 75 #ifdef CONFIG_SYS_NO_FLASH 76 #define CONFIG_ENV_IS_NOWHERE 77 #else 78 #define CONFIG_FLASH_CFI_DRIVER 79 #define CONFIG_SYS_FLASH_CFI 80 #endif 81 82 #if defined(CONFIG_SPIFLASH) 83 #define CONFIG_SYS_EXTRA_ENV_RELOC 84 #define CONFIG_ENV_IS_IN_SPI_FLASH 85 #define CONFIG_ENV_SPI_BUS 0 86 #define CONFIG_ENV_SPI_CS 0 87 #define CONFIG_ENV_SPI_MAX_HZ 10000000 88 #define CONFIG_ENV_SPI_MODE 0 89 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 90 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 91 #define CONFIG_ENV_SECT_SIZE 0x10000 92 #elif defined(CONFIG_SDCARD) 93 #define CONFIG_SYS_EXTRA_ENV_RELOC 94 #define CONFIG_ENV_IS_IN_MMC 95 #define CONFIG_FSL_FIXED_MMC_LOCATION 96 #define CONFIG_SYS_MMC_ENV_DEV 0 97 #define CONFIG_ENV_SIZE 0x2000 98 #define CONFIG_ENV_OFFSET (512 * 1097) 99 #elif defined(CONFIG_NAND) 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_ENV_IS_IN_NAND 102 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 103 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 104 #else 105 #define CONFIG_ENV_IS_IN_FLASH 106 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 107 - CONFIG_ENV_SECT_SIZE) 108 #define CONFIG_ENV_SIZE 0x2000 109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 110 #endif 111 112 #ifndef __ASSEMBLY__ 113 unsigned long get_board_sys_clk(unsigned long dummy); 114 #endif 115 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 116 117 /* 118 * These can be toggled for performance analysis, otherwise use default. 119 */ 120 #define CONFIG_SYS_CACHE_STASHING 121 #define CONFIG_BACKSIDE_L2_CACHE 122 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 123 #define CONFIG_BTB /* toggle branch predition */ 124 125 #define CONFIG_ENABLE_36BIT_PHYS 126 127 #ifdef CONFIG_PHYS_64BIT 128 #define CONFIG_ADDR_MAP 129 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 130 #endif 131 132 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 133 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 134 #define CONFIG_SYS_MEMTEST_END 0x00400000 135 #define CONFIG_SYS_ALT_MEMTEST 136 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 137 138 /* 139 * Config the L3 Cache as L3 SRAM 140 */ 141 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 144 CONFIG_RAMBOOT_TEXT_BASE) 145 #else 146 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 147 #endif 148 #define CONFIG_SYS_L3_SIZE (1024 << 10) 149 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 150 151 #ifdef CONFIG_PHYS_64BIT 152 #define CONFIG_SYS_DCSRBAR 0xf0000000 153 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 154 #endif 155 156 /* EEPROM */ 157 #define CONFIG_ID_EEPROM 158 #define CONFIG_SYS_I2C_EEPROM_NXID 159 #define CONFIG_SYS_EEPROM_BUS_NUM 0 160 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 161 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 162 163 /* 164 * DDR Setup 165 */ 166 #define CONFIG_VERY_BIG_RAM 167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 169 170 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 171 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 172 173 #define CONFIG_DDR_SPD 174 #define CONFIG_FSL_DDR3 175 176 #define CONFIG_SYS_SPD_BUS_NUM 0 177 #define SPD_EEPROM_ADDRESS 0x52 178 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 179 180 /* 181 * Local Bus Definitions 182 */ 183 184 /* Set the local bus clock 1/8 of platform clock */ 185 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 186 187 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ 188 #ifdef CONFIG_PHYS_64BIT 189 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 190 #else 191 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 192 #endif 193 194 #define CONFIG_SYS_FLASH_BR_PRELIM \ 195 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 196 #define CONFIG_SYS_FLASH_OR_PRELIM \ 197 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 198 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 199 200 #define CONFIG_FSL_CPLD 201 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 202 #ifdef CONFIG_PHYS_64BIT 203 #define CPLD_BASE_PHYS 0xfffdf0000ull 204 #else 205 #define CPLD_BASE_PHYS CPLD_BASE 206 #endif 207 208 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 209 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 210 211 #define PIXIS_LBMAP_SWITCH 7 212 #define PIXIS_LBMAP_MASK 0xf0 213 #define PIXIS_LBMAP_SHIFT 4 214 #define PIXIS_LBMAP_ALTBANK 0x40 215 216 #define CONFIG_SYS_FLASH_QUIET_TEST 217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 223 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 225 226 #if defined(CONFIG_RAMBOOT_PBL) 227 #define CONFIG_SYS_RAMBOOT 228 #endif 229 230 #define CONFIG_NAND_FSL_ELBC 231 /* Nand Flash */ 232 #ifdef CONFIG_NAND_FSL_ELBC 233 #define CONFIG_SYS_NAND_BASE 0xffa00000 234 #ifdef CONFIG_PHYS_64BIT 235 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 236 #else 237 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 238 #endif 239 240 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 241 #define CONFIG_SYS_MAX_NAND_DEVICE 1 242 #define CONFIG_MTD_NAND_VERIFY_WRITE 243 #define CONFIG_CMD_NAND 244 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 245 246 /* NAND flash config */ 247 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 248 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 249 | BR_PS_8 /* Port Size = 8 bit */ \ 250 | BR_MS_FCM /* MSEL = FCM */ \ 251 | BR_V) /* valid */ 252 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 253 | OR_FCM_PGS /* Large Page*/ \ 254 | OR_FCM_CSCT \ 255 | OR_FCM_CST \ 256 | OR_FCM_CHT \ 257 | OR_FCM_SCY_1 \ 258 | OR_FCM_TRLX \ 259 | OR_FCM_EHTR) 260 261 #ifdef CONFIG_NAND 262 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 263 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 264 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 265 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 266 #else 267 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 268 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 269 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 270 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 271 #endif 272 #else 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 275 #endif /* CONFIG_NAND_FSL_ELBC */ 276 277 #define CONFIG_SYS_FLASH_EMPTY_INFO 278 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 279 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 280 281 #define CONFIG_BOARD_EARLY_INIT_F 282 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 283 #define CONFIG_MISC_INIT_R 284 285 #define CONFIG_HWCONFIG 286 287 /* define to use L1 as initial stack */ 288 #define CONFIG_L1_INIT_RAM 289 #define CONFIG_SYS_INIT_RAM_LOCK 290 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 294 /* The assembler doesn't like typecast */ 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 296 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 297 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 298 #else 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 302 #endif 303 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 304 305 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 306 GENERATED_GBL_DATA_SIZE) 307 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 308 309 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 310 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 311 312 /* Serial Port - controlled on board with jumper J8 313 * open - index 2 314 * shorted - index 1 315 */ 316 #define CONFIG_CONS_INDEX 1 317 #define CONFIG_SYS_NS16550 318 #define CONFIG_SYS_NS16550_SERIAL 319 #define CONFIG_SYS_NS16550_REG_SIZE 1 320 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 321 322 #define CONFIG_SYS_BAUDRATE_TABLE \ 323 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 324 325 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 326 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 327 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 328 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 329 330 /* Use the HUSH parser */ 331 #define CONFIG_SYS_HUSH_PARSER 332 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 333 334 /* pass open firmware flat tree */ 335 #define CONFIG_OF_LIBFDT 336 #define CONFIG_OF_BOARD_SETUP 337 #define CONFIG_OF_STDOUT_VIA_ALIAS 338 339 /* new uImage format support */ 340 #define CONFIG_FIT 341 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 342 343 /* I2C */ 344 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 345 #define CONFIG_HARD_I2C /* I2C with hardware support */ 346 #define CONFIG_I2C_MULTI_BUS 347 #define CONFIG_I2C_CMD_TREE 348 #define CONFIG_SYS_I2C_SPEED 400000 349 #define CONFIG_SYS_I2C_SLAVE 0x7F 350 #define CONFIG_SYS_I2C_OFFSET 0x118000 351 #define CONFIG_SYS_I2C2_OFFSET 0x118100 352 353 /* 354 * RapidIO 355 */ 356 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 359 #else 360 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 361 #endif 362 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 363 364 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 365 #ifdef CONFIG_PHYS_64BIT 366 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 367 #else 368 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 369 #endif 370 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 371 372 /* 373 * eSPI - Enhanced SPI 374 */ 375 #define CONFIG_FSL_ESPI 376 #define CONFIG_SPI_FLASH 377 #define CONFIG_SPI_FLASH_SPANSION 378 #define CONFIG_CMD_SF 379 #define CONFIG_SF_DEFAULT_SPEED 10000000 380 #define CONFIG_SF_DEFAULT_MODE 0 381 382 /* 383 * General PCI 384 * Memory space is mapped 1-1, but I/O space must start from 0. 385 */ 386 387 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 388 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 389 #ifdef CONFIG_PHYS_64BIT 390 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 391 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 392 #else 393 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 394 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 395 #endif 396 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 397 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 398 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 399 #ifdef CONFIG_PHYS_64BIT 400 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 401 #else 402 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 403 #endif 404 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 405 406 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 407 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 410 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 411 #else 412 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 414 #endif 415 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 416 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 417 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 420 #else 421 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 422 #endif 423 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 424 425 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 426 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 429 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 430 #else 431 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 432 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 433 #endif 434 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 435 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 436 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 439 #else 440 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 441 #endif 442 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 443 444 /* Qman/Bman */ 445 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 446 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 447 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 450 #else 451 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 452 #endif 453 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 454 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 455 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 456 #ifdef CONFIG_PHYS_64BIT 457 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 458 #else 459 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 460 #endif 461 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 462 463 #define CONFIG_SYS_DPAA_FMAN 464 #define CONFIG_SYS_DPAA_PME 465 /* Default address of microcode for the Linux Fman driver */ 466 #if defined(CONFIG_SPIFLASH) 467 /* 468 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 469 * env, so we got 0x110000. 470 */ 471 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 472 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 473 #elif defined(CONFIG_SDCARD) 474 /* 475 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 476 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 477 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 478 */ 479 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 480 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 481 #elif defined(CONFIG_NAND) 482 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 483 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 484 #else 485 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 486 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 487 #endif 488 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 489 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 490 491 #ifdef CONFIG_SYS_DPAA_FMAN 492 #define CONFIG_FMAN_ENET 493 #define CONFIG_PHYLIB_10G 494 #define CONFIG_PHY_VITESSE 495 #define CONFIG_PHY_TERANETICS 496 #endif 497 498 #ifdef CONFIG_PCI 499 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 500 #define CONFIG_E1000 501 502 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 503 #define CONFIG_DOS_PARTITION 504 #endif /* CONFIG_PCI */ 505 506 /* SATA */ 507 #define CONFIG_FSL_SATA 508 #ifdef CONFIG_FSL_SATA 509 #define CONFIG_LIBATA 510 511 #define CONFIG_SYS_SATA_MAX_DEVICE 2 512 #define CONFIG_SATA1 513 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 514 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 515 #define CONFIG_SATA2 516 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 517 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 518 519 #define CONFIG_LBA48 520 #define CONFIG_CMD_SATA 521 #define CONFIG_DOS_PARTITION 522 #define CONFIG_CMD_EXT2 523 #endif 524 525 #ifdef CONFIG_FMAN_ENET 526 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 527 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 528 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 529 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 530 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 531 532 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 533 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 534 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 535 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 536 537 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 538 539 #define CONFIG_SYS_TBIPA_VALUE 8 540 #define CONFIG_MII /* MII PHY management */ 541 #define CONFIG_ETHPRIME "FM1@DTSEC1" 542 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 543 #endif 544 545 /* 546 * Environment 547 */ 548 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 549 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 550 551 /* 552 * Command line configuration. 553 */ 554 #include <config_cmd_default.h> 555 556 #define CONFIG_CMD_DHCP 557 #define CONFIG_CMD_ELF 558 #define CONFIG_CMD_ERRATA 559 #define CONFIG_CMD_GREPENV 560 #define CONFIG_CMD_IRQ 561 #define CONFIG_CMD_I2C 562 #define CONFIG_CMD_MII 563 #define CONFIG_CMD_PING 564 #define CONFIG_CMD_SETEXPR 565 566 #ifdef CONFIG_PCI 567 #define CONFIG_CMD_PCI 568 #define CONFIG_CMD_NET 569 #endif 570 571 /* 572 * USB 573 */ 574 #define CONFIG_CMD_USB 575 #define CONFIG_USB_STORAGE 576 #define CONFIG_USB_EHCI 577 #define CONFIG_USB_EHCI_FSL 578 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 579 #define CONFIG_CMD_EXT2 580 581 #define CONFIG_MMC 582 583 #ifdef CONFIG_MMC 584 #define CONFIG_FSL_ESDHC 585 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 586 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 587 #define CONFIG_CMD_MMC 588 #define CONFIG_GENERIC_MMC 589 #define CONFIG_CMD_EXT2 590 #define CONFIG_CMD_FAT 591 #define CONFIG_DOS_PARTITION 592 #endif 593 594 /* 595 * Miscellaneous configurable options 596 */ 597 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 598 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 599 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 600 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 601 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 602 #ifdef CONFIG_CMD_KGDB 603 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 604 #else 605 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 606 #endif 607 /* Print Buffer Size */ 608 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 609 sizeof(CONFIG_SYS_PROMPT)+16) 610 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 611 /* Boot Argument Buffer Size */ 612 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 613 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ 614 615 /* 616 * For booting Linux, the board info and command line data 617 * have to be in the first 64 MB of memory, since this is 618 * the maximum mapped by the Linux kernel during initialization. 619 */ 620 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 621 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 622 623 #ifdef CONFIG_CMD_KGDB 624 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 625 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 626 #endif 627 628 /* 629 * Environment Configuration 630 */ 631 #define CONFIG_ROOTPATH "/opt/nfsroot" 632 #define CONFIG_BOOTFILE "uImage" 633 #define CONFIG_UBOOTPATH u-boot.bin 634 635 /* default location for tftp and bootm */ 636 #define CONFIG_LOADADDR 1000000 637 638 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 639 640 #define CONFIG_BAUDRATE 115200 641 642 #define __USB_PHY_TYPE utmi 643 644 #define CONFIG_EXTRA_ENV_SETTINGS \ 645 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 646 "bank_intlv=cs0_cs1\0" \ 647 "netdev=eth0\0" \ 648 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 649 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 650 "tftpflash=tftpboot $loadaddr $uboot && " \ 651 "protect off $ubootaddr +$filesize && " \ 652 "erase $ubootaddr +$filesize && " \ 653 "cp.b $loadaddr $ubootaddr $filesize && " \ 654 "protect on $ubootaddr +$filesize && " \ 655 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 656 "consoledev=ttyS0\0" \ 657 "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ 658 "usb_dr_mode=host\0" \ 659 "ramdiskaddr=2000000\0" \ 660 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 661 "fdtaddr=c00000\0" \ 662 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 663 "bdev=sda3\0" \ 664 "c=ffe\0" 665 666 #define CONFIG_HDBOOT \ 667 "setenv bootargs root=/dev/$bdev rw " \ 668 "console=$consoledev,$baudrate $othbootargs;" \ 669 "tftp $loadaddr $bootfile;" \ 670 "tftp $fdtaddr $fdtfile;" \ 671 "bootm $loadaddr - $fdtaddr" 672 673 #define CONFIG_NFSBOOTCOMMAND \ 674 "setenv bootargs root=/dev/nfs rw " \ 675 "nfsroot=$serverip:$rootpath " \ 676 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 677 "console=$consoledev,$baudrate $othbootargs;" \ 678 "tftp $loadaddr $bootfile;" \ 679 "tftp $fdtaddr $fdtfile;" \ 680 "bootm $loadaddr - $fdtaddr" 681 682 #define CONFIG_RAMBOOTCOMMAND \ 683 "setenv bootargs root=/dev/ram rw " \ 684 "console=$consoledev,$baudrate $othbootargs;" \ 685 "tftp $ramdiskaddr $ramdiskfile;" \ 686 "tftp $loadaddr $bootfile;" \ 687 "tftp $fdtaddr $fdtfile;" \ 688 "bootm $loadaddr $ramdiskaddr $fdtaddr" 689 690 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 691 692 #ifdef CONFIG_SECURE_BOOT 693 #include <asm/fsl_secure_boot.h> 694 #endif 695 696 #endif /* __CONFIG_H */ 697