1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #define CONFIG_SYS_NO_FLASH 28 #endif 29 30 /* High Level Configuration Options */ 31 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 32 #define CONFIG_MP /* support multiple processors */ 33 34 #ifndef CONFIG_SYS_TEXT_BASE 35 #define CONFIG_SYS_TEXT_BASE 0xeff40000 36 #endif 37 38 #ifndef CONFIG_RESET_VECTOR_ADDRESS 39 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 40 #endif 41 42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 43 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_PCIE1 /* PCIE controller 1 */ 46 #define CONFIG_PCIE2 /* PCIE controller 2 */ 47 #define CONFIG_PCIE3 /* PCIE controller 3 */ 48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 49 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 50 51 #define CONFIG_SYS_SRIO 52 #define CONFIG_SRIO1 /* SRIO port 1 */ 53 #define CONFIG_SRIO2 /* SRIO port 2 */ 54 #define CONFIG_SRIO_PCIE_BOOT_MASTER 55 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 56 57 #define CONFIG_ENV_OVERWRITE 58 59 #ifdef CONFIG_SYS_NO_FLASH 60 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 61 #define CONFIG_ENV_IS_NOWHERE 62 #endif 63 #else 64 #define CONFIG_FLASH_CFI_DRIVER 65 #define CONFIG_SYS_FLASH_CFI 66 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 67 #endif 68 69 #if defined(CONFIG_SPIFLASH) 70 #define CONFIG_SYS_EXTRA_ENV_RELOC 71 #define CONFIG_ENV_IS_IN_SPI_FLASH 72 #define CONFIG_ENV_SPI_BUS 0 73 #define CONFIG_ENV_SPI_CS 0 74 #define CONFIG_ENV_SPI_MAX_HZ 10000000 75 #define CONFIG_ENV_SPI_MODE 0 76 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 77 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 78 #define CONFIG_ENV_SECT_SIZE 0x10000 79 #elif defined(CONFIG_SDCARD) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_IS_IN_MMC 82 #define CONFIG_FSL_FIXED_MMC_LOCATION 83 #define CONFIG_SYS_MMC_ENV_DEV 0 84 #define CONFIG_ENV_SIZE 0x2000 85 #define CONFIG_ENV_OFFSET (512 * 1658) 86 #elif defined(CONFIG_NAND) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_IS_IN_NAND 89 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 90 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 91 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 92 #define CONFIG_ENV_IS_IN_REMOTE 93 #define CONFIG_ENV_ADDR 0xffe20000 94 #define CONFIG_ENV_SIZE 0x2000 95 #elif defined(CONFIG_ENV_IS_NOWHERE) 96 #define CONFIG_ENV_SIZE 0x2000 97 #else 98 #define CONFIG_ENV_IS_IN_FLASH 99 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 100 - CONFIG_ENV_SECT_SIZE) 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 103 #endif 104 105 #ifndef __ASSEMBLY__ 106 unsigned long get_board_sys_clk(unsigned long dummy); 107 #endif 108 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 109 110 /* 111 * These can be toggled for performance analysis, otherwise use default. 112 */ 113 #define CONFIG_SYS_CACHE_STASHING 114 #define CONFIG_BACKSIDE_L2_CACHE 115 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 116 #define CONFIG_BTB /* toggle branch predition */ 117 118 #define CONFIG_ENABLE_36BIT_PHYS 119 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_ADDR_MAP 122 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 123 #endif 124 125 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 126 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 127 #define CONFIG_SYS_MEMTEST_END 0x00400000 128 #define CONFIG_SYS_ALT_MEMTEST 129 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 130 131 /* 132 * Config the L3 Cache as L3 SRAM 133 */ 134 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 137 CONFIG_RAMBOOT_TEXT_BASE) 138 #else 139 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 140 #endif 141 #define CONFIG_SYS_L3_SIZE (1024 << 10) 142 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 143 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_SYS_DCSRBAR 0xf0000000 146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 147 #endif 148 149 /* EEPROM */ 150 #define CONFIG_ID_EEPROM 151 #define CONFIG_SYS_I2C_EEPROM_NXID 152 #define CONFIG_SYS_EEPROM_BUS_NUM 0 153 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 155 156 /* 157 * DDR Setup 158 */ 159 #define CONFIG_VERY_BIG_RAM 160 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 161 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 162 163 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 164 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 165 166 #define CONFIG_DDR_SPD 167 168 #define CONFIG_SYS_SPD_BUS_NUM 0 169 #define SPD_EEPROM_ADDRESS 0x52 170 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 171 172 /* 173 * Local Bus Definitions 174 */ 175 176 /* Set the local bus clock 1/8 of platform clock */ 177 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 178 179 /* 180 * This board doesn't have a promjet connector. 181 * However, it uses commone corenet board LAW and TLB. 182 * It is necessary to use the same start address with proper offset. 183 */ 184 #define CONFIG_SYS_FLASH_BASE 0xe0000000 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 187 #else 188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 189 #endif 190 191 #define CONFIG_SYS_FLASH_BR_PRELIM \ 192 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 193 BR_PS_16 | BR_V) 194 #define CONFIG_SYS_FLASH_OR_PRELIM \ 195 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 196 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 197 198 #define CONFIG_FSL_CPLD 199 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 200 #ifdef CONFIG_PHYS_64BIT 201 #define CPLD_BASE_PHYS 0xfffdf0000ull 202 #else 203 #define CPLD_BASE_PHYS CPLD_BASE 204 #endif 205 206 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 207 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 208 209 #define PIXIS_LBMAP_SWITCH 7 210 #define PIXIS_LBMAP_MASK 0xf0 211 #define PIXIS_LBMAP_SHIFT 4 212 #define PIXIS_LBMAP_ALTBANK 0x40 213 214 #define CONFIG_SYS_FLASH_QUIET_TEST 215 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 216 217 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 218 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 219 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 220 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 221 222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 223 224 #if defined(CONFIG_RAMBOOT_PBL) 225 #define CONFIG_SYS_RAMBOOT 226 #endif 227 228 #define CONFIG_NAND_FSL_ELBC 229 /* Nand Flash */ 230 #ifdef CONFIG_NAND_FSL_ELBC 231 #define CONFIG_SYS_NAND_BASE 0xffa00000 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 234 #else 235 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 236 #endif 237 238 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 239 #define CONFIG_SYS_MAX_NAND_DEVICE 1 240 #define CONFIG_CMD_NAND 241 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 242 243 /* NAND flash config */ 244 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 245 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 246 | BR_PS_8 /* Port Size = 8 bit */ \ 247 | BR_MS_FCM /* MSEL = FCM */ \ 248 | BR_V) /* valid */ 249 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 250 | OR_FCM_PGS /* Large Page*/ \ 251 | OR_FCM_CSCT \ 252 | OR_FCM_CST \ 253 | OR_FCM_CHT \ 254 | OR_FCM_SCY_1 \ 255 | OR_FCM_TRLX \ 256 | OR_FCM_EHTR) 257 258 #ifdef CONFIG_NAND 259 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 260 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 261 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 262 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 263 #else 264 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 265 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 266 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 267 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 268 #endif 269 #else 270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 272 #endif /* CONFIG_NAND_FSL_ELBC */ 273 274 #define CONFIG_SYS_FLASH_EMPTY_INFO 275 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 276 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 277 278 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 279 #define CONFIG_MISC_INIT_R 280 281 #define CONFIG_HWCONFIG 282 283 /* define to use L1 as initial stack */ 284 #define CONFIG_L1_INIT_RAM 285 #define CONFIG_SYS_INIT_RAM_LOCK 286 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 287 #ifdef CONFIG_PHYS_64BIT 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 290 /* The assembler doesn't like typecast */ 291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 292 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 293 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 294 #else 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 298 #endif 299 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 300 301 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 302 GENERATED_GBL_DATA_SIZE) 303 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 304 305 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 306 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 307 308 /* Serial Port - controlled on board with jumper J8 309 * open - index 2 310 * shorted - index 1 311 */ 312 #define CONFIG_CONS_INDEX 1 313 #define CONFIG_SYS_NS16550_SERIAL 314 #define CONFIG_SYS_NS16550_REG_SIZE 1 315 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 316 317 #define CONFIG_SYS_BAUDRATE_TABLE \ 318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 319 320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 322 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 323 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 324 325 /* I2C */ 326 #define CONFIG_SYS_I2C 327 #define CONFIG_SYS_I2C_FSL 328 #define CONFIG_SYS_FSL_I2C_SPEED 400000 329 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 330 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 331 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 332 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 333 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 334 335 /* 336 * RapidIO 337 */ 338 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 339 #ifdef CONFIG_PHYS_64BIT 340 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 341 #else 342 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 343 #endif 344 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 345 346 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 347 #ifdef CONFIG_PHYS_64BIT 348 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 349 #else 350 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 351 #endif 352 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 353 354 /* 355 * for slave u-boot IMAGE instored in master memory space, 356 * PHYS must be aligned based on the SIZE 357 */ 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 360 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 361 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 362 /* 363 * for slave UCODE and ENV instored in master memory space, 364 * PHYS must be aligned based on the SIZE 365 */ 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 367 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 368 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 369 370 /* slave core release by master*/ 371 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 372 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 373 374 /* 375 * SRIO_PCIE_BOOT - SLAVE 376 */ 377 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 378 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 379 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 380 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 381 #endif 382 383 /* 384 * eSPI - Enhanced SPI 385 */ 386 #define CONFIG_SF_DEFAULT_SPEED 10000000 387 #define CONFIG_SF_DEFAULT_MODE 0 388 389 /* 390 * General PCI 391 * Memory space is mapped 1-1, but I/O space must start from 0. 392 */ 393 394 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 395 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 396 #ifdef CONFIG_PHYS_64BIT 397 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 398 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 399 #else 400 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 401 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 402 #endif 403 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 404 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 405 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 408 #else 409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 410 #endif 411 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 412 413 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 414 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 417 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 418 #else 419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 421 #endif 422 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 424 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 427 #else 428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 429 #endif 430 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 431 432 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 433 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 436 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 437 #else 438 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 439 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 440 #endif 441 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 442 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 443 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 446 #else 447 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 448 #endif 449 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 450 451 /* Qman/Bman */ 452 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 453 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 454 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 457 #else 458 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 459 #endif 460 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 461 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 462 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 463 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 464 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 465 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 466 CONFIG_SYS_BMAN_CENA_SIZE) 467 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 468 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 469 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 470 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 473 #else 474 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 475 #endif 476 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 477 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 478 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 479 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 480 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 481 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 482 CONFIG_SYS_QMAN_CENA_SIZE) 483 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 484 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 485 486 #define CONFIG_SYS_DPAA_FMAN 487 #define CONFIG_SYS_DPAA_PME 488 /* Default address of microcode for the Linux Fman driver */ 489 #if defined(CONFIG_SPIFLASH) 490 /* 491 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 492 * env, so we got 0x110000. 493 */ 494 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 495 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 496 #elif defined(CONFIG_SDCARD) 497 /* 498 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 499 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 500 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 501 */ 502 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 503 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 504 #elif defined(CONFIG_NAND) 505 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 506 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 507 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 508 /* 509 * Slave has no ucode locally, it can fetch this from remote. When implementing 510 * in two corenet boards, slave's ucode could be stored in master's memory 511 * space, the address can be mapped from slave TLB->slave LAW-> 512 * slave SRIO or PCIE outbound window->master inbound window-> 513 * master LAW->the ucode address in master's memory space. 514 */ 515 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 516 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 517 #else 518 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 519 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 520 #endif 521 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 522 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 523 524 #ifdef CONFIG_SYS_DPAA_FMAN 525 #define CONFIG_FMAN_ENET 526 #define CONFIG_PHYLIB_10G 527 #define CONFIG_PHY_VITESSE 528 #define CONFIG_PHY_TERANETICS 529 #endif 530 531 #ifdef CONFIG_PCI 532 #define CONFIG_PCI_INDIRECT_BRIDGE 533 534 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 535 #endif /* CONFIG_PCI */ 536 537 /* SATA */ 538 #define CONFIG_FSL_SATA_V2 539 540 #ifdef CONFIG_FSL_SATA_V2 541 #define CONFIG_FSL_SATA 542 #define CONFIG_LIBATA 543 544 #define CONFIG_SYS_SATA_MAX_DEVICE 2 545 #define CONFIG_SATA1 546 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 547 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 548 #define CONFIG_SATA2 549 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 550 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 551 552 #define CONFIG_LBA48 553 #define CONFIG_CMD_SATA 554 #endif 555 556 #ifdef CONFIG_FMAN_ENET 557 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 558 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 559 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 560 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 561 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 562 563 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 564 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 565 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 566 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 567 568 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 569 570 #define CONFIG_SYS_TBIPA_VALUE 8 571 #define CONFIG_MII /* MII PHY management */ 572 #define CONFIG_ETHPRIME "FM1@DTSEC1" 573 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 574 #endif 575 576 /* 577 * Environment 578 */ 579 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 580 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 581 582 /* 583 * Command line configuration. 584 */ 585 #define CONFIG_CMD_ERRATA 586 #define CONFIG_CMD_IRQ 587 588 #ifdef CONFIG_PCI 589 #define CONFIG_CMD_PCI 590 #endif 591 592 /* 593 * USB 594 */ 595 #define CONFIG_HAS_FSL_DR_USB 596 #define CONFIG_HAS_FSL_MPH_USB 597 598 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 599 #define CONFIG_USB_EHCI 600 #define CONFIG_USB_EHCI_FSL 601 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 602 #endif 603 604 #ifdef CONFIG_MMC 605 #define CONFIG_FSL_ESDHC 606 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 607 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 608 #endif 609 610 /* Hash command with SHA acceleration supported in hardware */ 611 #ifdef CONFIG_FSL_CAAM 612 #define CONFIG_CMD_HASH 613 #define CONFIG_SHA_HW_ACCEL 614 #endif 615 616 /* 617 * Miscellaneous configurable options 618 */ 619 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 620 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 621 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 622 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 623 #ifdef CONFIG_CMD_KGDB 624 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 625 #else 626 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 627 #endif 628 /* Print Buffer Size */ 629 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 630 sizeof(CONFIG_SYS_PROMPT)+16) 631 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 632 /* Boot Argument Buffer Size */ 633 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 634 635 /* 636 * For booting Linux, the board info and command line data 637 * have to be in the first 64 MB of memory, since this is 638 * the maximum mapped by the Linux kernel during initialization. 639 */ 640 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 641 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 642 643 #ifdef CONFIG_CMD_KGDB 644 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 645 #endif 646 647 /* 648 * Environment Configuration 649 */ 650 #define CONFIG_ROOTPATH "/opt/nfsroot" 651 #define CONFIG_BOOTFILE "uImage" 652 #define CONFIG_UBOOTPATH u-boot.bin 653 654 /* default location for tftp and bootm */ 655 #define CONFIG_LOADADDR 1000000 656 657 658 #define CONFIG_BAUDRATE 115200 659 660 #define __USB_PHY_TYPE utmi 661 662 #define CONFIG_EXTRA_ENV_SETTINGS \ 663 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 664 "bank_intlv=cs0_cs1\0" \ 665 "netdev=eth0\0" \ 666 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 667 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 668 "tftpflash=tftpboot $loadaddr $uboot && " \ 669 "protect off $ubootaddr +$filesize && " \ 670 "erase $ubootaddr +$filesize && " \ 671 "cp.b $loadaddr $ubootaddr $filesize && " \ 672 "protect on $ubootaddr +$filesize && " \ 673 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 674 "consoledev=ttyS0\0" \ 675 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 676 "usb_dr_mode=host\0" \ 677 "ramdiskaddr=2000000\0" \ 678 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 679 "fdtaddr=1e00000\0" \ 680 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 681 "bdev=sda3\0" 682 683 #define CONFIG_HDBOOT \ 684 "setenv bootargs root=/dev/$bdev rw " \ 685 "console=$consoledev,$baudrate $othbootargs;" \ 686 "tftp $loadaddr $bootfile;" \ 687 "tftp $fdtaddr $fdtfile;" \ 688 "bootm $loadaddr - $fdtaddr" 689 690 #define CONFIG_NFSBOOTCOMMAND \ 691 "setenv bootargs root=/dev/nfs rw " \ 692 "nfsroot=$serverip:$rootpath " \ 693 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 694 "console=$consoledev,$baudrate $othbootargs;" \ 695 "tftp $loadaddr $bootfile;" \ 696 "tftp $fdtaddr $fdtfile;" \ 697 "bootm $loadaddr - $fdtaddr" 698 699 #define CONFIG_RAMBOOTCOMMAND \ 700 "setenv bootargs root=/dev/ram rw " \ 701 "console=$consoledev,$baudrate $othbootargs;" \ 702 "tftp $ramdiskaddr $ramdiskfile;" \ 703 "tftp $loadaddr $bootfile;" \ 704 "tftp $fdtaddr $fdtfile;" \ 705 "bootm $loadaddr $ramdiskaddr $fdtaddr" 706 707 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 708 709 #include <asm/fsl_secure_boot.h> 710 711 #endif /* __CONFIG_H */ 712