1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * P2041 RDB board configuration file 8 * Also supports P2040 RDB 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 15 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 17 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 18 #endif 19 20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 21 /* Set 1M boot space */ 22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 30 31 #ifndef CONFIG_RESET_VECTOR_ADDRESS 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 33 #endif 34 35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 36 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 37 #define CONFIG_PCIE1 /* PCIE controller 1 */ 38 #define CONFIG_PCIE2 /* PCIE controller 2 */ 39 #define CONFIG_PCIE3 /* PCIE controller 3 */ 40 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 41 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 #define CONFIG_SRIO2 /* SRIO port 2 */ 46 #define CONFIG_SRIO_PCIE_BOOT_MASTER 47 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 48 49 #define CONFIG_ENV_OVERWRITE 50 51 #ifndef CONFIG_MTD_NOR_FLASH 52 #else 53 #define CONFIG_FLASH_CFI_DRIVER 54 #define CONFIG_SYS_FLASH_CFI 55 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 56 #endif 57 58 #if defined(CONFIG_SPIFLASH) 59 #define CONFIG_ENV_SPI_BUS 0 60 #define CONFIG_ENV_SPI_CS 0 61 #define CONFIG_ENV_SPI_MAX_HZ 10000000 62 #define CONFIG_ENV_SPI_MODE 0 63 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 64 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 65 #define CONFIG_ENV_SECT_SIZE 0x10000 66 #elif defined(CONFIG_SDCARD) 67 #define CONFIG_FSL_FIXED_MMC_LOCATION 68 #define CONFIG_SYS_MMC_ENV_DEV 0 69 #define CONFIG_ENV_SIZE 0x2000 70 #define CONFIG_ENV_OFFSET (512 * 1658) 71 #elif defined(CONFIG_NAND) 72 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 73 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 74 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 75 #define CONFIG_ENV_ADDR 0xffe20000 76 #define CONFIG_ENV_SIZE 0x2000 77 #elif defined(CONFIG_ENV_IS_NOWHERE) 78 #define CONFIG_ENV_SIZE 0x2000 79 #else 80 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 81 - CONFIG_ENV_SECT_SIZE) 82 #define CONFIG_ENV_SIZE 0x2000 83 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 84 #endif 85 86 #ifndef __ASSEMBLY__ 87 unsigned long get_board_sys_clk(unsigned long dummy); 88 #endif 89 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 90 91 /* 92 * These can be toggled for performance analysis, otherwise use default. 93 */ 94 #define CONFIG_SYS_CACHE_STASHING 95 #define CONFIG_BACKSIDE_L2_CACHE 96 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 97 #define CONFIG_BTB /* toggle branch predition */ 98 99 #define CONFIG_ENABLE_36BIT_PHYS 100 101 #ifdef CONFIG_PHYS_64BIT 102 #define CONFIG_ADDR_MAP 103 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 104 #endif 105 106 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 107 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 108 #define CONFIG_SYS_MEMTEST_END 0x00400000 109 110 /* 111 * Config the L3 Cache as L3 SRAM 112 */ 113 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 114 #ifdef CONFIG_PHYS_64BIT 115 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 116 CONFIG_RAMBOOT_TEXT_BASE) 117 #else 118 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 119 #endif 120 #define CONFIG_SYS_L3_SIZE (1024 << 10) 121 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 122 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_SYS_DCSRBAR 0xf0000000 125 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 126 #endif 127 128 /* EEPROM */ 129 #define CONFIG_ID_EEPROM 130 #define CONFIG_SYS_I2C_EEPROM_NXID 131 #define CONFIG_SYS_EEPROM_BUS_NUM 0 132 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 133 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 134 135 /* 136 * DDR Setup 137 */ 138 #define CONFIG_VERY_BIG_RAM 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 144 145 #define CONFIG_DDR_SPD 146 147 #define CONFIG_SYS_SPD_BUS_NUM 0 148 #define SPD_EEPROM_ADDRESS 0x52 149 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 150 151 /* 152 * Local Bus Definitions 153 */ 154 155 /* Set the local bus clock 1/8 of platform clock */ 156 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 157 158 /* 159 * This board doesn't have a promjet connector. 160 * However, it uses commone corenet board LAW and TLB. 161 * It is necessary to use the same start address with proper offset. 162 */ 163 #define CONFIG_SYS_FLASH_BASE 0xe0000000 164 #ifdef CONFIG_PHYS_64BIT 165 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 166 #else 167 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 168 #endif 169 170 #define CONFIG_SYS_FLASH_BR_PRELIM \ 171 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 172 BR_PS_16 | BR_V) 173 #define CONFIG_SYS_FLASH_OR_PRELIM \ 174 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 175 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 176 177 #define CONFIG_FSL_CPLD 178 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 179 #ifdef CONFIG_PHYS_64BIT 180 #define CPLD_BASE_PHYS 0xfffdf0000ull 181 #else 182 #define CPLD_BASE_PHYS CPLD_BASE 183 #endif 184 185 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 186 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 187 188 #define PIXIS_LBMAP_SWITCH 7 189 #define PIXIS_LBMAP_MASK 0xf0 190 #define PIXIS_LBMAP_SHIFT 4 191 #define PIXIS_LBMAP_ALTBANK 0x40 192 193 #define CONFIG_SYS_FLASH_QUIET_TEST 194 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 195 196 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 197 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 198 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 199 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 200 201 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 202 203 #if defined(CONFIG_RAMBOOT_PBL) 204 #define CONFIG_SYS_RAMBOOT 205 #endif 206 207 #define CONFIG_NAND_FSL_ELBC 208 /* Nand Flash */ 209 #ifdef CONFIG_NAND_FSL_ELBC 210 #define CONFIG_SYS_NAND_BASE 0xffa00000 211 #ifdef CONFIG_PHYS_64BIT 212 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 213 #else 214 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 215 #endif 216 217 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 218 #define CONFIG_SYS_MAX_NAND_DEVICE 1 219 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 220 221 /* NAND flash config */ 222 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 223 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 224 | BR_PS_8 /* Port Size = 8 bit */ \ 225 | BR_MS_FCM /* MSEL = FCM */ \ 226 | BR_V) /* valid */ 227 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 228 | OR_FCM_PGS /* Large Page*/ \ 229 | OR_FCM_CSCT \ 230 | OR_FCM_CST \ 231 | OR_FCM_CHT \ 232 | OR_FCM_SCY_1 \ 233 | OR_FCM_TRLX \ 234 | OR_FCM_EHTR) 235 236 #ifdef CONFIG_NAND 237 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 238 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 239 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 240 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 241 #else 242 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 243 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 244 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 245 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 246 #endif 247 #else 248 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 249 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 250 #endif /* CONFIG_NAND_FSL_ELBC */ 251 252 #define CONFIG_SYS_FLASH_EMPTY_INFO 253 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 254 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 255 256 #define CONFIG_HWCONFIG 257 258 /* define to use L1 as initial stack */ 259 #define CONFIG_L1_INIT_RAM 260 #define CONFIG_SYS_INIT_RAM_LOCK 261 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 262 #ifdef CONFIG_PHYS_64BIT 263 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 264 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 265 /* The assembler doesn't like typecast */ 266 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 267 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 268 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 269 #else 270 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 271 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 273 #endif 274 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 275 276 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 277 GENERATED_GBL_DATA_SIZE) 278 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 279 280 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 281 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 282 283 /* Serial Port - controlled on board with jumper J8 284 * open - index 2 285 * shorted - index 1 286 */ 287 #define CONFIG_SYS_NS16550_SERIAL 288 #define CONFIG_SYS_NS16550_REG_SIZE 1 289 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 290 291 #define CONFIG_SYS_BAUDRATE_TABLE \ 292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 293 294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 296 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 297 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 298 299 /* I2C */ 300 #define CONFIG_SYS_I2C 301 #define CONFIG_SYS_I2C_FSL 302 #define CONFIG_SYS_FSL_I2C_SPEED 400000 303 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 304 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 305 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 306 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 307 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 308 309 /* 310 * RapidIO 311 */ 312 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 313 #ifdef CONFIG_PHYS_64BIT 314 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 315 #else 316 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 317 #endif 318 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 319 320 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 321 #ifdef CONFIG_PHYS_64BIT 322 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 323 #else 324 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 325 #endif 326 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 327 328 /* 329 * for slave u-boot IMAGE instored in master memory space, 330 * PHYS must be aligned based on the SIZE 331 */ 332 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 336 /* 337 * for slave UCODE and ENV instored in master memory space, 338 * PHYS must be aligned based on the SIZE 339 */ 340 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 341 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 342 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 343 344 /* slave core release by master*/ 345 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 346 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 347 348 /* 349 * SRIO_PCIE_BOOT - SLAVE 350 */ 351 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 352 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 353 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 354 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 355 #endif 356 357 /* 358 * eSPI - Enhanced SPI 359 */ 360 #define CONFIG_SF_DEFAULT_SPEED 10000000 361 #define CONFIG_SF_DEFAULT_MODE 0 362 363 /* 364 * General PCI 365 * Memory space is mapped 1-1, but I/O space must start from 0. 366 */ 367 368 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 369 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 370 #ifdef CONFIG_PHYS_64BIT 371 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 372 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 373 #else 374 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 375 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 376 #endif 377 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 378 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 379 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 380 #ifdef CONFIG_PHYS_64BIT 381 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 382 #else 383 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 384 #endif 385 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 386 387 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 388 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 389 #ifdef CONFIG_PHYS_64BIT 390 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 391 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 392 #else 393 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 394 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 395 #endif 396 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 397 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 398 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 399 #ifdef CONFIG_PHYS_64BIT 400 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 401 #else 402 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 403 #endif 404 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 405 406 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 407 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 410 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 411 #else 412 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 413 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 414 #endif 415 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 416 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 417 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 420 #else 421 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 422 #endif 423 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 424 425 /* Qman/Bman */ 426 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 427 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 430 #else 431 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 432 #endif 433 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 434 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 435 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 436 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 437 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 438 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 439 CONFIG_SYS_BMAN_CENA_SIZE) 440 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 441 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 442 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 443 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 446 #else 447 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 448 #endif 449 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 450 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 451 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 452 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 453 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 454 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 455 CONFIG_SYS_QMAN_CENA_SIZE) 456 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 457 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 458 459 #define CONFIG_SYS_DPAA_FMAN 460 #define CONFIG_SYS_DPAA_PME 461 /* Default address of microcode for the Linux Fman driver */ 462 #if defined(CONFIG_SPIFLASH) 463 /* 464 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 465 * env, so we got 0x110000. 466 */ 467 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 468 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 469 #elif defined(CONFIG_SDCARD) 470 /* 471 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 472 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 473 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 474 */ 475 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 476 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 477 #elif defined(CONFIG_NAND) 478 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 479 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 480 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 481 /* 482 * Slave has no ucode locally, it can fetch this from remote. When implementing 483 * in two corenet boards, slave's ucode could be stored in master's memory 484 * space, the address can be mapped from slave TLB->slave LAW-> 485 * slave SRIO or PCIE outbound window->master inbound window-> 486 * master LAW->the ucode address in master's memory space. 487 */ 488 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 489 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 490 #else 491 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 492 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 493 #endif 494 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 495 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 496 497 #ifdef CONFIG_SYS_DPAA_FMAN 498 #define CONFIG_FMAN_ENET 499 #define CONFIG_PHYLIB_10G 500 #define CONFIG_PHY_VITESSE 501 #define CONFIG_PHY_TERANETICS 502 #endif 503 504 #ifdef CONFIG_PCI 505 #define CONFIG_PCI_INDIRECT_BRIDGE 506 507 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 508 #endif /* CONFIG_PCI */ 509 510 /* SATA */ 511 #define CONFIG_FSL_SATA_V2 512 513 #ifdef CONFIG_FSL_SATA_V2 514 #define CONFIG_SYS_SATA_MAX_DEVICE 2 515 #define CONFIG_SATA1 516 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 517 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 518 #define CONFIG_SATA2 519 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 520 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 521 522 #define CONFIG_LBA48 523 #endif 524 525 #ifdef CONFIG_FMAN_ENET 526 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 527 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 528 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 529 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 530 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 531 532 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 533 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 534 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 535 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 536 537 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 538 539 #define CONFIG_SYS_TBIPA_VALUE 8 540 #define CONFIG_ETHPRIME "FM1@DTSEC1" 541 #endif 542 543 /* 544 * Environment 545 */ 546 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 547 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 548 549 /* 550 * Command line configuration. 551 */ 552 553 /* 554 * USB 555 */ 556 #define CONFIG_HAS_FSL_DR_USB 557 #define CONFIG_HAS_FSL_MPH_USB 558 559 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 560 #define CONFIG_USB_EHCI_FSL 561 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 562 #endif 563 564 #ifdef CONFIG_MMC 565 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 566 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 567 #endif 568 569 /* 570 * Miscellaneous configurable options 571 */ 572 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 573 574 /* 575 * For booting Linux, the board info and command line data 576 * have to be in the first 64 MB of memory, since this is 577 * the maximum mapped by the Linux kernel during initialization. 578 */ 579 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 580 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 581 582 #ifdef CONFIG_CMD_KGDB 583 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 584 #endif 585 586 /* 587 * Environment Configuration 588 */ 589 #define CONFIG_ROOTPATH "/opt/nfsroot" 590 #define CONFIG_BOOTFILE "uImage" 591 #define CONFIG_UBOOTPATH u-boot.bin 592 593 /* default location for tftp and bootm */ 594 #define CONFIG_LOADADDR 1000000 595 596 #define __USB_PHY_TYPE utmi 597 598 #define CONFIG_EXTRA_ENV_SETTINGS \ 599 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 600 "bank_intlv=cs0_cs1\0" \ 601 "netdev=eth0\0" \ 602 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 603 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 604 "tftpflash=tftpboot $loadaddr $uboot && " \ 605 "protect off $ubootaddr +$filesize && " \ 606 "erase $ubootaddr +$filesize && " \ 607 "cp.b $loadaddr $ubootaddr $filesize && " \ 608 "protect on $ubootaddr +$filesize && " \ 609 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 610 "consoledev=ttyS0\0" \ 611 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 612 "usb_dr_mode=host\0" \ 613 "ramdiskaddr=2000000\0" \ 614 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 615 "fdtaddr=1e00000\0" \ 616 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 617 "bdev=sda3\0" 618 619 #define CONFIG_HDBOOT \ 620 "setenv bootargs root=/dev/$bdev rw " \ 621 "console=$consoledev,$baudrate $othbootargs;" \ 622 "tftp $loadaddr $bootfile;" \ 623 "tftp $fdtaddr $fdtfile;" \ 624 "bootm $loadaddr - $fdtaddr" 625 626 #define CONFIG_NFSBOOTCOMMAND \ 627 "setenv bootargs root=/dev/nfs rw " \ 628 "nfsroot=$serverip:$rootpath " \ 629 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 630 "console=$consoledev,$baudrate $othbootargs;" \ 631 "tftp $loadaddr $bootfile;" \ 632 "tftp $fdtaddr $fdtfile;" \ 633 "bootm $loadaddr - $fdtaddr" 634 635 #define CONFIG_RAMBOOTCOMMAND \ 636 "setenv bootargs root=/dev/ram rw " \ 637 "console=$consoledev,$baudrate $othbootargs;" \ 638 "tftp $ramdiskaddr $ramdiskfile;" \ 639 "tftp $loadaddr $bootfile;" \ 640 "tftp $fdtaddr $fdtfile;" \ 641 "bootm $loadaddr $ramdiskaddr $fdtaddr" 642 643 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 644 645 #include <asm/fsl_secure_boot.h> 646 647 #endif /* __CONFIG_H */ 648