1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_P2041RDB 15 #define CONFIG_PPC_P2041 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 20 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 21 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 22 #endif 23 24 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 25 /* Set 1M boot space */ 26 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 27 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 28 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 30 #define CONFIG_SYS_NO_FLASH 31 #endif 32 33 /* High Level Configuration Options */ 34 #define CONFIG_BOOKE 35 #define CONFIG_E500 /* BOOKE e500 family */ 36 #define CONFIG_E500MC /* BOOKE e500mc family */ 37 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 38 #define CONFIG_MP /* support multiple processors */ 39 40 #ifndef CONFIG_SYS_TEXT_BASE 41 #define CONFIG_SYS_TEXT_BASE 0xeff40000 42 #endif 43 44 #ifndef CONFIG_RESET_VECTOR_ADDRESS 45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 46 #endif 47 48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 49 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 50 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 51 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 52 #define CONFIG_PCIE1 /* PCIE controller 1 */ 53 #define CONFIG_PCIE2 /* PCIE controller 2 */ 54 #define CONFIG_PCIE3 /* PCIE controller 3 */ 55 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 58 #define CONFIG_SYS_SRIO 59 #define CONFIG_SRIO1 /* SRIO port 1 */ 60 #define CONFIG_SRIO2 /* SRIO port 2 */ 61 #define CONFIG_SRIO_PCIE_BOOT_MASTER 62 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 63 64 #define CONFIG_FSL_LAW /* Use common FSL init code */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifdef CONFIG_SYS_NO_FLASH 69 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 70 #define CONFIG_ENV_IS_NOWHERE 71 #endif 72 #else 73 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #endif 77 78 #if defined(CONFIG_SPIFLASH) 79 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_ENV_IS_IN_SPI_FLASH 81 #define CONFIG_ENV_SPI_BUS 0 82 #define CONFIG_ENV_SPI_CS 0 83 #define CONFIG_ENV_SPI_MAX_HZ 10000000 84 #define CONFIG_ENV_SPI_MODE 0 85 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 86 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 87 #define CONFIG_ENV_SECT_SIZE 0x10000 88 #elif defined(CONFIG_SDCARD) 89 #define CONFIG_SYS_EXTRA_ENV_RELOC 90 #define CONFIG_ENV_IS_IN_MMC 91 #define CONFIG_FSL_FIXED_MMC_LOCATION 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_OFFSET (512 * 1658) 95 #elif defined(CONFIG_NAND) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 101 #define CONFIG_ENV_IS_IN_REMOTE 102 #define CONFIG_ENV_ADDR 0xffe20000 103 #define CONFIG_ENV_SIZE 0x2000 104 #elif defined(CONFIG_ENV_IS_NOWHERE) 105 #define CONFIG_ENV_SIZE 0x2000 106 #else 107 #define CONFIG_ENV_IS_IN_FLASH 108 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 109 - CONFIG_ENV_SECT_SIZE) 110 #define CONFIG_ENV_SIZE 0x2000 111 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 112 #endif 113 114 #ifndef __ASSEMBLY__ 115 unsigned long get_board_sys_clk(unsigned long dummy); 116 #endif 117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_BTB /* toggle branch predition */ 126 127 #define CONFIG_ENABLE_36BIT_PHYS 128 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_ADDR_MAP 131 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 132 #endif 133 134 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 135 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 136 #define CONFIG_SYS_MEMTEST_END 0x00400000 137 #define CONFIG_SYS_ALT_MEMTEST 138 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 139 140 /* 141 * Config the L3 Cache as L3 SRAM 142 */ 143 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 144 #ifdef CONFIG_PHYS_64BIT 145 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 146 CONFIG_RAMBOOT_TEXT_BASE) 147 #else 148 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 149 #endif 150 #define CONFIG_SYS_L3_SIZE (1024 << 10) 151 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 152 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_DCSRBAR 0xf0000000 155 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 156 #endif 157 158 /* EEPROM */ 159 #define CONFIG_ID_EEPROM 160 #define CONFIG_SYS_I2C_EEPROM_NXID 161 #define CONFIG_SYS_EEPROM_BUS_NUM 0 162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 164 165 /* 166 * DDR Setup 167 */ 168 #define CONFIG_VERY_BIG_RAM 169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 171 172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 173 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 174 175 #define CONFIG_DDR_SPD 176 #define CONFIG_SYS_FSL_DDR3 177 178 #define CONFIG_SYS_SPD_BUS_NUM 0 179 #define SPD_EEPROM_ADDRESS 0x52 180 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 181 182 /* 183 * Local Bus Definitions 184 */ 185 186 /* Set the local bus clock 1/8 of platform clock */ 187 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 188 189 /* 190 * This board doesn't have a promjet connector. 191 * However, it uses commone corenet board LAW and TLB. 192 * It is necessary to use the same start address with proper offset. 193 */ 194 #define CONFIG_SYS_FLASH_BASE 0xe0000000 195 #ifdef CONFIG_PHYS_64BIT 196 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 197 #else 198 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 199 #endif 200 201 #define CONFIG_SYS_FLASH_BR_PRELIM \ 202 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 203 BR_PS_16 | BR_V) 204 #define CONFIG_SYS_FLASH_OR_PRELIM \ 205 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 206 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 207 208 #define CONFIG_FSL_CPLD 209 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 210 #ifdef CONFIG_PHYS_64BIT 211 #define CPLD_BASE_PHYS 0xfffdf0000ull 212 #else 213 #define CPLD_BASE_PHYS CPLD_BASE 214 #endif 215 216 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 217 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 218 219 #define PIXIS_LBMAP_SWITCH 7 220 #define PIXIS_LBMAP_MASK 0xf0 221 #define PIXIS_LBMAP_SHIFT 4 222 #define PIXIS_LBMAP_ALTBANK 0x40 223 224 #define CONFIG_SYS_FLASH_QUIET_TEST 225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 226 227 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 231 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 233 234 #if defined(CONFIG_RAMBOOT_PBL) 235 #define CONFIG_SYS_RAMBOOT 236 #endif 237 238 #define CONFIG_NAND_FSL_ELBC 239 /* Nand Flash */ 240 #ifdef CONFIG_NAND_FSL_ELBC 241 #define CONFIG_SYS_NAND_BASE 0xffa00000 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 244 #else 245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 246 #endif 247 248 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 249 #define CONFIG_SYS_MAX_NAND_DEVICE 1 250 #define CONFIG_CMD_NAND 251 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 252 253 /* NAND flash config */ 254 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 255 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 256 | BR_PS_8 /* Port Size = 8 bit */ \ 257 | BR_MS_FCM /* MSEL = FCM */ \ 258 | BR_V) /* valid */ 259 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 260 | OR_FCM_PGS /* Large Page*/ \ 261 | OR_FCM_CSCT \ 262 | OR_FCM_CST \ 263 | OR_FCM_CHT \ 264 | OR_FCM_SCY_1 \ 265 | OR_FCM_TRLX \ 266 | OR_FCM_EHTR) 267 268 #ifdef CONFIG_NAND 269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 271 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 272 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 273 #else 274 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 275 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 276 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 277 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 278 #endif 279 #else 280 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 281 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 282 #endif /* CONFIG_NAND_FSL_ELBC */ 283 284 #define CONFIG_SYS_FLASH_EMPTY_INFO 285 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 286 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 287 288 #define CONFIG_BOARD_EARLY_INIT_F 289 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 290 #define CONFIG_MISC_INIT_R 291 292 #define CONFIG_HWCONFIG 293 294 /* define to use L1 as initial stack */ 295 #define CONFIG_L1_INIT_RAM 296 #define CONFIG_SYS_INIT_RAM_LOCK 297 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 298 #ifdef CONFIG_PHYS_64BIT 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 301 /* The assembler doesn't like typecast */ 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 303 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 304 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 305 #else 306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 309 #endif 310 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 311 312 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 313 GENERATED_GBL_DATA_SIZE) 314 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 315 316 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 317 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 318 319 /* Serial Port - controlled on board with jumper J8 320 * open - index 2 321 * shorted - index 1 322 */ 323 #define CONFIG_CONS_INDEX 1 324 #define CONFIG_SYS_NS16550_SERIAL 325 #define CONFIG_SYS_NS16550_REG_SIZE 1 326 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 327 328 #define CONFIG_SYS_BAUDRATE_TABLE \ 329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 330 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 333 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 334 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 335 336 /* I2C */ 337 #define CONFIG_SYS_I2C 338 #define CONFIG_SYS_I2C_FSL 339 #define CONFIG_SYS_FSL_I2C_SPEED 400000 340 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 341 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 342 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 343 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 344 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 345 346 /* 347 * RapidIO 348 */ 349 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 350 #ifdef CONFIG_PHYS_64BIT 351 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 352 #else 353 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 354 #endif 355 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 356 357 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 358 #ifdef CONFIG_PHYS_64BIT 359 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 360 #else 361 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 362 #endif 363 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 364 365 /* 366 * for slave u-boot IMAGE instored in master memory space, 367 * PHYS must be aligned based on the SIZE 368 */ 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 373 /* 374 * for slave UCODE and ENV instored in master memory space, 375 * PHYS must be aligned based on the SIZE 376 */ 377 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 379 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 380 381 /* slave core release by master*/ 382 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 383 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 384 385 /* 386 * SRIO_PCIE_BOOT - SLAVE 387 */ 388 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 389 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 390 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 391 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 392 #endif 393 394 /* 395 * eSPI - Enhanced SPI 396 */ 397 #define CONFIG_SF_DEFAULT_SPEED 10000000 398 #define CONFIG_SF_DEFAULT_MODE 0 399 400 /* 401 * General PCI 402 * Memory space is mapped 1-1, but I/O space must start from 0. 403 */ 404 405 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 406 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 410 #else 411 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 412 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 413 #endif 414 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 415 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 416 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 419 #else 420 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 421 #endif 422 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 423 424 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 425 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 428 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 429 #else 430 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 431 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 432 #endif 433 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 434 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 435 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 438 #else 439 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 440 #endif 441 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 442 443 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 444 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 447 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 448 #else 449 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 450 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 451 #endif 452 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 453 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 454 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 457 #else 458 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 459 #endif 460 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 461 462 /* Qman/Bman */ 463 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 464 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 465 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 466 #ifdef CONFIG_PHYS_64BIT 467 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 468 #else 469 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 470 #endif 471 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 472 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 473 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 474 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 475 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 476 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 477 CONFIG_SYS_BMAN_CENA_SIZE) 478 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 479 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 480 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 481 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 482 #ifdef CONFIG_PHYS_64BIT 483 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 484 #else 485 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 486 #endif 487 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 488 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 489 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 490 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 491 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 492 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 493 CONFIG_SYS_QMAN_CENA_SIZE) 494 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 495 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 496 497 #define CONFIG_SYS_DPAA_FMAN 498 #define CONFIG_SYS_DPAA_PME 499 /* Default address of microcode for the Linux Fman driver */ 500 #if defined(CONFIG_SPIFLASH) 501 /* 502 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 503 * env, so we got 0x110000. 504 */ 505 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 506 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 507 #elif defined(CONFIG_SDCARD) 508 /* 509 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 510 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 511 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 512 */ 513 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 514 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 515 #elif defined(CONFIG_NAND) 516 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 517 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 518 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 519 /* 520 * Slave has no ucode locally, it can fetch this from remote. When implementing 521 * in two corenet boards, slave's ucode could be stored in master's memory 522 * space, the address can be mapped from slave TLB->slave LAW-> 523 * slave SRIO or PCIE outbound window->master inbound window-> 524 * master LAW->the ucode address in master's memory space. 525 */ 526 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 527 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 528 #else 529 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 530 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 531 #endif 532 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 533 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 534 535 #ifdef CONFIG_SYS_DPAA_FMAN 536 #define CONFIG_FMAN_ENET 537 #define CONFIG_PHYLIB_10G 538 #define CONFIG_PHY_VITESSE 539 #define CONFIG_PHY_TERANETICS 540 #endif 541 542 #ifdef CONFIG_PCI 543 #define CONFIG_PCI_INDIRECT_BRIDGE 544 545 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 546 #define CONFIG_DOS_PARTITION 547 #endif /* CONFIG_PCI */ 548 549 /* SATA */ 550 #define CONFIG_FSL_SATA_V2 551 552 #ifdef CONFIG_FSL_SATA_V2 553 #define CONFIG_FSL_SATA 554 #define CONFIG_LIBATA 555 556 #define CONFIG_SYS_SATA_MAX_DEVICE 2 557 #define CONFIG_SATA1 558 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 559 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 560 #define CONFIG_SATA2 561 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 562 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 563 564 #define CONFIG_LBA48 565 #define CONFIG_CMD_SATA 566 #define CONFIG_DOS_PARTITION 567 #endif 568 569 #ifdef CONFIG_FMAN_ENET 570 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 571 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 572 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 573 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 574 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 575 576 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 577 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 578 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 579 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 580 581 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 582 583 #define CONFIG_SYS_TBIPA_VALUE 8 584 #define CONFIG_MII /* MII PHY management */ 585 #define CONFIG_ETHPRIME "FM1@DTSEC1" 586 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 587 #endif 588 589 /* 590 * Environment 591 */ 592 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 593 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 594 595 /* 596 * Command line configuration. 597 */ 598 #define CONFIG_CMD_ERRATA 599 #define CONFIG_CMD_IRQ 600 601 #ifdef CONFIG_PCI 602 #define CONFIG_CMD_PCI 603 #endif 604 605 /* 606 * USB 607 */ 608 #define CONFIG_HAS_FSL_DR_USB 609 #define CONFIG_HAS_FSL_MPH_USB 610 611 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 612 #define CONFIG_USB_EHCI 613 #define CONFIG_USB_EHCI_FSL 614 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 615 #endif 616 617 #define CONFIG_MMC 618 619 #ifdef CONFIG_MMC 620 #define CONFIG_FSL_ESDHC 621 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 622 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 623 #define CONFIG_GENERIC_MMC 624 #define CONFIG_DOS_PARTITION 625 #endif 626 627 /* Hash command with SHA acceleration supported in hardware */ 628 #ifdef CONFIG_FSL_CAAM 629 #define CONFIG_CMD_HASH 630 #define CONFIG_SHA_HW_ACCEL 631 #endif 632 633 /* 634 * Miscellaneous configurable options 635 */ 636 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 637 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 638 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 639 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 640 #ifdef CONFIG_CMD_KGDB 641 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 642 #else 643 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 644 #endif 645 /* Print Buffer Size */ 646 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 647 sizeof(CONFIG_SYS_PROMPT)+16) 648 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 649 /* Boot Argument Buffer Size */ 650 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 651 652 /* 653 * For booting Linux, the board info and command line data 654 * have to be in the first 64 MB of memory, since this is 655 * the maximum mapped by the Linux kernel during initialization. 656 */ 657 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 658 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 659 660 #ifdef CONFIG_CMD_KGDB 661 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 662 #endif 663 664 /* 665 * Environment Configuration 666 */ 667 #define CONFIG_ROOTPATH "/opt/nfsroot" 668 #define CONFIG_BOOTFILE "uImage" 669 #define CONFIG_UBOOTPATH u-boot.bin 670 671 /* default location for tftp and bootm */ 672 #define CONFIG_LOADADDR 1000000 673 674 675 #define CONFIG_BAUDRATE 115200 676 677 #define __USB_PHY_TYPE utmi 678 679 #define CONFIG_EXTRA_ENV_SETTINGS \ 680 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 681 "bank_intlv=cs0_cs1\0" \ 682 "netdev=eth0\0" \ 683 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 684 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 685 "tftpflash=tftpboot $loadaddr $uboot && " \ 686 "protect off $ubootaddr +$filesize && " \ 687 "erase $ubootaddr +$filesize && " \ 688 "cp.b $loadaddr $ubootaddr $filesize && " \ 689 "protect on $ubootaddr +$filesize && " \ 690 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 691 "consoledev=ttyS0\0" \ 692 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 693 "usb_dr_mode=host\0" \ 694 "ramdiskaddr=2000000\0" \ 695 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 696 "fdtaddr=1e00000\0" \ 697 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 698 "bdev=sda3\0" 699 700 #define CONFIG_HDBOOT \ 701 "setenv bootargs root=/dev/$bdev rw " \ 702 "console=$consoledev,$baudrate $othbootargs;" \ 703 "tftp $loadaddr $bootfile;" \ 704 "tftp $fdtaddr $fdtfile;" \ 705 "bootm $loadaddr - $fdtaddr" 706 707 #define CONFIG_NFSBOOTCOMMAND \ 708 "setenv bootargs root=/dev/nfs rw " \ 709 "nfsroot=$serverip:$rootpath " \ 710 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 711 "console=$consoledev,$baudrate $othbootargs;" \ 712 "tftp $loadaddr $bootfile;" \ 713 "tftp $fdtaddr $fdtfile;" \ 714 "bootm $loadaddr - $fdtaddr" 715 716 #define CONFIG_RAMBOOTCOMMAND \ 717 "setenv bootargs root=/dev/ram rw " \ 718 "console=$consoledev,$baudrate $othbootargs;" \ 719 "tftp $ramdiskaddr $ramdiskfile;" \ 720 "tftp $loadaddr $bootfile;" \ 721 "tftp $fdtaddr $fdtfile;" \ 722 "bootm $loadaddr $ramdiskaddr $fdtaddr" 723 724 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 725 726 #include <asm/fsl_secure_boot.h> 727 728 #endif /* __CONFIG_H */ 729