1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #endif 28 29 /* High Level Configuration Options */ 30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 31 #define CONFIG_MP /* support multiple processors */ 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 38 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 39 #define CONFIG_PCIE1 /* PCIE controller 1 */ 40 #define CONFIG_PCIE2 /* PCIE controller 2 */ 41 #define CONFIG_PCIE3 /* PCIE controller 3 */ 42 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 43 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 44 45 #define CONFIG_SYS_SRIO 46 #define CONFIG_SRIO1 /* SRIO port 1 */ 47 #define CONFIG_SRIO2 /* SRIO port 2 */ 48 #define CONFIG_SRIO_PCIE_BOOT_MASTER 49 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 50 51 #define CONFIG_ENV_OVERWRITE 52 53 #ifndef CONFIG_MTD_NOR_FLASH 54 #else 55 #define CONFIG_FLASH_CFI_DRIVER 56 #define CONFIG_SYS_FLASH_CFI 57 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 58 #endif 59 60 #if defined(CONFIG_SPIFLASH) 61 #define CONFIG_SYS_EXTRA_ENV_RELOC 62 #define CONFIG_ENV_SPI_BUS 0 63 #define CONFIG_ENV_SPI_CS 0 64 #define CONFIG_ENV_SPI_MAX_HZ 10000000 65 #define CONFIG_ENV_SPI_MODE 0 66 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 67 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 68 #define CONFIG_ENV_SECT_SIZE 0x10000 69 #elif defined(CONFIG_SDCARD) 70 #define CONFIG_SYS_EXTRA_ENV_RELOC 71 #define CONFIG_FSL_FIXED_MMC_LOCATION 72 #define CONFIG_SYS_MMC_ENV_DEV 0 73 #define CONFIG_ENV_SIZE 0x2000 74 #define CONFIG_ENV_OFFSET (512 * 1658) 75 #elif defined(CONFIG_NAND) 76 #define CONFIG_SYS_EXTRA_ENV_RELOC 77 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 78 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 79 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 80 #define CONFIG_ENV_ADDR 0xffe20000 81 #define CONFIG_ENV_SIZE 0x2000 82 #elif defined(CONFIG_ENV_IS_NOWHERE) 83 #define CONFIG_ENV_SIZE 0x2000 84 #else 85 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 86 - CONFIG_ENV_SECT_SIZE) 87 #define CONFIG_ENV_SIZE 0x2000 88 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 89 #endif 90 91 #ifndef __ASSEMBLY__ 92 unsigned long get_board_sys_clk(unsigned long dummy); 93 #endif 94 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 95 96 /* 97 * These can be toggled for performance analysis, otherwise use default. 98 */ 99 #define CONFIG_SYS_CACHE_STASHING 100 #define CONFIG_BACKSIDE_L2_CACHE 101 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 102 #define CONFIG_BTB /* toggle branch predition */ 103 104 #define CONFIG_ENABLE_36BIT_PHYS 105 106 #ifdef CONFIG_PHYS_64BIT 107 #define CONFIG_ADDR_MAP 108 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 109 #endif 110 111 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 113 #define CONFIG_SYS_MEMTEST_END 0x00400000 114 #define CONFIG_SYS_ALT_MEMTEST 115 116 /* 117 * Config the L3 Cache as L3 SRAM 118 */ 119 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 122 CONFIG_RAMBOOT_TEXT_BASE) 123 #else 124 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 125 #endif 126 #define CONFIG_SYS_L3_SIZE (1024 << 10) 127 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 128 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SYS_DCSRBAR 0xf0000000 131 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 132 #endif 133 134 /* EEPROM */ 135 #define CONFIG_ID_EEPROM 136 #define CONFIG_SYS_I2C_EEPROM_NXID 137 #define CONFIG_SYS_EEPROM_BUS_NUM 0 138 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 139 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 140 141 /* 142 * DDR Setup 143 */ 144 #define CONFIG_VERY_BIG_RAM 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 150 151 #define CONFIG_DDR_SPD 152 153 #define CONFIG_SYS_SPD_BUS_NUM 0 154 #define SPD_EEPROM_ADDRESS 0x52 155 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 156 157 /* 158 * Local Bus Definitions 159 */ 160 161 /* Set the local bus clock 1/8 of platform clock */ 162 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 163 164 /* 165 * This board doesn't have a promjet connector. 166 * However, it uses commone corenet board LAW and TLB. 167 * It is necessary to use the same start address with proper offset. 168 */ 169 #define CONFIG_SYS_FLASH_BASE 0xe0000000 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 172 #else 173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 174 #endif 175 176 #define CONFIG_SYS_FLASH_BR_PRELIM \ 177 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 178 BR_PS_16 | BR_V) 179 #define CONFIG_SYS_FLASH_OR_PRELIM \ 180 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 181 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 182 183 #define CONFIG_FSL_CPLD 184 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 185 #ifdef CONFIG_PHYS_64BIT 186 #define CPLD_BASE_PHYS 0xfffdf0000ull 187 #else 188 #define CPLD_BASE_PHYS CPLD_BASE 189 #endif 190 191 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 192 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 193 194 #define PIXIS_LBMAP_SWITCH 7 195 #define PIXIS_LBMAP_MASK 0xf0 196 #define PIXIS_LBMAP_SHIFT 4 197 #define PIXIS_LBMAP_ALTBANK 0x40 198 199 #define CONFIG_SYS_FLASH_QUIET_TEST 200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 201 202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 206 207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 208 209 #if defined(CONFIG_RAMBOOT_PBL) 210 #define CONFIG_SYS_RAMBOOT 211 #endif 212 213 #define CONFIG_NAND_FSL_ELBC 214 /* Nand Flash */ 215 #ifdef CONFIG_NAND_FSL_ELBC 216 #define CONFIG_SYS_NAND_BASE 0xffa00000 217 #ifdef CONFIG_PHYS_64BIT 218 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 219 #else 220 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 221 #endif 222 223 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 224 #define CONFIG_SYS_MAX_NAND_DEVICE 1 225 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 226 227 /* NAND flash config */ 228 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 229 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 230 | BR_PS_8 /* Port Size = 8 bit */ \ 231 | BR_MS_FCM /* MSEL = FCM */ \ 232 | BR_V) /* valid */ 233 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 234 | OR_FCM_PGS /* Large Page*/ \ 235 | OR_FCM_CSCT \ 236 | OR_FCM_CST \ 237 | OR_FCM_CHT \ 238 | OR_FCM_SCY_1 \ 239 | OR_FCM_TRLX \ 240 | OR_FCM_EHTR) 241 242 #ifdef CONFIG_NAND 243 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 244 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 245 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 246 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 247 #else 248 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 249 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 250 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 251 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 252 #endif 253 #else 254 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 255 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 256 #endif /* CONFIG_NAND_FSL_ELBC */ 257 258 #define CONFIG_SYS_FLASH_EMPTY_INFO 259 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 260 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 261 262 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 263 #define CONFIG_MISC_INIT_R 264 265 #define CONFIG_HWCONFIG 266 267 /* define to use L1 as initial stack */ 268 #define CONFIG_L1_INIT_RAM 269 #define CONFIG_SYS_INIT_RAM_LOCK 270 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 271 #ifdef CONFIG_PHYS_64BIT 272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 273 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 274 /* The assembler doesn't like typecast */ 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 276 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 277 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 278 #else 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 282 #endif 283 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 284 285 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 286 GENERATED_GBL_DATA_SIZE) 287 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 288 289 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 290 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 291 292 /* Serial Port - controlled on board with jumper J8 293 * open - index 2 294 * shorted - index 1 295 */ 296 #define CONFIG_SYS_NS16550_SERIAL 297 #define CONFIG_SYS_NS16550_REG_SIZE 1 298 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 299 300 #define CONFIG_SYS_BAUDRATE_TABLE \ 301 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 302 303 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 304 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 305 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 306 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 307 308 /* I2C */ 309 #define CONFIG_SYS_I2C 310 #define CONFIG_SYS_I2C_FSL 311 #define CONFIG_SYS_FSL_I2C_SPEED 400000 312 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 313 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 314 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 315 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 316 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 317 318 /* 319 * RapidIO 320 */ 321 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 324 #else 325 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 326 #endif 327 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 328 329 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 330 #ifdef CONFIG_PHYS_64BIT 331 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 332 #else 333 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 334 #endif 335 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 336 337 /* 338 * for slave u-boot IMAGE instored in master memory space, 339 * PHYS must be aligned based on the SIZE 340 */ 341 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 342 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 343 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 344 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 345 /* 346 * for slave UCODE and ENV instored in master memory space, 347 * PHYS must be aligned based on the SIZE 348 */ 349 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 350 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 351 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 352 353 /* slave core release by master*/ 354 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 355 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 356 357 /* 358 * SRIO_PCIE_BOOT - SLAVE 359 */ 360 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 361 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 362 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 363 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 364 #endif 365 366 /* 367 * eSPI - Enhanced SPI 368 */ 369 #define CONFIG_SF_DEFAULT_SPEED 10000000 370 #define CONFIG_SF_DEFAULT_MODE 0 371 372 /* 373 * General PCI 374 * Memory space is mapped 1-1, but I/O space must start from 0. 375 */ 376 377 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 378 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 379 #ifdef CONFIG_PHYS_64BIT 380 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 381 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 382 #else 383 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 384 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 385 #endif 386 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 387 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 388 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 389 #ifdef CONFIG_PHYS_64BIT 390 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 391 #else 392 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 393 #endif 394 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 395 396 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 397 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 398 #ifdef CONFIG_PHYS_64BIT 399 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 400 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 401 #else 402 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 403 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 404 #endif 405 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 406 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 407 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 410 #else 411 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 412 #endif 413 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 414 415 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 416 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 419 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 420 #else 421 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 422 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 423 #endif 424 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 425 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 426 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 429 #else 430 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 431 #endif 432 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 433 434 /* Qman/Bman */ 435 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 436 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 439 #else 440 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 441 #endif 442 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 443 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 444 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 445 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 446 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 447 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 448 CONFIG_SYS_BMAN_CENA_SIZE) 449 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 450 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 451 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 452 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 455 #else 456 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 457 #endif 458 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 459 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 460 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 461 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 462 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 463 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 464 CONFIG_SYS_QMAN_CENA_SIZE) 465 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 466 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 467 468 #define CONFIG_SYS_DPAA_FMAN 469 #define CONFIG_SYS_DPAA_PME 470 /* Default address of microcode for the Linux Fman driver */ 471 #if defined(CONFIG_SPIFLASH) 472 /* 473 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 474 * env, so we got 0x110000. 475 */ 476 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 477 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 478 #elif defined(CONFIG_SDCARD) 479 /* 480 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 481 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 482 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 483 */ 484 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 485 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 486 #elif defined(CONFIG_NAND) 487 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 488 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 489 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 490 /* 491 * Slave has no ucode locally, it can fetch this from remote. When implementing 492 * in two corenet boards, slave's ucode could be stored in master's memory 493 * space, the address can be mapped from slave TLB->slave LAW-> 494 * slave SRIO or PCIE outbound window->master inbound window-> 495 * master LAW->the ucode address in master's memory space. 496 */ 497 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 498 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 499 #else 500 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 501 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 502 #endif 503 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 504 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 505 506 #ifdef CONFIG_SYS_DPAA_FMAN 507 #define CONFIG_FMAN_ENET 508 #define CONFIG_PHYLIB_10G 509 #define CONFIG_PHY_VITESSE 510 #define CONFIG_PHY_TERANETICS 511 #endif 512 513 #ifdef CONFIG_PCI 514 #define CONFIG_PCI_INDIRECT_BRIDGE 515 516 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 517 #endif /* CONFIG_PCI */ 518 519 /* SATA */ 520 #define CONFIG_FSL_SATA_V2 521 522 #ifdef CONFIG_FSL_SATA_V2 523 #define CONFIG_SYS_SATA_MAX_DEVICE 2 524 #define CONFIG_SATA1 525 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 526 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 527 #define CONFIG_SATA2 528 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 529 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 530 531 #define CONFIG_LBA48 532 #endif 533 534 #ifdef CONFIG_FMAN_ENET 535 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 536 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 537 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 538 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 539 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 540 541 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 542 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 543 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 544 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 545 546 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 547 548 #define CONFIG_SYS_TBIPA_VALUE 8 549 #define CONFIG_MII /* MII PHY management */ 550 #define CONFIG_ETHPRIME "FM1@DTSEC1" 551 #endif 552 553 /* 554 * Environment 555 */ 556 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 557 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 558 559 /* 560 * Command line configuration. 561 */ 562 563 /* 564 * USB 565 */ 566 #define CONFIG_HAS_FSL_DR_USB 567 #define CONFIG_HAS_FSL_MPH_USB 568 569 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 570 #define CONFIG_USB_EHCI_FSL 571 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 572 #endif 573 574 #ifdef CONFIG_MMC 575 #define CONFIG_FSL_ESDHC 576 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 577 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 578 #endif 579 580 /* 581 * Miscellaneous configurable options 582 */ 583 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 584 585 /* 586 * For booting Linux, the board info and command line data 587 * have to be in the first 64 MB of memory, since this is 588 * the maximum mapped by the Linux kernel during initialization. 589 */ 590 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 591 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 592 593 #ifdef CONFIG_CMD_KGDB 594 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 595 #endif 596 597 /* 598 * Environment Configuration 599 */ 600 #define CONFIG_ROOTPATH "/opt/nfsroot" 601 #define CONFIG_BOOTFILE "uImage" 602 #define CONFIG_UBOOTPATH u-boot.bin 603 604 /* default location for tftp and bootm */ 605 #define CONFIG_LOADADDR 1000000 606 607 #define __USB_PHY_TYPE utmi 608 609 #define CONFIG_EXTRA_ENV_SETTINGS \ 610 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 611 "bank_intlv=cs0_cs1\0" \ 612 "netdev=eth0\0" \ 613 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 614 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 615 "tftpflash=tftpboot $loadaddr $uboot && " \ 616 "protect off $ubootaddr +$filesize && " \ 617 "erase $ubootaddr +$filesize && " \ 618 "cp.b $loadaddr $ubootaddr $filesize && " \ 619 "protect on $ubootaddr +$filesize && " \ 620 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 621 "consoledev=ttyS0\0" \ 622 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 623 "usb_dr_mode=host\0" \ 624 "ramdiskaddr=2000000\0" \ 625 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 626 "fdtaddr=1e00000\0" \ 627 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 628 "bdev=sda3\0" 629 630 #define CONFIG_HDBOOT \ 631 "setenv bootargs root=/dev/$bdev rw " \ 632 "console=$consoledev,$baudrate $othbootargs;" \ 633 "tftp $loadaddr $bootfile;" \ 634 "tftp $fdtaddr $fdtfile;" \ 635 "bootm $loadaddr - $fdtaddr" 636 637 #define CONFIG_NFSBOOTCOMMAND \ 638 "setenv bootargs root=/dev/nfs rw " \ 639 "nfsroot=$serverip:$rootpath " \ 640 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 641 "console=$consoledev,$baudrate $othbootargs;" \ 642 "tftp $loadaddr $bootfile;" \ 643 "tftp $fdtaddr $fdtfile;" \ 644 "bootm $loadaddr - $fdtaddr" 645 646 #define CONFIG_RAMBOOTCOMMAND \ 647 "setenv bootargs root=/dev/ram rw " \ 648 "console=$consoledev,$baudrate $othbootargs;" \ 649 "tftp $ramdiskaddr $ramdiskfile;" \ 650 "tftp $loadaddr $bootfile;" \ 651 "tftp $fdtaddr $fdtfile;" \ 652 "bootm $loadaddr $ramdiskaddr $fdtaddr" 653 654 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 655 656 #include <asm/fsl_secure_boot.h> 657 658 #endif /* __CONFIG_H */ 659