1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P2041 RDB board configuration file 25 * Also supports P2040 RDB 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #define CONFIG_P2041RDB 31 #define CONFIG_PHYS_64BIT 32 #define CONFIG_PPC_P2041 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 37 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg 38 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg 39 #endif 40 41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 42 /* Set 1M boot space */ 43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 47 #define CONFIG_SYS_NO_FLASH 48 #endif 49 50 /* High Level Configuration Options */ 51 #define CONFIG_BOOKE 52 #define CONFIG_E500 /* BOOKE e500 family */ 53 #define CONFIG_E500MC /* BOOKE e500mc family */ 54 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 55 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 56 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 57 #define CONFIG_MP /* support multiple processors */ 58 59 #ifndef CONFIG_SYS_TEXT_BASE 60 #define CONFIG_SYS_TEXT_BASE 0xeff80000 61 #endif 62 63 #ifndef CONFIG_RESET_VECTOR_ADDRESS 64 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 65 #endif 66 67 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 68 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 69 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 70 #define CONFIG_PCI /* Enable PCI/PCIE */ 71 #define CONFIG_PCIE1 /* PCIE controler 1 */ 72 #define CONFIG_PCIE2 /* PCIE controler 2 */ 73 #define CONFIG_PCIE3 /* PCIE controler 3 */ 74 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 75 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 76 77 #define CONFIG_SYS_SRIO 78 #define CONFIG_SRIO1 /* SRIO port 1 */ 79 #define CONFIG_SRIO2 /* SRIO port 2 */ 80 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 81 82 #define CONFIG_FSL_LAW /* Use common FSL init code */ 83 84 #define CONFIG_ENV_OVERWRITE 85 86 #ifdef CONFIG_SYS_NO_FLASH 87 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 88 #define CONFIG_ENV_IS_NOWHERE 89 #endif 90 #else 91 #define CONFIG_FLASH_CFI_DRIVER 92 #define CONFIG_SYS_FLASH_CFI 93 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 94 #endif 95 96 #if defined(CONFIG_SPIFLASH) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_SPI_FLASH 99 #define CONFIG_ENV_SPI_BUS 0 100 #define CONFIG_ENV_SPI_CS 0 101 #define CONFIG_ENV_SPI_MAX_HZ 10000000 102 #define CONFIG_ENV_SPI_MODE 0 103 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 104 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 105 #define CONFIG_ENV_SECT_SIZE 0x10000 106 #elif defined(CONFIG_SDCARD) 107 #define CONFIG_SYS_EXTRA_ENV_RELOC 108 #define CONFIG_ENV_IS_IN_MMC 109 #define CONFIG_FSL_FIXED_MMC_LOCATION 110 #define CONFIG_SYS_MMC_ENV_DEV 0 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_OFFSET (512 * 1097) 113 #elif defined(CONFIG_NAND) 114 #define CONFIG_SYS_EXTRA_ENV_RELOC 115 #define CONFIG_ENV_IS_IN_NAND 116 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 117 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 118 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 119 #define CONFIG_ENV_IS_IN_REMOTE 120 #define CONFIG_ENV_ADDR 0xffe20000 121 #define CONFIG_ENV_SIZE 0x2000 122 #elif defined(CONFIG_ENV_IS_NOWHERE) 123 #define CONFIG_ENV_SIZE 0x2000 124 #else 125 #define CONFIG_ENV_IS_IN_FLASH 126 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 127 - CONFIG_ENV_SECT_SIZE) 128 #define CONFIG_ENV_SIZE 0x2000 129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 130 #endif 131 132 #ifndef __ASSEMBLY__ 133 unsigned long get_board_sys_clk(unsigned long dummy); 134 #endif 135 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 136 137 /* 138 * These can be toggled for performance analysis, otherwise use default. 139 */ 140 #define CONFIG_SYS_CACHE_STASHING 141 #define CONFIG_BACKSIDE_L2_CACHE 142 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 143 #define CONFIG_BTB /* toggle branch predition */ 144 145 #define CONFIG_ENABLE_36BIT_PHYS 146 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_ADDR_MAP 149 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 150 #endif 151 152 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 153 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 154 #define CONFIG_SYS_MEMTEST_END 0x00400000 155 #define CONFIG_SYS_ALT_MEMTEST 156 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 157 158 /* 159 * Config the L3 Cache as L3 SRAM 160 */ 161 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 162 #ifdef CONFIG_PHYS_64BIT 163 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 164 CONFIG_RAMBOOT_TEXT_BASE) 165 #else 166 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 167 #endif 168 #define CONFIG_SYS_L3_SIZE (1024 << 10) 169 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 170 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_SYS_DCSRBAR 0xf0000000 173 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 174 #endif 175 176 /* EEPROM */ 177 #define CONFIG_ID_EEPROM 178 #define CONFIG_SYS_I2C_EEPROM_NXID 179 #define CONFIG_SYS_EEPROM_BUS_NUM 0 180 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 182 183 /* 184 * DDR Setup 185 */ 186 #define CONFIG_VERY_BIG_RAM 187 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 189 190 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 191 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 192 193 #define CONFIG_DDR_SPD 194 #define CONFIG_FSL_DDR3 195 196 #define CONFIG_SYS_SPD_BUS_NUM 0 197 #define SPD_EEPROM_ADDRESS 0x52 198 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 199 200 /* 201 * Local Bus Definitions 202 */ 203 204 /* Set the local bus clock 1/8 of platform clock */ 205 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 206 207 /* 208 * This board doesn't have a promjet connector. 209 * However, it uses commone corenet board LAW and TLB. 210 * It is necessary to use the same start address with proper offset. 211 */ 212 #define CONFIG_SYS_FLASH_BASE 0xe0000000 213 #ifdef CONFIG_PHYS_64BIT 214 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 215 #else 216 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 217 #endif 218 219 #define CONFIG_SYS_FLASH_BR_PRELIM \ 220 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 221 BR_PS_16 | BR_V) 222 #define CONFIG_SYS_FLASH_OR_PRELIM \ 223 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 224 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 225 226 #define CONFIG_FSL_CPLD 227 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 228 #ifdef CONFIG_PHYS_64BIT 229 #define CPLD_BASE_PHYS 0xfffdf0000ull 230 #else 231 #define CPLD_BASE_PHYS CPLD_BASE 232 #endif 233 234 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 235 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 236 237 #define PIXIS_LBMAP_SWITCH 7 238 #define PIXIS_LBMAP_MASK 0xf0 239 #define PIXIS_LBMAP_SHIFT 4 240 #define PIXIS_LBMAP_ALTBANK 0x40 241 242 #define CONFIG_SYS_FLASH_QUIET_TEST 243 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 244 245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 246 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 247 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 248 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 249 250 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 251 252 #if defined(CONFIG_RAMBOOT_PBL) 253 #define CONFIG_SYS_RAMBOOT 254 #endif 255 256 #define CONFIG_NAND_FSL_ELBC 257 /* Nand Flash */ 258 #ifdef CONFIG_NAND_FSL_ELBC 259 #define CONFIG_SYS_NAND_BASE 0xffa00000 260 #ifdef CONFIG_PHYS_64BIT 261 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 262 #else 263 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 264 #endif 265 266 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 267 #define CONFIG_SYS_MAX_NAND_DEVICE 1 268 #define CONFIG_MTD_NAND_VERIFY_WRITE 269 #define CONFIG_CMD_NAND 270 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 271 272 /* NAND flash config */ 273 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 274 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 275 | BR_PS_8 /* Port Size = 8 bit */ \ 276 | BR_MS_FCM /* MSEL = FCM */ \ 277 | BR_V) /* valid */ 278 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 279 | OR_FCM_PGS /* Large Page*/ \ 280 | OR_FCM_CSCT \ 281 | OR_FCM_CST \ 282 | OR_FCM_CHT \ 283 | OR_FCM_SCY_1 \ 284 | OR_FCM_TRLX \ 285 | OR_FCM_EHTR) 286 287 #ifdef CONFIG_NAND 288 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 289 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 290 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 291 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 292 #else 293 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 294 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 295 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 296 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 297 #endif 298 #else 299 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 300 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 301 #endif /* CONFIG_NAND_FSL_ELBC */ 302 303 #define CONFIG_SYS_FLASH_EMPTY_INFO 304 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 305 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 306 307 #define CONFIG_BOARD_EARLY_INIT_F 308 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 309 #define CONFIG_MISC_INIT_R 310 311 #define CONFIG_HWCONFIG 312 313 /* define to use L1 as initial stack */ 314 #define CONFIG_L1_INIT_RAM 315 #define CONFIG_SYS_INIT_RAM_LOCK 316 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 317 #ifdef CONFIG_PHYS_64BIT 318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 320 /* The assembler doesn't like typecast */ 321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 322 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 323 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 324 #else 325 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 326 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 328 #endif 329 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 330 331 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 332 GENERATED_GBL_DATA_SIZE) 333 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 334 335 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 336 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 337 338 /* Serial Port - controlled on board with jumper J8 339 * open - index 2 340 * shorted - index 1 341 */ 342 #define CONFIG_CONS_INDEX 1 343 #define CONFIG_SYS_NS16550 344 #define CONFIG_SYS_NS16550_SERIAL 345 #define CONFIG_SYS_NS16550_REG_SIZE 1 346 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 347 348 #define CONFIG_SYS_BAUDRATE_TABLE \ 349 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 350 351 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 352 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 353 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 354 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 355 356 /* Use the HUSH parser */ 357 #define CONFIG_SYS_HUSH_PARSER 358 359 /* pass open firmware flat tree */ 360 #define CONFIG_OF_LIBFDT 361 #define CONFIG_OF_BOARD_SETUP 362 #define CONFIG_OF_STDOUT_VIA_ALIAS 363 364 /* new uImage format support */ 365 #define CONFIG_FIT 366 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 367 368 /* I2C */ 369 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 370 #define CONFIG_HARD_I2C /* I2C with hardware support */ 371 #define CONFIG_I2C_MULTI_BUS 372 #define CONFIG_I2C_CMD_TREE 373 #define CONFIG_SYS_I2C_SPEED 400000 374 #define CONFIG_SYS_I2C_SLAVE 0x7F 375 #define CONFIG_SYS_I2C_OFFSET 0x118000 376 #define CONFIG_SYS_I2C2_OFFSET 0x118100 377 378 /* 379 * RapidIO 380 */ 381 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 382 #ifdef CONFIG_PHYS_64BIT 383 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 384 #else 385 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 386 #endif 387 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 388 389 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 390 #ifdef CONFIG_PHYS_64BIT 391 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 392 #else 393 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 394 #endif 395 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 396 397 /* 398 * for slave u-boot IMAGE instored in master memory space, 399 * PHYS must be aligned based on the SIZE 400 */ 401 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 402 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 403 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 404 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 405 /* 406 * for slave UCODE and ENV instored in master memory space, 407 * PHYS must be aligned based on the SIZE 408 */ 409 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 410 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 411 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 412 413 /* slave core release by master*/ 414 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 415 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 416 417 /* 418 * SRIO_PCIE_BOOT - SLAVE 419 */ 420 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 421 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 422 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 423 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 424 #endif 425 426 /* 427 * eSPI - Enhanced SPI 428 */ 429 #define CONFIG_FSL_ESPI 430 #define CONFIG_SPI_FLASH 431 #define CONFIG_SPI_FLASH_SPANSION 432 #define CONFIG_CMD_SF 433 #define CONFIG_SF_DEFAULT_SPEED 10000000 434 #define CONFIG_SF_DEFAULT_MODE 0 435 436 /* 437 * General PCI 438 * Memory space is mapped 1-1, but I/O space must start from 0. 439 */ 440 441 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 442 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 445 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 446 #else 447 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 448 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 449 #endif 450 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 451 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 452 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 455 #else 456 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 457 #endif 458 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 459 460 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 461 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 464 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 465 #else 466 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 467 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 468 #endif 469 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 470 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 471 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 474 #else 475 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 476 #endif 477 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 478 479 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 480 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 481 #ifdef CONFIG_PHYS_64BIT 482 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 483 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 484 #else 485 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 486 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 487 #endif 488 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 489 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 490 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 491 #ifdef CONFIG_PHYS_64BIT 492 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 493 #else 494 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 495 #endif 496 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 497 498 /* Qman/Bman */ 499 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 500 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 501 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 502 #ifdef CONFIG_PHYS_64BIT 503 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 504 #else 505 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 506 #endif 507 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 508 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 509 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 510 #ifdef CONFIG_PHYS_64BIT 511 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 512 #else 513 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 514 #endif 515 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 516 517 #define CONFIG_SYS_DPAA_FMAN 518 #define CONFIG_SYS_DPAA_PME 519 /* Default address of microcode for the Linux Fman driver */ 520 #if defined(CONFIG_SPIFLASH) 521 /* 522 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 523 * env, so we got 0x110000. 524 */ 525 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 526 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 527 #elif defined(CONFIG_SDCARD) 528 /* 529 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 530 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 531 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 532 */ 533 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 534 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 535 #elif defined(CONFIG_NAND) 536 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 537 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 538 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 539 /* 540 * Slave has no ucode locally, it can fetch this from remote. When implementing 541 * in two corenet boards, slave's ucode could be stored in master's memory 542 * space, the address can be mapped from slave TLB->slave LAW-> 543 * slave SRIO or PCIE outbound window->master inbound window-> 544 * master LAW->the ucode address in master's memory space. 545 */ 546 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 547 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 548 #else 549 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 550 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 551 #endif 552 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 553 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 554 555 #ifdef CONFIG_SYS_DPAA_FMAN 556 #define CONFIG_FMAN_ENET 557 #define CONFIG_PHYLIB_10G 558 #define CONFIG_PHY_VITESSE 559 #define CONFIG_PHY_TERANETICS 560 #endif 561 562 #ifdef CONFIG_PCI 563 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 564 #define CONFIG_E1000 565 566 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 567 #define CONFIG_DOS_PARTITION 568 #endif /* CONFIG_PCI */ 569 570 /* SATA */ 571 #define CONFIG_FSL_SATA_V2 572 573 #ifdef CONFIG_FSL_SATA_V2 574 #define CONFIG_FSL_SATA 575 #define CONFIG_LIBATA 576 577 #define CONFIG_SYS_SATA_MAX_DEVICE 2 578 #define CONFIG_SATA1 579 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 580 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 581 #define CONFIG_SATA2 582 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 583 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 584 585 #define CONFIG_LBA48 586 #define CONFIG_CMD_SATA 587 #define CONFIG_DOS_PARTITION 588 #define CONFIG_CMD_EXT2 589 #endif 590 591 #ifdef CONFIG_FMAN_ENET 592 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 593 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 594 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 595 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 596 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 597 598 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 599 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 600 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 601 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 602 603 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 604 605 #define CONFIG_SYS_TBIPA_VALUE 8 606 #define CONFIG_MII /* MII PHY management */ 607 #define CONFIG_ETHPRIME "FM1@DTSEC1" 608 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 609 #endif 610 611 /* 612 * Environment 613 */ 614 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 615 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 616 617 /* 618 * Command line configuration. 619 */ 620 #include <config_cmd_default.h> 621 622 #define CONFIG_CMD_DHCP 623 #define CONFIG_CMD_ELF 624 #define CONFIG_CMD_ERRATA 625 #define CONFIG_CMD_GREPENV 626 #define CONFIG_CMD_IRQ 627 #define CONFIG_CMD_I2C 628 #define CONFIG_CMD_MII 629 #define CONFIG_CMD_PING 630 #define CONFIG_CMD_SETEXPR 631 632 #ifdef CONFIG_PCI 633 #define CONFIG_CMD_PCI 634 #define CONFIG_CMD_NET 635 #endif 636 637 /* 638 * USB 639 */ 640 #define CONFIG_HAS_FSL_DR_USB 641 #define CONFIG_HAS_FSL_MPH_USB 642 643 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 644 #define CONFIG_CMD_USB 645 #define CONFIG_USB_STORAGE 646 #define CONFIG_USB_EHCI 647 #define CONFIG_USB_EHCI_FSL 648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 649 #endif 650 651 #define CONFIG_CMD_EXT2 652 653 #define CONFIG_MMC 654 655 #ifdef CONFIG_MMC 656 #define CONFIG_FSL_ESDHC 657 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 658 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 659 #define CONFIG_CMD_MMC 660 #define CONFIG_GENERIC_MMC 661 #define CONFIG_CMD_EXT2 662 #define CONFIG_CMD_FAT 663 #define CONFIG_DOS_PARTITION 664 #endif 665 666 /* 667 * Miscellaneous configurable options 668 */ 669 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 670 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 671 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 672 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 673 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 674 #ifdef CONFIG_CMD_KGDB 675 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 676 #else 677 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 678 #endif 679 /* Print Buffer Size */ 680 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 681 sizeof(CONFIG_SYS_PROMPT)+16) 682 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 683 /* Boot Argument Buffer Size */ 684 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 685 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ 686 687 /* 688 * For booting Linux, the board info and command line data 689 * have to be in the first 64 MB of memory, since this is 690 * the maximum mapped by the Linux kernel during initialization. 691 */ 692 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 693 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 694 695 #ifdef CONFIG_CMD_KGDB 696 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 697 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 698 #endif 699 700 /* 701 * Environment Configuration 702 */ 703 #define CONFIG_ROOTPATH "/opt/nfsroot" 704 #define CONFIG_BOOTFILE "uImage" 705 #define CONFIG_UBOOTPATH u-boot.bin 706 707 /* default location for tftp and bootm */ 708 #define CONFIG_LOADADDR 1000000 709 710 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 711 712 #define CONFIG_BAUDRATE 115200 713 714 #define __USB_PHY_TYPE utmi 715 716 #define CONFIG_EXTRA_ENV_SETTINGS \ 717 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 718 "bank_intlv=cs0_cs1\0" \ 719 "netdev=eth0\0" \ 720 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 721 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 722 "tftpflash=tftpboot $loadaddr $uboot && " \ 723 "protect off $ubootaddr +$filesize && " \ 724 "erase $ubootaddr +$filesize && " \ 725 "cp.b $loadaddr $ubootaddr $filesize && " \ 726 "protect on $ubootaddr +$filesize && " \ 727 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 728 "consoledev=ttyS0\0" \ 729 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 730 "usb_dr_mode=host\0" \ 731 "ramdiskaddr=2000000\0" \ 732 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 733 "fdtaddr=c00000\0" \ 734 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 735 "bdev=sda3\0" \ 736 "c=ffe\0" 737 738 #define CONFIG_HDBOOT \ 739 "setenv bootargs root=/dev/$bdev rw " \ 740 "console=$consoledev,$baudrate $othbootargs;" \ 741 "tftp $loadaddr $bootfile;" \ 742 "tftp $fdtaddr $fdtfile;" \ 743 "bootm $loadaddr - $fdtaddr" 744 745 #define CONFIG_NFSBOOTCOMMAND \ 746 "setenv bootargs root=/dev/nfs rw " \ 747 "nfsroot=$serverip:$rootpath " \ 748 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 749 "console=$consoledev,$baudrate $othbootargs;" \ 750 "tftp $loadaddr $bootfile;" \ 751 "tftp $fdtaddr $fdtfile;" \ 752 "bootm $loadaddr - $fdtaddr" 753 754 #define CONFIG_RAMBOOTCOMMAND \ 755 "setenv bootargs root=/dev/ram rw " \ 756 "console=$consoledev,$baudrate $othbootargs;" \ 757 "tftp $ramdiskaddr $ramdiskfile;" \ 758 "tftp $loadaddr $bootfile;" \ 759 "tftp $fdtaddr $fdtfile;" \ 760 "bootm $loadaddr $ramdiskaddr $fdtaddr" 761 762 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 763 764 #ifdef CONFIG_SECURE_BOOT 765 #include <asm/fsl_secure_boot.h> 766 #endif 767 768 #endif /* __CONFIG_H */ 769