xref: /openbmc/u-boot/include/configs/P2041RDB.h (revision 63e22517)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
4  */
5 
6 /*
7  * P2041 RDB board configuration file
8  * Also supports P2040 RDB
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
15 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
16 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
17 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
18 #endif
19 
20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
21 /* Set 1M boot space */
22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
24 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #endif
27 
28 /* High Level Configuration Options */
29 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
30 #define CONFIG_MP			/* support multiple processors */
31 
32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
33 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
34 #endif
35 
36 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
37 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
38 #define CONFIG_PCIE1			/* PCIE controller 1 */
39 #define CONFIG_PCIE2			/* PCIE controller 2 */
40 #define CONFIG_PCIE3			/* PCIE controller 3 */
41 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
42 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
43 
44 #define CONFIG_SYS_SRIO
45 #define CONFIG_SRIO1			/* SRIO port 1 */
46 #define CONFIG_SRIO2			/* SRIO port 2 */
47 #define CONFIG_SRIO_PCIE_BOOT_MASTER
48 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
49 
50 #define CONFIG_ENV_OVERWRITE
51 
52 #ifndef CONFIG_MTD_NOR_FLASH
53 #else
54 #define CONFIG_FLASH_CFI_DRIVER
55 #define CONFIG_SYS_FLASH_CFI
56 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
57 #endif
58 
59 #if defined(CONFIG_SPIFLASH)
60 	#define CONFIG_SYS_EXTRA_ENV_RELOC
61 	#define CONFIG_ENV_SPI_BUS              0
62 	#define CONFIG_ENV_SPI_CS               0
63 	#define CONFIG_ENV_SPI_MAX_HZ           10000000
64 	#define CONFIG_ENV_SPI_MODE             0
65 	#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
66 	#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
67 	#define CONFIG_ENV_SECT_SIZE            0x10000
68 #elif defined(CONFIG_SDCARD)
69 	#define CONFIG_SYS_EXTRA_ENV_RELOC
70 	#define CONFIG_FSL_FIXED_MMC_LOCATION
71 	#define CONFIG_SYS_MMC_ENV_DEV          0
72 	#define CONFIG_ENV_SIZE			0x2000
73 	#define CONFIG_ENV_OFFSET		(512 * 1658)
74 #elif defined(CONFIG_NAND)
75 #define CONFIG_SYS_EXTRA_ENV_RELOC
76 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
77 #define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
78 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
79 #define CONFIG_ENV_ADDR		0xffe20000
80 #define CONFIG_ENV_SIZE		0x2000
81 #elif defined(CONFIG_ENV_IS_NOWHERE)
82 #define CONFIG_ENV_SIZE		0x2000
83 #else
84 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
85 			- CONFIG_ENV_SECT_SIZE)
86 	#define CONFIG_ENV_SIZE		0x2000
87 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
88 #endif
89 
90 #ifndef __ASSEMBLY__
91 unsigned long get_board_sys_clk(unsigned long dummy);
92 #endif
93 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
94 
95 /*
96  * These can be toggled for performance analysis, otherwise use default.
97  */
98 #define CONFIG_SYS_CACHE_STASHING
99 #define CONFIG_BACKSIDE_L2_CACHE
100 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
101 #define CONFIG_BTB			/* toggle branch predition */
102 
103 #define CONFIG_ENABLE_36BIT_PHYS
104 
105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_ADDR_MAP
107 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
108 #endif
109 
110 #define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
111 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
112 #define CONFIG_SYS_MEMTEST_END		0x00400000
113 
114 /*
115  *  Config the L3 Cache as L3 SRAM
116  */
117 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
118 #ifdef CONFIG_PHYS_64BIT
119 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
120 		CONFIG_RAMBOOT_TEXT_BASE)
121 #else
122 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
123 #endif
124 #define CONFIG_SYS_L3_SIZE		(1024 << 10)
125 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
126 
127 #ifdef CONFIG_PHYS_64BIT
128 #define CONFIG_SYS_DCSRBAR		0xf0000000
129 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
130 #endif
131 
132 /* EEPROM */
133 #define CONFIG_ID_EEPROM
134 #define CONFIG_SYS_I2C_EEPROM_NXID
135 #define CONFIG_SYS_EEPROM_BUS_NUM	0
136 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
138 
139 /*
140  * DDR Setup
141  */
142 #define CONFIG_VERY_BIG_RAM
143 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
144 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
145 
146 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
147 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
148 
149 #define CONFIG_DDR_SPD
150 
151 #define CONFIG_SYS_SPD_BUS_NUM	0
152 #define SPD_EEPROM_ADDRESS	0x52
153 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
154 
155 /*
156  * Local Bus Definitions
157  */
158 
159 /* Set the local bus clock 1/8 of platform clock */
160 #define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
161 
162 /*
163  * This board doesn't have a promjet connector.
164  * However, it uses commone corenet board LAW and TLB.
165  * It is necessary to use the same start address with proper offset.
166  */
167 #define CONFIG_SYS_FLASH_BASE		0xe0000000
168 #ifdef CONFIG_PHYS_64BIT
169 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
170 #else
171 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
172 #endif
173 
174 #define CONFIG_SYS_FLASH_BR_PRELIM \
175 		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
176 		BR_PS_16 | BR_V)
177 #define CONFIG_SYS_FLASH_OR_PRELIM \
178 		((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
179 		 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
180 
181 #define CONFIG_FSL_CPLD
182 #define CPLD_BASE		0xffdf0000	/* CPLD registers */
183 #ifdef CONFIG_PHYS_64BIT
184 #define CPLD_BASE_PHYS		0xfffdf0000ull
185 #else
186 #define CPLD_BASE_PHYS		CPLD_BASE
187 #endif
188 
189 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
190 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
191 
192 #define PIXIS_LBMAP_SWITCH	7
193 #define PIXIS_LBMAP_MASK	0xf0
194 #define PIXIS_LBMAP_SHIFT	4
195 #define PIXIS_LBMAP_ALTBANK	0x40
196 
197 #define CONFIG_SYS_FLASH_QUIET_TEST
198 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
199 
200 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
201 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
202 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Erase Timeout (ms) */
203 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Write Timeout (ms) */
204 
205 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
206 
207 #if defined(CONFIG_RAMBOOT_PBL)
208 #define CONFIG_SYS_RAMBOOT
209 #endif
210 
211 #define CONFIG_NAND_FSL_ELBC
212 /* Nand Flash */
213 #ifdef CONFIG_NAND_FSL_ELBC
214 #define CONFIG_SYS_NAND_BASE		0xffa00000
215 #ifdef CONFIG_PHYS_64BIT
216 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
217 #else
218 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
219 #endif
220 
221 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
222 #define CONFIG_SYS_MAX_NAND_DEVICE	1
223 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
224 
225 /* NAND flash config */
226 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
227 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
228 			       | BR_PS_8	       /* Port Size = 8 bit */ \
229 			       | BR_MS_FCM	       /* MSEL = FCM */ \
230 			       | BR_V)		       /* valid */
231 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
232 			       | OR_FCM_PGS	       /* Large Page*/ \
233 			       | OR_FCM_CSCT \
234 			       | OR_FCM_CST \
235 			       | OR_FCM_CHT \
236 			       | OR_FCM_SCY_1 \
237 			       | OR_FCM_TRLX \
238 			       | OR_FCM_EHTR)
239 
240 #ifdef CONFIG_NAND
241 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
242 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
243 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
244 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
245 #else
246 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
247 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
248 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
249 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
250 #endif
251 #else
252 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
253 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
254 #endif /* CONFIG_NAND_FSL_ELBC */
255 
256 #define CONFIG_SYS_FLASH_EMPTY_INFO
257 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
258 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
259 
260 #define CONFIG_MISC_INIT_R
261 
262 #define CONFIG_HWCONFIG
263 
264 /* define to use L1 as initial stack */
265 #define CONFIG_L1_INIT_RAM
266 #define CONFIG_SYS_INIT_RAM_LOCK
267 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
268 #ifdef CONFIG_PHYS_64BIT
269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
270 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
271 /* The assembler doesn't like typecast */
272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
273 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
274 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
275 #else
276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
279 #endif
280 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
281 
282 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
283 					GENERATED_GBL_DATA_SIZE)
284 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
285 
286 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
287 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
288 
289 /* Serial Port - controlled on board with jumper J8
290  * open - index 2
291  * shorted - index 1
292  */
293 #define CONFIG_SYS_NS16550_SERIAL
294 #define CONFIG_SYS_NS16550_REG_SIZE	1
295 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
296 
297 #define CONFIG_SYS_BAUDRATE_TABLE	\
298 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
299 
300 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
301 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
302 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
303 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
304 
305 /* I2C */
306 #define CONFIG_SYS_I2C
307 #define CONFIG_SYS_I2C_FSL
308 #define CONFIG_SYS_FSL_I2C_SPEED	400000
309 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
310 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
311 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
312 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
313 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
314 
315 /*
316  * RapidIO
317  */
318 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
319 #ifdef CONFIG_PHYS_64BIT
320 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
321 #else
322 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
323 #endif
324 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
325 
326 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
327 #ifdef CONFIG_PHYS_64BIT
328 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
329 #else
330 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
331 #endif
332 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
333 
334 /*
335  * for slave u-boot IMAGE instored in master memory space,
336  * PHYS must be aligned based on the SIZE
337  */
338 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
339 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
340 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
341 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
342 /*
343  * for slave UCODE and ENV instored in master memory space,
344  * PHYS must be aligned based on the SIZE
345  */
346 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
347 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
348 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
349 
350 /* slave core release by master*/
351 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
352 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
353 
354 /*
355  * SRIO_PCIE_BOOT - SLAVE
356  */
357 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
358 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
359 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
360 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
361 #endif
362 
363 /*
364  * eSPI - Enhanced SPI
365  */
366 #define CONFIG_SF_DEFAULT_SPEED         10000000
367 #define CONFIG_SF_DEFAULT_MODE          0
368 
369 /*
370  * General PCI
371  * Memory space is mapped 1-1, but I/O space must start from 0.
372  */
373 
374 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
375 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
376 #ifdef CONFIG_PHYS_64BIT
377 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
378 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
379 #else
380 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
381 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
382 #endif
383 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
384 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
385 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
386 #ifdef CONFIG_PHYS_64BIT
387 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
388 #else
389 #define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
390 #endif
391 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
392 
393 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
394 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
395 #ifdef CONFIG_PHYS_64BIT
396 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
397 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
398 #else
399 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
400 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
401 #endif
402 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
403 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
404 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
405 #ifdef CONFIG_PHYS_64BIT
406 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
407 #else
408 #define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
409 #endif
410 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
411 
412 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
413 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
414 #ifdef CONFIG_PHYS_64BIT
415 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
416 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
417 #else
418 #define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
419 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
420 #endif
421 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
422 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
423 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
424 #ifdef CONFIG_PHYS_64BIT
425 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
426 #else
427 #define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
428 #endif
429 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
430 
431 /* Qman/Bman */
432 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
433 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
434 #ifdef CONFIG_PHYS_64BIT
435 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
436 #else
437 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
438 #endif
439 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
440 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
441 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
442 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
443 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
444 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
445 					CONFIG_SYS_BMAN_CENA_SIZE)
446 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
447 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
448 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
449 #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
450 #ifdef CONFIG_PHYS_64BIT
451 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
452 #else
453 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
454 #endif
455 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
456 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
457 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
458 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
459 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
460 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
461 					CONFIG_SYS_QMAN_CENA_SIZE)
462 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
463 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
464 
465 #define CONFIG_SYS_DPAA_FMAN
466 #define CONFIG_SYS_DPAA_PME
467 /* Default address of microcode for the Linux Fman driver */
468 #if defined(CONFIG_SPIFLASH)
469 /*
470  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
471  * env, so we got 0x110000.
472  */
473 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
474 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
475 #elif defined(CONFIG_SDCARD)
476 /*
477  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
478  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
479  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
480  */
481 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
482 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
483 #elif defined(CONFIG_NAND)
484 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
485 #define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
486 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
487 /*
488  * Slave has no ucode locally, it can fetch this from remote. When implementing
489  * in two corenet boards, slave's ucode could be stored in master's memory
490  * space, the address can be mapped from slave TLB->slave LAW->
491  * slave SRIO or PCIE outbound window->master inbound window->
492  * master LAW->the ucode address in master's memory space.
493  */
494 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
495 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
496 #else
497 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
498 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
499 #endif
500 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
501 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
502 
503 #ifdef CONFIG_SYS_DPAA_FMAN
504 #define CONFIG_FMAN_ENET
505 #define CONFIG_PHYLIB_10G
506 #define CONFIG_PHY_VITESSE
507 #define CONFIG_PHY_TERANETICS
508 #endif
509 
510 #ifdef CONFIG_PCI
511 #define CONFIG_PCI_INDIRECT_BRIDGE
512 
513 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
514 #endif	/* CONFIG_PCI */
515 
516 /* SATA */
517 #define CONFIG_FSL_SATA_V2
518 
519 #ifdef CONFIG_FSL_SATA_V2
520 #define CONFIG_SYS_SATA_MAX_DEVICE	2
521 #define CONFIG_SATA1
522 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
523 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
524 #define CONFIG_SATA2
525 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
526 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
527 
528 #define CONFIG_LBA48
529 #endif
530 
531 #ifdef CONFIG_FMAN_ENET
532 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
533 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
534 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x4
535 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1
536 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x0
537 
538 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR	0x1c
539 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR	0x1d
540 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR	0x1e
541 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR	0x1f
542 
543 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	0
544 
545 #define CONFIG_SYS_TBIPA_VALUE	8
546 #define CONFIG_MII		/* MII PHY management */
547 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
548 #endif
549 
550 /*
551  * Environment
552  */
553 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
554 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
555 
556 /*
557  * Command line configuration.
558  */
559 
560 /*
561 * USB
562 */
563 #define CONFIG_HAS_FSL_DR_USB
564 #define CONFIG_HAS_FSL_MPH_USB
565 
566 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
567 #define CONFIG_USB_EHCI_FSL
568 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
569 #endif
570 
571 #ifdef CONFIG_MMC
572 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
573 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
574 #endif
575 
576 /*
577  * Miscellaneous configurable options
578  */
579 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
580 
581 /*
582  * For booting Linux, the board info and command line data
583  * have to be in the first 64 MB of memory, since this is
584  * the maximum mapped by the Linux kernel during initialization.
585  */
586 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
587 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
588 
589 #ifdef CONFIG_CMD_KGDB
590 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
591 #endif
592 
593 /*
594  * Environment Configuration
595  */
596 #define CONFIG_ROOTPATH		"/opt/nfsroot"
597 #define CONFIG_BOOTFILE		"uImage"
598 #define CONFIG_UBOOTPATH	u-boot.bin
599 
600 /* default location for tftp and bootm */
601 #define CONFIG_LOADADDR		1000000
602 
603 #define __USB_PHY_TYPE	utmi
604 
605 #define	CONFIG_EXTRA_ENV_SETTINGS				\
606 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
607 	"bank_intlv=cs0_cs1\0"					\
608 	"netdev=eth0\0"						\
609 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
610 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
611 	"tftpflash=tftpboot $loadaddr $uboot && "		\
612 	"protect off $ubootaddr +$filesize && "			\
613 	"erase $ubootaddr +$filesize && "			\
614 	"cp.b $loadaddr $ubootaddr $filesize && "		\
615 	"protect on $ubootaddr +$filesize && "			\
616 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
617 	"consoledev=ttyS0\0"					\
618 	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
619 	"usb_dr_mode=host\0"					\
620 	"ramdiskaddr=2000000\0"					\
621 	"ramdiskfile=p2041rdb/ramdisk.uboot\0"			\
622 	"fdtaddr=1e00000\0"					\
623 	"fdtfile=p2041rdb/p2041rdb.dtb\0"			\
624 	"bdev=sda3\0"
625 
626 #define CONFIG_HDBOOT					\
627 	"setenv bootargs root=/dev/$bdev rw "		\
628 	"console=$consoledev,$baudrate $othbootargs;"	\
629 	"tftp $loadaddr $bootfile;"			\
630 	"tftp $fdtaddr $fdtfile;"			\
631 	"bootm $loadaddr - $fdtaddr"
632 
633 #define CONFIG_NFSBOOTCOMMAND			\
634 	"setenv bootargs root=/dev/nfs rw "	\
635 	"nfsroot=$serverip:$rootpath "		\
636 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
637 	"console=$consoledev,$baudrate $othbootargs;"	\
638 	"tftp $loadaddr $bootfile;"		\
639 	"tftp $fdtaddr $fdtfile;"		\
640 	"bootm $loadaddr - $fdtaddr"
641 
642 #define CONFIG_RAMBOOTCOMMAND				\
643 	"setenv bootargs root=/dev/ram rw "		\
644 	"console=$consoledev,$baudrate $othbootargs;"	\
645 	"tftp $ramdiskaddr $ramdiskfile;"		\
646 	"tftp $loadaddr $bootfile;"			\
647 	"tftp $fdtaddr $fdtfile;"			\
648 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
649 
650 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
651 
652 #include <asm/fsl_secure_boot.h>
653 
654 #endif	/* __CONFIG_H */
655