1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_P2041RDB 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_PPC_P2041 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 21 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 22 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 23 #endif 24 25 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 26 /* Set 1M boot space */ 27 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 28 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 29 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 31 #define CONFIG_SYS_NO_FLASH 32 #endif 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 36 #define CONFIG_E500 /* BOOKE e500 family */ 37 #define CONFIG_E500MC /* BOOKE e500mc family */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 #ifndef CONFIG_SYS_TEXT_BASE 42 #define CONFIG_SYS_TEXT_BASE 0xeff40000 43 #endif 44 45 #ifndef CONFIG_RESET_VECTOR_ADDRESS 46 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 47 #endif 48 49 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 50 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 51 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 52 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 53 #define CONFIG_PCI /* Enable PCI/PCIE */ 54 #define CONFIG_PCIE1 /* PCIE controller 1 */ 55 #define CONFIG_PCIE2 /* PCIE controller 2 */ 56 #define CONFIG_PCIE3 /* PCIE controller 3 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #define CONFIG_SYS_SRIO 61 #define CONFIG_SRIO1 /* SRIO port 1 */ 62 #define CONFIG_SRIO2 /* SRIO port 2 */ 63 #define CONFIG_SRIO_PCIE_BOOT_MASTER 64 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 65 66 #define CONFIG_FSL_LAW /* Use common FSL init code */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #ifdef CONFIG_SYS_NO_FLASH 71 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 72 #define CONFIG_ENV_IS_NOWHERE 73 #endif 74 #else 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_CFI 77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 78 #endif 79 80 #if defined(CONFIG_SPIFLASH) 81 #define CONFIG_SYS_EXTRA_ENV_RELOC 82 #define CONFIG_ENV_IS_IN_SPI_FLASH 83 #define CONFIG_ENV_SPI_BUS 0 84 #define CONFIG_ENV_SPI_CS 0 85 #define CONFIG_ENV_SPI_MAX_HZ 10000000 86 #define CONFIG_ENV_SPI_MODE 0 87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 89 #define CONFIG_ENV_SECT_SIZE 0x10000 90 #elif defined(CONFIG_SDCARD) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_IS_IN_MMC 93 #define CONFIG_FSL_FIXED_MMC_LOCATION 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1658) 97 #elif defined(CONFIG_NAND) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_NAND 100 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 101 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 102 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 103 #define CONFIG_ENV_IS_IN_REMOTE 104 #define CONFIG_ENV_ADDR 0xffe20000 105 #define CONFIG_ENV_SIZE 0x2000 106 #elif defined(CONFIG_ENV_IS_NOWHERE) 107 #define CONFIG_ENV_SIZE 0x2000 108 #else 109 #define CONFIG_ENV_IS_IN_FLASH 110 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 111 - CONFIG_ENV_SECT_SIZE) 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 114 #endif 115 116 #ifndef __ASSEMBLY__ 117 unsigned long get_board_sys_clk(unsigned long dummy); 118 #endif 119 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 120 121 /* 122 * These can be toggled for performance analysis, otherwise use default. 123 */ 124 #define CONFIG_SYS_CACHE_STASHING 125 #define CONFIG_BACKSIDE_L2_CACHE 126 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 127 #define CONFIG_BTB /* toggle branch predition */ 128 129 #define CONFIG_ENABLE_36BIT_PHYS 130 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_ADDR_MAP 133 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 134 #endif 135 136 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_END 0x00400000 139 #define CONFIG_SYS_ALT_MEMTEST 140 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 141 142 /* 143 * Config the L3 Cache as L3 SRAM 144 */ 145 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 146 #ifdef CONFIG_PHYS_64BIT 147 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 148 CONFIG_RAMBOOT_TEXT_BASE) 149 #else 150 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 151 #endif 152 #define CONFIG_SYS_L3_SIZE (1024 << 10) 153 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 154 155 #ifdef CONFIG_PHYS_64BIT 156 #define CONFIG_SYS_DCSRBAR 0xf0000000 157 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 158 #endif 159 160 /* EEPROM */ 161 #define CONFIG_ID_EEPROM 162 #define CONFIG_SYS_I2C_EEPROM_NXID 163 #define CONFIG_SYS_EEPROM_BUS_NUM 0 164 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 166 167 /* 168 * DDR Setup 169 */ 170 #define CONFIG_VERY_BIG_RAM 171 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 172 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 173 174 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 175 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 176 177 #define CONFIG_DDR_SPD 178 #define CONFIG_SYS_FSL_DDR3 179 180 #define CONFIG_SYS_SPD_BUS_NUM 0 181 #define SPD_EEPROM_ADDRESS 0x52 182 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 183 184 /* 185 * Local Bus Definitions 186 */ 187 188 /* Set the local bus clock 1/8 of platform clock */ 189 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 190 191 /* 192 * This board doesn't have a promjet connector. 193 * However, it uses commone corenet board LAW and TLB. 194 * It is necessary to use the same start address with proper offset. 195 */ 196 #define CONFIG_SYS_FLASH_BASE 0xe0000000 197 #ifdef CONFIG_PHYS_64BIT 198 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 199 #else 200 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 201 #endif 202 203 #define CONFIG_SYS_FLASH_BR_PRELIM \ 204 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 205 BR_PS_16 | BR_V) 206 #define CONFIG_SYS_FLASH_OR_PRELIM \ 207 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 208 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 209 210 #define CONFIG_FSL_CPLD 211 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 212 #ifdef CONFIG_PHYS_64BIT 213 #define CPLD_BASE_PHYS 0xfffdf0000ull 214 #else 215 #define CPLD_BASE_PHYS CPLD_BASE 216 #endif 217 218 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 219 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 220 221 #define PIXIS_LBMAP_SWITCH 7 222 #define PIXIS_LBMAP_MASK 0xf0 223 #define PIXIS_LBMAP_SHIFT 4 224 #define PIXIS_LBMAP_ALTBANK 0x40 225 226 #define CONFIG_SYS_FLASH_QUIET_TEST 227 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 228 229 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 230 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 233 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 235 236 #if defined(CONFIG_RAMBOOT_PBL) 237 #define CONFIG_SYS_RAMBOOT 238 #endif 239 240 #define CONFIG_NAND_FSL_ELBC 241 /* Nand Flash */ 242 #ifdef CONFIG_NAND_FSL_ELBC 243 #define CONFIG_SYS_NAND_BASE 0xffa00000 244 #ifdef CONFIG_PHYS_64BIT 245 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 246 #else 247 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 248 #endif 249 250 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 251 #define CONFIG_SYS_MAX_NAND_DEVICE 1 252 #define CONFIG_CMD_NAND 253 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 254 255 /* NAND flash config */ 256 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 257 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 258 | BR_PS_8 /* Port Size = 8 bit */ \ 259 | BR_MS_FCM /* MSEL = FCM */ \ 260 | BR_V) /* valid */ 261 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 262 | OR_FCM_PGS /* Large Page*/ \ 263 | OR_FCM_CSCT \ 264 | OR_FCM_CST \ 265 | OR_FCM_CHT \ 266 | OR_FCM_SCY_1 \ 267 | OR_FCM_TRLX \ 268 | OR_FCM_EHTR) 269 270 #ifdef CONFIG_NAND 271 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 272 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 273 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 274 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 275 #else 276 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 277 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 278 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 279 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 280 #endif 281 #else 282 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 283 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 284 #endif /* CONFIG_NAND_FSL_ELBC */ 285 286 #define CONFIG_SYS_FLASH_EMPTY_INFO 287 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 288 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 289 290 #define CONFIG_BOARD_EARLY_INIT_F 291 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 292 #define CONFIG_MISC_INIT_R 293 294 #define CONFIG_HWCONFIG 295 296 /* define to use L1 as initial stack */ 297 #define CONFIG_L1_INIT_RAM 298 #define CONFIG_SYS_INIT_RAM_LOCK 299 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 300 #ifdef CONFIG_PHYS_64BIT 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 303 /* The assembler doesn't like typecast */ 304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 305 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 306 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 307 #else 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 311 #endif 312 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 313 314 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 315 GENERATED_GBL_DATA_SIZE) 316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 317 318 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 319 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 320 321 /* Serial Port - controlled on board with jumper J8 322 * open - index 2 323 * shorted - index 1 324 */ 325 #define CONFIG_CONS_INDEX 1 326 #define CONFIG_SYS_NS16550_SERIAL 327 #define CONFIG_SYS_NS16550_REG_SIZE 1 328 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 329 330 #define CONFIG_SYS_BAUDRATE_TABLE \ 331 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 332 333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 335 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 336 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 337 338 /* I2C */ 339 #define CONFIG_SYS_I2C 340 #define CONFIG_SYS_I2C_FSL 341 #define CONFIG_SYS_FSL_I2C_SPEED 400000 342 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 343 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 344 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 345 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 346 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 347 348 /* 349 * RapidIO 350 */ 351 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 352 #ifdef CONFIG_PHYS_64BIT 353 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 354 #else 355 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 356 #endif 357 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 358 359 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 360 #ifdef CONFIG_PHYS_64BIT 361 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 362 #else 363 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 364 #endif 365 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 366 367 /* 368 * for slave u-boot IMAGE instored in master memory space, 369 * PHYS must be aligned based on the SIZE 370 */ 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 375 /* 376 * for slave UCODE and ENV instored in master memory space, 377 * PHYS must be aligned based on the SIZE 378 */ 379 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 381 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 382 383 /* slave core release by master*/ 384 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 385 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 386 387 /* 388 * SRIO_PCIE_BOOT - SLAVE 389 */ 390 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 391 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 392 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 393 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 394 #endif 395 396 /* 397 * eSPI - Enhanced SPI 398 */ 399 #define CONFIG_SF_DEFAULT_SPEED 10000000 400 #define CONFIG_SF_DEFAULT_MODE 0 401 402 /* 403 * General PCI 404 * Memory space is mapped 1-1, but I/O space must start from 0. 405 */ 406 407 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 408 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 409 #ifdef CONFIG_PHYS_64BIT 410 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 411 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 412 #else 413 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 414 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 415 #endif 416 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 417 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 418 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 419 #ifdef CONFIG_PHYS_64BIT 420 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 421 #else 422 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 423 #endif 424 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 425 426 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 427 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 430 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 431 #else 432 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 433 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 434 #endif 435 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 436 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 437 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 440 #else 441 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 442 #endif 443 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 444 445 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 446 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 449 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 450 #else 451 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 452 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 453 #endif 454 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 455 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 456 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 457 #ifdef CONFIG_PHYS_64BIT 458 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 459 #else 460 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 461 #endif 462 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 463 464 /* Qman/Bman */ 465 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 466 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 467 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 470 #else 471 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 472 #endif 473 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 474 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 475 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 476 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 477 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 478 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 479 CONFIG_SYS_BMAN_CENA_SIZE) 480 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 481 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 482 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 483 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 484 #ifdef CONFIG_PHYS_64BIT 485 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 486 #else 487 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 488 #endif 489 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 490 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 491 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 492 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 493 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 494 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 495 CONFIG_SYS_QMAN_CENA_SIZE) 496 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 497 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 498 499 #define CONFIG_SYS_DPAA_FMAN 500 #define CONFIG_SYS_DPAA_PME 501 /* Default address of microcode for the Linux Fman driver */ 502 #if defined(CONFIG_SPIFLASH) 503 /* 504 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 505 * env, so we got 0x110000. 506 */ 507 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 508 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 509 #elif defined(CONFIG_SDCARD) 510 /* 511 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 512 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 513 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 514 */ 515 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 516 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 517 #elif defined(CONFIG_NAND) 518 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 519 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 520 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 521 /* 522 * Slave has no ucode locally, it can fetch this from remote. When implementing 523 * in two corenet boards, slave's ucode could be stored in master's memory 524 * space, the address can be mapped from slave TLB->slave LAW-> 525 * slave SRIO or PCIE outbound window->master inbound window-> 526 * master LAW->the ucode address in master's memory space. 527 */ 528 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 529 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 530 #else 531 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 532 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 533 #endif 534 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 535 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 536 537 #ifdef CONFIG_SYS_DPAA_FMAN 538 #define CONFIG_FMAN_ENET 539 #define CONFIG_PHYLIB_10G 540 #define CONFIG_PHY_VITESSE 541 #define CONFIG_PHY_TERANETICS 542 #endif 543 544 #ifdef CONFIG_PCI 545 #define CONFIG_PCI_INDIRECT_BRIDGE 546 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 547 548 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 549 #define CONFIG_DOS_PARTITION 550 #endif /* CONFIG_PCI */ 551 552 /* SATA */ 553 #define CONFIG_FSL_SATA_V2 554 555 #ifdef CONFIG_FSL_SATA_V2 556 #define CONFIG_FSL_SATA 557 #define CONFIG_LIBATA 558 559 #define CONFIG_SYS_SATA_MAX_DEVICE 2 560 #define CONFIG_SATA1 561 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 562 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 563 #define CONFIG_SATA2 564 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 565 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 566 567 #define CONFIG_LBA48 568 #define CONFIG_CMD_SATA 569 #define CONFIG_DOS_PARTITION 570 #endif 571 572 #ifdef CONFIG_FMAN_ENET 573 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 574 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 575 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 576 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 577 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 578 579 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 580 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 581 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 582 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 583 584 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 585 586 #define CONFIG_SYS_TBIPA_VALUE 8 587 #define CONFIG_MII /* MII PHY management */ 588 #define CONFIG_ETHPRIME "FM1@DTSEC1" 589 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 590 #endif 591 592 /* 593 * Environment 594 */ 595 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 596 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 597 598 /* 599 * Command line configuration. 600 */ 601 #define CONFIG_CMD_ERRATA 602 #define CONFIG_CMD_IRQ 603 604 #ifdef CONFIG_PCI 605 #define CONFIG_CMD_PCI 606 #endif 607 608 /* 609 * USB 610 */ 611 #define CONFIG_HAS_FSL_DR_USB 612 #define CONFIG_HAS_FSL_MPH_USB 613 614 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 615 #define CONFIG_USB_STORAGE 616 #define CONFIG_USB_EHCI 617 #define CONFIG_USB_EHCI_FSL 618 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 619 #endif 620 621 #define CONFIG_MMC 622 623 #ifdef CONFIG_MMC 624 #define CONFIG_FSL_ESDHC 625 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 626 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 627 #define CONFIG_GENERIC_MMC 628 #define CONFIG_DOS_PARTITION 629 #endif 630 631 /* Hash command with SHA acceleration supported in hardware */ 632 #ifdef CONFIG_FSL_CAAM 633 #define CONFIG_CMD_HASH 634 #define CONFIG_SHA_HW_ACCEL 635 #endif 636 637 /* 638 * Miscellaneous configurable options 639 */ 640 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 641 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 642 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 643 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 644 #ifdef CONFIG_CMD_KGDB 645 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 646 #else 647 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 648 #endif 649 /* Print Buffer Size */ 650 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 651 sizeof(CONFIG_SYS_PROMPT)+16) 652 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 653 /* Boot Argument Buffer Size */ 654 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 655 656 /* 657 * For booting Linux, the board info and command line data 658 * have to be in the first 64 MB of memory, since this is 659 * the maximum mapped by the Linux kernel during initialization. 660 */ 661 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 662 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 663 664 #ifdef CONFIG_CMD_KGDB 665 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 666 #endif 667 668 /* 669 * Environment Configuration 670 */ 671 #define CONFIG_ROOTPATH "/opt/nfsroot" 672 #define CONFIG_BOOTFILE "uImage" 673 #define CONFIG_UBOOTPATH u-boot.bin 674 675 /* default location for tftp and bootm */ 676 #define CONFIG_LOADADDR 1000000 677 678 679 #define CONFIG_BAUDRATE 115200 680 681 #define __USB_PHY_TYPE utmi 682 683 #define CONFIG_EXTRA_ENV_SETTINGS \ 684 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 685 "bank_intlv=cs0_cs1\0" \ 686 "netdev=eth0\0" \ 687 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 688 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 689 "tftpflash=tftpboot $loadaddr $uboot && " \ 690 "protect off $ubootaddr +$filesize && " \ 691 "erase $ubootaddr +$filesize && " \ 692 "cp.b $loadaddr $ubootaddr $filesize && " \ 693 "protect on $ubootaddr +$filesize && " \ 694 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 695 "consoledev=ttyS0\0" \ 696 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 697 "usb_dr_mode=host\0" \ 698 "ramdiskaddr=2000000\0" \ 699 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 700 "fdtaddr=1e00000\0" \ 701 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 702 "bdev=sda3\0" 703 704 #define CONFIG_HDBOOT \ 705 "setenv bootargs root=/dev/$bdev rw " \ 706 "console=$consoledev,$baudrate $othbootargs;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr - $fdtaddr" 710 711 #define CONFIG_NFSBOOTCOMMAND \ 712 "setenv bootargs root=/dev/nfs rw " \ 713 "nfsroot=$serverip:$rootpath " \ 714 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 715 "console=$consoledev,$baudrate $othbootargs;" \ 716 "tftp $loadaddr $bootfile;" \ 717 "tftp $fdtaddr $fdtfile;" \ 718 "bootm $loadaddr - $fdtaddr" 719 720 #define CONFIG_RAMBOOTCOMMAND \ 721 "setenv bootargs root=/dev/ram rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $ramdiskaddr $ramdiskfile;" \ 724 "tftp $loadaddr $bootfile;" \ 725 "tftp $fdtaddr $fdtfile;" \ 726 "bootm $loadaddr $ramdiskaddr $fdtaddr" 727 728 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 729 730 #include <asm/fsl_secure_boot.h> 731 732 #endif /* __CONFIG_H */ 733