1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P2041 RDB board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #define CONFIG_P2041RDB 31 #define CONFIG_PHYS_64BIT 32 #define CONFIG_PPC_P2041 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_BOOKE 41 #define CONFIG_E500 /* BOOKE e500 family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 45 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 46 #define CONFIG_MP /* support multiple processors */ 47 48 #ifndef CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_TEXT_BASE 0xeff80000 50 #endif 51 52 #ifndef CONFIG_RESET_VECTOR_ADDRESS 53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 54 #endif 55 56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 57 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 58 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 59 #define CONFIG_PCI /* Enable PCI/PCIE */ 60 #define CONFIG_PCIE1 /* PCIE controler 1 */ 61 #define CONFIG_PCIE2 /* PCIE controler 2 */ 62 #define CONFIG_PCIE3 /* PCIE controler 3 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_SYS_SRIO 67 #define CONFIG_SRIO1 /* SRIO port 1 */ 68 #define CONFIG_SRIO2 /* SRIO port 2 */ 69 70 #define CONFIG_FSL_LAW /* Use common FSL init code */ 71 72 #define CONFIG_ENV_OVERWRITE 73 74 #ifdef CONFIG_SYS_NO_FLASH 75 #define CONFIG_ENV_IS_NOWHERE 76 #else 77 #define CONFIG_FLASH_CFI_DRIVER 78 #define CONFIG_SYS_FLASH_CFI 79 #endif 80 81 #if defined(CONFIG_SPIFLASH) 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_ENV_IS_IN_SPI_FLASH 84 #define CONFIG_ENV_SPI_BUS 0 85 #define CONFIG_ENV_SPI_CS 0 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 87 #define CONFIG_ENV_SPI_MODE 0 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 90 #define CONFIG_ENV_SECT_SIZE 0x10000 91 #elif defined(CONFIG_SDCARD) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_SYS_MMC_ENV_DEV 0 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_OFFSET (512 * 1097) 97 #else 98 #define CONFIG_ENV_IS_IN_FLASH 99 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 100 - CONFIG_ENV_SECT_SIZE) 101 #define CONFIG_ENV_SIZE 0x2000 102 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 103 #endif 104 105 #define CONFIG_SYS_CLK_FREQ 66666666 106 107 /* 108 * These can be toggled for performance analysis, otherwise use default. 109 */ 110 #define CONFIG_SYS_CACHE_STASHING 111 #define CONFIG_BTB /* toggle branch predition */ 112 113 #define CONFIG_ENABLE_36BIT_PHYS 114 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_ADDR_MAP 117 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 118 #endif 119 120 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 121 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 122 #define CONFIG_SYS_MEMTEST_END 0x00400000 123 #define CONFIG_SYS_ALT_MEMTEST 124 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 125 126 /* 127 * Config the L3 Cache as L3 SRAM 128 */ 129 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 132 CONFIG_RAMBOOT_TEXT_BASE) 133 #else 134 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 135 #endif 136 #define CONFIG_SYS_L3_SIZE (1024 << 10) 137 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 138 139 /* 140 * Base addresses -- Note these are effective addresses where the 141 * actual resources get mapped (not physical addresses) 142 */ 143 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ 144 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull 147 #else 148 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 149 #endif 150 /* PQII uses CONFIG_SYS_IMMR */ 151 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 152 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_DCSRBAR 0xf0000000 155 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 156 #endif 157 158 /* EEPROM */ 159 #define CONFIG_ID_EEPROM 160 #define CONFIG_SYS_I2C_EEPROM_NXID 161 #define CONFIG_SYS_EEPROM_BUS_NUM 0 162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 164 165 /* 166 * DDR Setup 167 */ 168 #define CONFIG_VERY_BIG_RAM 169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 171 172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 173 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 174 175 #define CONFIG_DDR_SPD 176 #define CONFIG_FSL_DDR3 177 178 #define CONFIG_SYS_SPD_BUS_NUM 0 179 #define SPD_EEPROM_ADDRESS 0x52 180 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 181 182 /* 183 * Local Bus Definitions 184 */ 185 186 /* Set the local bus clock 1/8 of platform clock */ 187 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 188 189 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ 190 #ifdef CONFIG_PHYS_64BIT 191 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 192 #else 193 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 194 #endif 195 196 #define CONFIG_SYS_BR0_PRELIM \ 197 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 198 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 199 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 200 201 #define CONFIG_FSL_CPLD 202 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 203 #ifdef CONFIG_PHYS_64BIT 204 #define CPLD_BASE_PHYS 0xfffdf0000ull 205 #else 206 #define CPLD_BASE_PHYS CPLD_BASE 207 #endif 208 209 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 210 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 211 212 #define PIXIS_LBMAP_SWITCH 7 213 #define PIXIS_LBMAP_MASK 0xf0 214 #define PIXIS_LBMAP_SHIFT 4 215 #define PIXIS_LBMAP_ALTBANK 0x40 216 217 #define CONFIG_SYS_FLASH_QUIET_TEST 218 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 219 220 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 221 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 224 225 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 226 227 #if defined(CONFIG_RAMBOOT_PBL) 228 #define CONFIG_SYS_RAMBOOT 229 #endif 230 231 #define CONFIG_SYS_FLASH_EMPTY_INFO 232 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 234 235 #define CONFIG_BOARD_EARLY_INIT_F 236 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 237 #define CONFIG_MISC_INIT_R 238 239 #define CONFIG_HWCONFIG 240 241 /* define to use L1 as initial stack */ 242 #define CONFIG_L1_INIT_RAM 243 #define CONFIG_SYS_INIT_RAM_LOCK 244 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 245 #ifdef CONFIG_PHYS_64BIT 246 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 247 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 248 /* The assembler doesn't like typecast */ 249 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 250 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 251 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 252 #else 253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 256 #endif 257 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 258 259 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 260 GENERATED_GBL_DATA_SIZE) 261 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 262 263 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 264 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 265 266 /* Serial Port - controlled on board with jumper J8 267 * open - index 2 268 * shorted - index 1 269 */ 270 #define CONFIG_CONS_INDEX 1 271 #define CONFIG_SYS_NS16550 272 #define CONFIG_SYS_NS16550_SERIAL 273 #define CONFIG_SYS_NS16550_REG_SIZE 1 274 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 275 276 #define CONFIG_SYS_BAUDRATE_TABLE \ 277 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 278 279 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 280 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 281 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 282 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 283 284 /* Use the HUSH parser */ 285 #define CONFIG_SYS_HUSH_PARSER 286 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 287 288 /* pass open firmware flat tree */ 289 #define CONFIG_OF_LIBFDT 290 #define CONFIG_OF_BOARD_SETUP 291 #define CONFIG_OF_STDOUT_VIA_ALIAS 292 293 /* new uImage format support */ 294 #define CONFIG_FIT 295 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 296 297 /* I2C */ 298 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 299 #define CONFIG_HARD_I2C /* I2C with hardware support */ 300 #define CONFIG_I2C_MULTI_BUS 301 #define CONFIG_I2C_CMD_TREE 302 #define CONFIG_SYS_I2C_SPEED 400000 303 #define CONFIG_SYS_I2C_SLAVE 0x7F 304 #define CONFIG_SYS_I2C_OFFSET 0x118000 305 #define CONFIG_SYS_I2C2_OFFSET 0x118100 306 307 /* 308 * RapidIO 309 */ 310 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 311 #ifdef CONFIG_PHYS_64BIT 312 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 313 #else 314 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 315 #endif 316 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 317 318 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 319 #ifdef CONFIG_PHYS_64BIT 320 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 321 #else 322 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 323 #endif 324 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 325 326 /* 327 * eSPI - Enhanced SPI 328 */ 329 #define CONFIG_FSL_ESPI 330 #define CONFIG_SPI_FLASH 331 #define CONFIG_SPI_FLASH_SPANSION 332 #define CONFIG_CMD_SF 333 #define CONFIG_SF_DEFAULT_SPEED 10000000 334 #define CONFIG_SF_DEFAULT_MODE 0 335 336 /* 337 * General PCI 338 * Memory space is mapped 1-1, but I/O space must start from 0. 339 */ 340 341 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 342 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 345 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 346 #else 347 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 348 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 349 #endif 350 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 351 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 352 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 355 #else 356 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 357 #endif 358 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 359 360 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 361 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 362 #ifdef CONFIG_PHYS_64BIT 363 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 364 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 365 #else 366 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 367 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 368 #endif 369 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 370 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 371 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 372 #ifdef CONFIG_PHYS_64BIT 373 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 374 #else 375 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 376 #endif 377 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 378 379 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 380 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 381 #ifdef CONFIG_PHYS_64BIT 382 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 383 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 384 #else 385 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 386 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 387 #endif 388 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 389 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 390 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 391 #ifdef CONFIG_PHYS_64BIT 392 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 393 #else 394 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 395 #endif 396 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 397 398 /* Qman/Bman */ 399 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 400 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 401 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 404 #else 405 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 406 #endif 407 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 408 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 409 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 410 #ifdef CONFIG_PHYS_64BIT 411 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 412 #else 413 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 414 #endif 415 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 416 417 #define CONFIG_SYS_DPAA_FMAN 418 #define CONFIG_SYS_DPAA_PME 419 /* Default address of microcode for the Linux Fman driver */ 420 #define CONFIG_SYS_FMAN_FW 421 #if defined(CONFIG_SPIFLASH) 422 /* 423 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 424 * env, so we got 0x110000. 425 */ 426 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 427 #elif defined(CONFIG_SDCARD) 428 /* 429 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 430 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 431 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 432 */ 433 #define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) 434 #elif defined(CONFIG_NAND) 435 #define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 436 #else 437 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 438 #endif 439 #define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 440 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) 441 442 #ifdef CONFIG_SYS_DPAA_FMAN 443 #define CONFIG_FMAN_ENET 444 #endif 445 446 #ifdef CONFIG_PCI 447 #define CONFIG_NET_MULTI 448 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 449 #define CONFIG_E1000 450 451 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 452 #define CONFIG_DOS_PARTITION 453 #endif /* CONFIG_PCI */ 454 455 #ifdef CONFIG_FMAN_ENET 456 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 457 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 458 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 459 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 460 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 461 462 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 463 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 464 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 465 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 466 467 #define CONFIG_SYS_TBIPA_VALUE 8 468 #define CONFIG_MII /* MII PHY management */ 469 #define CONFIG_ETHPRIME "FM1@DTSEC1" 470 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 471 #endif 472 473 /* 474 * Environment 475 */ 476 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 477 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 478 479 /* 480 * Command line configuration. 481 */ 482 #include <config_cmd_default.h> 483 484 #define CONFIG_CMD_DHCP 485 #define CONFIG_CMD_ELF 486 #define CONFIG_CMD_ERRATA 487 #define CONFIG_CMD_GREPENV 488 #define CONFIG_CMD_IRQ 489 #define CONFIG_CMD_I2C 490 #define CONFIG_CMD_MII 491 #define CONFIG_CMD_PING 492 #define CONFIG_CMD_SETEXPR 493 494 #ifdef CONFIG_PCI 495 #define CONFIG_CMD_PCI 496 #define CONFIG_CMD_NET 497 #endif 498 499 /* 500 * USB 501 */ 502 #define CONFIG_CMD_USB 503 #define CONFIG_USB_STORAGE 504 #define CONFIG_USB_EHCI 505 #define CONFIG_USB_EHCI_FSL 506 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 507 #define CONFIG_CMD_EXT2 508 509 #define CONFIG_MMC 510 511 #ifdef CONFIG_MMC 512 #define CONFIG_FSL_ESDHC 513 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 514 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 515 #define CONFIG_CMD_MMC 516 #define CONFIG_GENERIC_MMC 517 #define CONFIG_CMD_EXT2 518 #define CONFIG_CMD_FAT 519 #define CONFIG_DOS_PARTITION 520 #endif 521 522 /* 523 * Miscellaneous configurable options 524 */ 525 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 526 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 527 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 528 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 529 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 530 #ifdef CONFIG_CMD_KGDB 531 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 532 #else 533 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 534 #endif 535 /* Print Buffer Size */ 536 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 537 sizeof(CONFIG_SYS_PROMPT)+16) 538 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 539 /* Boot Argument Buffer Size */ 540 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 541 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ 542 543 /* 544 * For booting Linux, the board info and command line data 545 * have to be in the first 64 MB of memory, since this is 546 * the maximum mapped by the Linux kernel during initialization. 547 */ 548 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 549 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 550 551 #ifdef CONFIG_CMD_KGDB 552 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 553 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 554 #endif 555 556 /* 557 * Environment Configuration 558 */ 559 #define CONFIG_ROOTPATH /opt/nfsroot 560 #define CONFIG_BOOTFILE uImage 561 #define CONFIG_UBOOTPATH u-boot.bin 562 563 /* default location for tftp and bootm */ 564 #define CONFIG_LOADADDR 1000000 565 566 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 567 568 #define CONFIG_BAUDRATE 115200 569 570 #define __USB_PHY_TYPE utmi 571 572 #define CONFIG_EXTRA_ENV_SETTINGS \ 573 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 574 "bank_intlv=cs0_cs1\0" \ 575 "netdev=eth0\0" \ 576 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 577 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 578 "tftpflash=tftpboot $loadaddr $uboot && " \ 579 "protect off $ubootaddr +$filesize && " \ 580 "erase $ubootaddr +$filesize && " \ 581 "cp.b $loadaddr $ubootaddr $filesize && " \ 582 "protect on $ubootaddr +$filesize && " \ 583 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 584 "consoledev=ttyS0\0" \ 585 "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ 586 "usb_dr_mode=host\0" \ 587 "ramdiskaddr=2000000\0" \ 588 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 589 "fdtaddr=c00000\0" \ 590 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 591 "bdev=sda3\0" \ 592 "c=ffe\0" 593 594 #define CONFIG_HDBOOT \ 595 "setenv bootargs root=/dev/$bdev rw " \ 596 "console=$consoledev,$baudrate $othbootargs;" \ 597 "tftp $loadaddr $bootfile;" \ 598 "tftp $fdtaddr $fdtfile;" \ 599 "bootm $loadaddr - $fdtaddr" 600 601 #define CONFIG_NFSBOOTCOMMAND \ 602 "setenv bootargs root=/dev/nfs rw " \ 603 "nfsroot=$serverip:$rootpath " \ 604 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 605 "console=$consoledev,$baudrate $othbootargs;" \ 606 "tftp $loadaddr $bootfile;" \ 607 "tftp $fdtaddr $fdtfile;" \ 608 "bootm $loadaddr - $fdtaddr" 609 610 #define CONFIG_RAMBOOTCOMMAND \ 611 "setenv bootargs root=/dev/ram rw " \ 612 "console=$consoledev,$baudrate $othbootargs;" \ 613 "tftp $ramdiskaddr $ramdiskfile;" \ 614 "tftp $loadaddr $bootfile;" \ 615 "tftp $fdtaddr $fdtfile;" \ 616 "bootm $loadaddr $ramdiskaddr $fdtaddr" 617 618 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 619 620 #ifdef CONFIG_SECURE_BOOT 621 #include <asm/fsl_secure_boot.h> 622 #endif 623 624 #endif /* __CONFIG_H */ 625