1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #endif 28 29 /* High Level Configuration Options */ 30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 31 #define CONFIG_MP /* support multiple processors */ 32 33 #ifndef CONFIG_SYS_TEXT_BASE 34 #define CONFIG_SYS_TEXT_BASE 0xeff40000 35 #endif 36 37 #ifndef CONFIG_RESET_VECTOR_ADDRESS 38 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 43 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 44 #define CONFIG_PCIE1 /* PCIE controller 1 */ 45 #define CONFIG_PCIE2 /* PCIE controller 2 */ 46 #define CONFIG_PCIE3 /* PCIE controller 3 */ 47 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 50 #define CONFIG_SYS_SRIO 51 #define CONFIG_SRIO1 /* SRIO port 1 */ 52 #define CONFIG_SRIO2 /* SRIO port 2 */ 53 #define CONFIG_SRIO_PCIE_BOOT_MASTER 54 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 55 56 #define CONFIG_ENV_OVERWRITE 57 58 #ifndef CONFIG_MTD_NOR_FLASH 59 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 60 #define CONFIG_ENV_IS_NOWHERE 61 #endif 62 #else 63 #define CONFIG_FLASH_CFI_DRIVER 64 #define CONFIG_SYS_FLASH_CFI 65 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 66 #endif 67 68 #if defined(CONFIG_SPIFLASH) 69 #define CONFIG_SYS_EXTRA_ENV_RELOC 70 #define CONFIG_ENV_IS_IN_SPI_FLASH 71 #define CONFIG_ENV_SPI_BUS 0 72 #define CONFIG_ENV_SPI_CS 0 73 #define CONFIG_ENV_SPI_MAX_HZ 10000000 74 #define CONFIG_ENV_SPI_MODE 0 75 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 76 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 77 #define CONFIG_ENV_SECT_SIZE 0x10000 78 #elif defined(CONFIG_SDCARD) 79 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_ENV_IS_IN_MMC 81 #define CONFIG_FSL_FIXED_MMC_LOCATION 82 #define CONFIG_SYS_MMC_ENV_DEV 0 83 #define CONFIG_ENV_SIZE 0x2000 84 #define CONFIG_ENV_OFFSET (512 * 1658) 85 #elif defined(CONFIG_NAND) 86 #define CONFIG_SYS_EXTRA_ENV_RELOC 87 #define CONFIG_ENV_IS_IN_NAND 88 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 89 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 90 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 91 #define CONFIG_ENV_IS_IN_REMOTE 92 #define CONFIG_ENV_ADDR 0xffe20000 93 #define CONFIG_ENV_SIZE 0x2000 94 #elif defined(CONFIG_ENV_IS_NOWHERE) 95 #define CONFIG_ENV_SIZE 0x2000 96 #else 97 #define CONFIG_ENV_IS_IN_FLASH 98 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 99 - CONFIG_ENV_SECT_SIZE) 100 #define CONFIG_ENV_SIZE 0x2000 101 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 102 #endif 103 104 #ifndef __ASSEMBLY__ 105 unsigned long get_board_sys_clk(unsigned long dummy); 106 #endif 107 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_BACKSIDE_L2_CACHE 114 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 115 #define CONFIG_BTB /* toggle branch predition */ 116 117 #define CONFIG_ENABLE_36BIT_PHYS 118 119 #ifdef CONFIG_PHYS_64BIT 120 #define CONFIG_ADDR_MAP 121 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 122 #endif 123 124 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 125 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 126 #define CONFIG_SYS_MEMTEST_END 0x00400000 127 #define CONFIG_SYS_ALT_MEMTEST 128 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 129 130 /* 131 * Config the L3 Cache as L3 SRAM 132 */ 133 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 136 CONFIG_RAMBOOT_TEXT_BASE) 137 #else 138 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 139 #endif 140 #define CONFIG_SYS_L3_SIZE (1024 << 10) 141 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 142 143 #ifdef CONFIG_PHYS_64BIT 144 #define CONFIG_SYS_DCSRBAR 0xf0000000 145 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 146 #endif 147 148 /* EEPROM */ 149 #define CONFIG_ID_EEPROM 150 #define CONFIG_SYS_I2C_EEPROM_NXID 151 #define CONFIG_SYS_EEPROM_BUS_NUM 0 152 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 154 155 /* 156 * DDR Setup 157 */ 158 #define CONFIG_VERY_BIG_RAM 159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 161 162 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 163 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 164 165 #define CONFIG_DDR_SPD 166 167 #define CONFIG_SYS_SPD_BUS_NUM 0 168 #define SPD_EEPROM_ADDRESS 0x52 169 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 170 171 /* 172 * Local Bus Definitions 173 */ 174 175 /* Set the local bus clock 1/8 of platform clock */ 176 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 177 178 /* 179 * This board doesn't have a promjet connector. 180 * However, it uses commone corenet board LAW and TLB. 181 * It is necessary to use the same start address with proper offset. 182 */ 183 #define CONFIG_SYS_FLASH_BASE 0xe0000000 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 186 #else 187 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 188 #endif 189 190 #define CONFIG_SYS_FLASH_BR_PRELIM \ 191 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 192 BR_PS_16 | BR_V) 193 #define CONFIG_SYS_FLASH_OR_PRELIM \ 194 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 195 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 196 197 #define CONFIG_FSL_CPLD 198 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 199 #ifdef CONFIG_PHYS_64BIT 200 #define CPLD_BASE_PHYS 0xfffdf0000ull 201 #else 202 #define CPLD_BASE_PHYS CPLD_BASE 203 #endif 204 205 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 206 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 207 208 #define PIXIS_LBMAP_SWITCH 7 209 #define PIXIS_LBMAP_MASK 0xf0 210 #define PIXIS_LBMAP_SHIFT 4 211 #define PIXIS_LBMAP_ALTBANK 0x40 212 213 #define CONFIG_SYS_FLASH_QUIET_TEST 214 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 215 216 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 217 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 220 221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 222 223 #if defined(CONFIG_RAMBOOT_PBL) 224 #define CONFIG_SYS_RAMBOOT 225 #endif 226 227 #define CONFIG_NAND_FSL_ELBC 228 /* Nand Flash */ 229 #ifdef CONFIG_NAND_FSL_ELBC 230 #define CONFIG_SYS_NAND_BASE 0xffa00000 231 #ifdef CONFIG_PHYS_64BIT 232 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 233 #else 234 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 235 #endif 236 237 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 238 #define CONFIG_SYS_MAX_NAND_DEVICE 1 239 #define CONFIG_CMD_NAND 240 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 241 242 /* NAND flash config */ 243 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 244 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 245 | BR_PS_8 /* Port Size = 8 bit */ \ 246 | BR_MS_FCM /* MSEL = FCM */ \ 247 | BR_V) /* valid */ 248 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 249 | OR_FCM_PGS /* Large Page*/ \ 250 | OR_FCM_CSCT \ 251 | OR_FCM_CST \ 252 | OR_FCM_CHT \ 253 | OR_FCM_SCY_1 \ 254 | OR_FCM_TRLX \ 255 | OR_FCM_EHTR) 256 257 #ifdef CONFIG_NAND 258 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 259 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 260 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 261 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 262 #else 263 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 264 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 265 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 266 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 267 #endif 268 #else 269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 271 #endif /* CONFIG_NAND_FSL_ELBC */ 272 273 #define CONFIG_SYS_FLASH_EMPTY_INFO 274 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 275 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 276 277 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 278 #define CONFIG_MISC_INIT_R 279 280 #define CONFIG_HWCONFIG 281 282 /* define to use L1 as initial stack */ 283 #define CONFIG_L1_INIT_RAM 284 #define CONFIG_SYS_INIT_RAM_LOCK 285 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 289 /* The assembler doesn't like typecast */ 290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 291 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 292 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 293 #else 294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 297 #endif 298 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 299 300 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 301 GENERATED_GBL_DATA_SIZE) 302 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 303 304 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 305 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 306 307 /* Serial Port - controlled on board with jumper J8 308 * open - index 2 309 * shorted - index 1 310 */ 311 #define CONFIG_CONS_INDEX 1 312 #define CONFIG_SYS_NS16550_SERIAL 313 #define CONFIG_SYS_NS16550_REG_SIZE 1 314 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 315 316 #define CONFIG_SYS_BAUDRATE_TABLE \ 317 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 318 319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 321 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 322 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 323 324 /* I2C */ 325 #define CONFIG_SYS_I2C 326 #define CONFIG_SYS_I2C_FSL 327 #define CONFIG_SYS_FSL_I2C_SPEED 400000 328 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 329 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 330 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 331 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 332 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 333 334 /* 335 * RapidIO 336 */ 337 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 338 #ifdef CONFIG_PHYS_64BIT 339 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 340 #else 341 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 342 #endif 343 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 344 345 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 346 #ifdef CONFIG_PHYS_64BIT 347 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 348 #else 349 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 350 #endif 351 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 352 353 /* 354 * for slave u-boot IMAGE instored in master memory space, 355 * PHYS must be aligned based on the SIZE 356 */ 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 360 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 361 /* 362 * for slave UCODE and ENV instored in master memory space, 363 * PHYS must be aligned based on the SIZE 364 */ 365 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 367 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 368 369 /* slave core release by master*/ 370 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 371 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 372 373 /* 374 * SRIO_PCIE_BOOT - SLAVE 375 */ 376 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 377 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 378 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 379 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 380 #endif 381 382 /* 383 * eSPI - Enhanced SPI 384 */ 385 #define CONFIG_SF_DEFAULT_SPEED 10000000 386 #define CONFIG_SF_DEFAULT_MODE 0 387 388 /* 389 * General PCI 390 * Memory space is mapped 1-1, but I/O space must start from 0. 391 */ 392 393 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 394 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 395 #ifdef CONFIG_PHYS_64BIT 396 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 397 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 398 #else 399 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 401 #endif 402 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 403 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 404 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 407 #else 408 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 409 #endif 410 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 411 412 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 413 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 416 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 417 #else 418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 420 #endif 421 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 422 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 423 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 426 #else 427 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 428 #endif 429 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 430 431 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 432 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 435 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 436 #else 437 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 439 #endif 440 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 441 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 442 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 445 #else 446 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 447 #endif 448 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 449 450 /* Qman/Bman */ 451 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 452 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 453 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 454 #ifdef CONFIG_PHYS_64BIT 455 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 456 #else 457 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 458 #endif 459 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 460 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 461 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 462 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 463 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 464 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 465 CONFIG_SYS_BMAN_CENA_SIZE) 466 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 467 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 468 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 469 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 472 #else 473 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 474 #endif 475 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 476 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 477 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 478 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 479 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 480 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 481 CONFIG_SYS_QMAN_CENA_SIZE) 482 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 483 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 484 485 #define CONFIG_SYS_DPAA_FMAN 486 #define CONFIG_SYS_DPAA_PME 487 /* Default address of microcode for the Linux Fman driver */ 488 #if defined(CONFIG_SPIFLASH) 489 /* 490 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 491 * env, so we got 0x110000. 492 */ 493 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 494 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 495 #elif defined(CONFIG_SDCARD) 496 /* 497 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 498 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 499 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 500 */ 501 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 502 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 503 #elif defined(CONFIG_NAND) 504 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 505 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 506 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 507 /* 508 * Slave has no ucode locally, it can fetch this from remote. When implementing 509 * in two corenet boards, slave's ucode could be stored in master's memory 510 * space, the address can be mapped from slave TLB->slave LAW-> 511 * slave SRIO or PCIE outbound window->master inbound window-> 512 * master LAW->the ucode address in master's memory space. 513 */ 514 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 515 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 516 #else 517 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 518 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 519 #endif 520 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 521 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 522 523 #ifdef CONFIG_SYS_DPAA_FMAN 524 #define CONFIG_FMAN_ENET 525 #define CONFIG_PHYLIB_10G 526 #define CONFIG_PHY_VITESSE 527 #define CONFIG_PHY_TERANETICS 528 #endif 529 530 #ifdef CONFIG_PCI 531 #define CONFIG_PCI_INDIRECT_BRIDGE 532 533 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 534 #endif /* CONFIG_PCI */ 535 536 /* SATA */ 537 #define CONFIG_FSL_SATA_V2 538 539 #ifdef CONFIG_FSL_SATA_V2 540 #define CONFIG_FSL_SATA 541 #define CONFIG_LIBATA 542 543 #define CONFIG_SYS_SATA_MAX_DEVICE 2 544 #define CONFIG_SATA1 545 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 546 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 547 #define CONFIG_SATA2 548 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 549 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 550 551 #define CONFIG_LBA48 552 #define CONFIG_CMD_SATA 553 #endif 554 555 #ifdef CONFIG_FMAN_ENET 556 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 557 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 558 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 559 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 560 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 561 562 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 563 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 564 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 565 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 566 567 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 568 569 #define CONFIG_SYS_TBIPA_VALUE 8 570 #define CONFIG_MII /* MII PHY management */ 571 #define CONFIG_ETHPRIME "FM1@DTSEC1" 572 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 573 #endif 574 575 /* 576 * Environment 577 */ 578 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 579 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 580 581 /* 582 * Command line configuration. 583 */ 584 #define CONFIG_CMD_ERRATA 585 #define CONFIG_CMD_IRQ 586 587 #ifdef CONFIG_PCI 588 #define CONFIG_CMD_PCI 589 #endif 590 591 /* 592 * USB 593 */ 594 #define CONFIG_HAS_FSL_DR_USB 595 #define CONFIG_HAS_FSL_MPH_USB 596 597 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 598 #define CONFIG_USB_EHCI 599 #define CONFIG_USB_EHCI_FSL 600 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 601 #endif 602 603 #ifdef CONFIG_MMC 604 #define CONFIG_FSL_ESDHC 605 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 606 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 607 #endif 608 609 /* Hash command with SHA acceleration supported in hardware */ 610 #ifdef CONFIG_FSL_CAAM 611 #define CONFIG_CMD_HASH 612 #define CONFIG_SHA_HW_ACCEL 613 #endif 614 615 /* 616 * Miscellaneous configurable options 617 */ 618 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 619 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 620 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 621 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 622 #ifdef CONFIG_CMD_KGDB 623 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 624 #else 625 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 626 #endif 627 /* Print Buffer Size */ 628 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 629 sizeof(CONFIG_SYS_PROMPT)+16) 630 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 631 /* Boot Argument Buffer Size */ 632 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 633 634 /* 635 * For booting Linux, the board info and command line data 636 * have to be in the first 64 MB of memory, since this is 637 * the maximum mapped by the Linux kernel during initialization. 638 */ 639 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 640 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 641 642 #ifdef CONFIG_CMD_KGDB 643 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 644 #endif 645 646 /* 647 * Environment Configuration 648 */ 649 #define CONFIG_ROOTPATH "/opt/nfsroot" 650 #define CONFIG_BOOTFILE "uImage" 651 #define CONFIG_UBOOTPATH u-boot.bin 652 653 /* default location for tftp and bootm */ 654 #define CONFIG_LOADADDR 1000000 655 656 657 #define CONFIG_BAUDRATE 115200 658 659 #define __USB_PHY_TYPE utmi 660 661 #define CONFIG_EXTRA_ENV_SETTINGS \ 662 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 663 "bank_intlv=cs0_cs1\0" \ 664 "netdev=eth0\0" \ 665 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 666 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 667 "tftpflash=tftpboot $loadaddr $uboot && " \ 668 "protect off $ubootaddr +$filesize && " \ 669 "erase $ubootaddr +$filesize && " \ 670 "cp.b $loadaddr $ubootaddr $filesize && " \ 671 "protect on $ubootaddr +$filesize && " \ 672 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 673 "consoledev=ttyS0\0" \ 674 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 675 "usb_dr_mode=host\0" \ 676 "ramdiskaddr=2000000\0" \ 677 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 678 "fdtaddr=1e00000\0" \ 679 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 680 "bdev=sda3\0" 681 682 #define CONFIG_HDBOOT \ 683 "setenv bootargs root=/dev/$bdev rw " \ 684 "console=$consoledev,$baudrate $othbootargs;" \ 685 "tftp $loadaddr $bootfile;" \ 686 "tftp $fdtaddr $fdtfile;" \ 687 "bootm $loadaddr - $fdtaddr" 688 689 #define CONFIG_NFSBOOTCOMMAND \ 690 "setenv bootargs root=/dev/nfs rw " \ 691 "nfsroot=$serverip:$rootpath " \ 692 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 693 "console=$consoledev,$baudrate $othbootargs;" \ 694 "tftp $loadaddr $bootfile;" \ 695 "tftp $fdtaddr $fdtfile;" \ 696 "bootm $loadaddr - $fdtaddr" 697 698 #define CONFIG_RAMBOOTCOMMAND \ 699 "setenv bootargs root=/dev/ram rw " \ 700 "console=$consoledev,$baudrate $othbootargs;" \ 701 "tftp $ramdiskaddr $ramdiskfile;" \ 702 "tftp $loadaddr $bootfile;" \ 703 "tftp $fdtaddr $fdtfile;" \ 704 "bootm $loadaddr $ramdiskaddr $fdtaddr" 705 706 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 707 708 #include <asm/fsl_secure_boot.h> 709 710 #endif /* __CONFIG_H */ 711