1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_P2041RDB 15 #define CONFIG_PPC_P2041 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 20 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 21 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 22 #endif 23 24 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 25 /* Set 1M boot space */ 26 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 27 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 28 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 30 #define CONFIG_SYS_NO_FLASH 31 #endif 32 33 /* High Level Configuration Options */ 34 #define CONFIG_BOOKE 35 #define CONFIG_E500 /* BOOKE e500 family */ 36 #define CONFIG_E500MC /* BOOKE e500mc family */ 37 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 38 #define CONFIG_MP /* support multiple processors */ 39 40 #ifndef CONFIG_SYS_TEXT_BASE 41 #define CONFIG_SYS_TEXT_BASE 0xeff40000 42 #endif 43 44 #ifndef CONFIG_RESET_VECTOR_ADDRESS 45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 46 #endif 47 48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 49 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 50 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 51 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 52 #define CONFIG_PCI /* Enable PCI/PCIE */ 53 #define CONFIG_PCIE1 /* PCIE controller 1 */ 54 #define CONFIG_PCIE2 /* PCIE controller 2 */ 55 #define CONFIG_PCIE3 /* PCIE controller 3 */ 56 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 57 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 58 59 #define CONFIG_SYS_SRIO 60 #define CONFIG_SRIO1 /* SRIO port 1 */ 61 #define CONFIG_SRIO2 /* SRIO port 2 */ 62 #define CONFIG_SRIO_PCIE_BOOT_MASTER 63 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 64 65 #define CONFIG_FSL_LAW /* Use common FSL init code */ 66 67 #define CONFIG_ENV_OVERWRITE 68 69 #ifdef CONFIG_SYS_NO_FLASH 70 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 71 #define CONFIG_ENV_IS_NOWHERE 72 #endif 73 #else 74 #define CONFIG_FLASH_CFI_DRIVER 75 #define CONFIG_SYS_FLASH_CFI 76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 77 #endif 78 79 #if defined(CONFIG_SPIFLASH) 80 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #elif defined(CONFIG_SDCARD) 90 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_FSL_FIXED_MMC_LOCATION 93 #define CONFIG_SYS_MMC_ENV_DEV 0 94 #define CONFIG_ENV_SIZE 0x2000 95 #define CONFIG_ENV_OFFSET (512 * 1658) 96 #elif defined(CONFIG_NAND) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_NAND 99 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 100 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 101 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 102 #define CONFIG_ENV_IS_IN_REMOTE 103 #define CONFIG_ENV_ADDR 0xffe20000 104 #define CONFIG_ENV_SIZE 0x2000 105 #elif defined(CONFIG_ENV_IS_NOWHERE) 106 #define CONFIG_ENV_SIZE 0x2000 107 #else 108 #define CONFIG_ENV_IS_IN_FLASH 109 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 110 - CONFIG_ENV_SECT_SIZE) 111 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 113 #endif 114 115 #ifndef __ASSEMBLY__ 116 unsigned long get_board_sys_clk(unsigned long dummy); 117 #endif 118 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 119 120 /* 121 * These can be toggled for performance analysis, otherwise use default. 122 */ 123 #define CONFIG_SYS_CACHE_STASHING 124 #define CONFIG_BACKSIDE_L2_CACHE 125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 126 #define CONFIG_BTB /* toggle branch predition */ 127 128 #define CONFIG_ENABLE_36BIT_PHYS 129 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_ADDR_MAP 132 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 133 #endif 134 135 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 136 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 137 #define CONFIG_SYS_MEMTEST_END 0x00400000 138 #define CONFIG_SYS_ALT_MEMTEST 139 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 140 141 /* 142 * Config the L3 Cache as L3 SRAM 143 */ 144 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 147 CONFIG_RAMBOOT_TEXT_BASE) 148 #else 149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 150 #endif 151 #define CONFIG_SYS_L3_SIZE (1024 << 10) 152 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 153 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_DCSRBAR 0xf0000000 156 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 157 #endif 158 159 /* EEPROM */ 160 #define CONFIG_ID_EEPROM 161 #define CONFIG_SYS_I2C_EEPROM_NXID 162 #define CONFIG_SYS_EEPROM_BUS_NUM 0 163 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 164 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 165 166 /* 167 * DDR Setup 168 */ 169 #define CONFIG_VERY_BIG_RAM 170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 172 173 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 174 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 175 176 #define CONFIG_DDR_SPD 177 #define CONFIG_SYS_FSL_DDR3 178 179 #define CONFIG_SYS_SPD_BUS_NUM 0 180 #define SPD_EEPROM_ADDRESS 0x52 181 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 182 183 /* 184 * Local Bus Definitions 185 */ 186 187 /* Set the local bus clock 1/8 of platform clock */ 188 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 189 190 /* 191 * This board doesn't have a promjet connector. 192 * However, it uses commone corenet board LAW and TLB. 193 * It is necessary to use the same start address with proper offset. 194 */ 195 #define CONFIG_SYS_FLASH_BASE 0xe0000000 196 #ifdef CONFIG_PHYS_64BIT 197 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 198 #else 199 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 200 #endif 201 202 #define CONFIG_SYS_FLASH_BR_PRELIM \ 203 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 204 BR_PS_16 | BR_V) 205 #define CONFIG_SYS_FLASH_OR_PRELIM \ 206 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 207 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 208 209 #define CONFIG_FSL_CPLD 210 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 211 #ifdef CONFIG_PHYS_64BIT 212 #define CPLD_BASE_PHYS 0xfffdf0000ull 213 #else 214 #define CPLD_BASE_PHYS CPLD_BASE 215 #endif 216 217 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 218 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 219 220 #define PIXIS_LBMAP_SWITCH 7 221 #define PIXIS_LBMAP_MASK 0xf0 222 #define PIXIS_LBMAP_SHIFT 4 223 #define PIXIS_LBMAP_ALTBANK 0x40 224 225 #define CONFIG_SYS_FLASH_QUIET_TEST 226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 227 228 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 232 233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 234 235 #if defined(CONFIG_RAMBOOT_PBL) 236 #define CONFIG_SYS_RAMBOOT 237 #endif 238 239 #define CONFIG_NAND_FSL_ELBC 240 /* Nand Flash */ 241 #ifdef CONFIG_NAND_FSL_ELBC 242 #define CONFIG_SYS_NAND_BASE 0xffa00000 243 #ifdef CONFIG_PHYS_64BIT 244 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 245 #else 246 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 247 #endif 248 249 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 250 #define CONFIG_SYS_MAX_NAND_DEVICE 1 251 #define CONFIG_CMD_NAND 252 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 253 254 /* NAND flash config */ 255 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 256 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 257 | BR_PS_8 /* Port Size = 8 bit */ \ 258 | BR_MS_FCM /* MSEL = FCM */ \ 259 | BR_V) /* valid */ 260 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 261 | OR_FCM_PGS /* Large Page*/ \ 262 | OR_FCM_CSCT \ 263 | OR_FCM_CST \ 264 | OR_FCM_CHT \ 265 | OR_FCM_SCY_1 \ 266 | OR_FCM_TRLX \ 267 | OR_FCM_EHTR) 268 269 #ifdef CONFIG_NAND 270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 272 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 273 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 274 #else 275 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 276 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 277 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 278 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 279 #endif 280 #else 281 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 282 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 283 #endif /* CONFIG_NAND_FSL_ELBC */ 284 285 #define CONFIG_SYS_FLASH_EMPTY_INFO 286 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 287 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 288 289 #define CONFIG_BOARD_EARLY_INIT_F 290 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 291 #define CONFIG_MISC_INIT_R 292 293 #define CONFIG_HWCONFIG 294 295 /* define to use L1 as initial stack */ 296 #define CONFIG_L1_INIT_RAM 297 #define CONFIG_SYS_INIT_RAM_LOCK 298 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 302 /* The assembler doesn't like typecast */ 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 304 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 305 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 306 #else 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 310 #endif 311 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 312 313 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 314 GENERATED_GBL_DATA_SIZE) 315 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 316 317 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 318 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 319 320 /* Serial Port - controlled on board with jumper J8 321 * open - index 2 322 * shorted - index 1 323 */ 324 #define CONFIG_CONS_INDEX 1 325 #define CONFIG_SYS_NS16550_SERIAL 326 #define CONFIG_SYS_NS16550_REG_SIZE 1 327 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 328 329 #define CONFIG_SYS_BAUDRATE_TABLE \ 330 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 331 332 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 333 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 334 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 335 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 336 337 /* I2C */ 338 #define CONFIG_SYS_I2C 339 #define CONFIG_SYS_I2C_FSL 340 #define CONFIG_SYS_FSL_I2C_SPEED 400000 341 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 342 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 343 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 344 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 345 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 346 347 /* 348 * RapidIO 349 */ 350 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 353 #else 354 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 355 #endif 356 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 357 358 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 361 #else 362 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 363 #endif 364 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 365 366 /* 367 * for slave u-boot IMAGE instored in master memory space, 368 * PHYS must be aligned based on the SIZE 369 */ 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 374 /* 375 * for slave UCODE and ENV instored in master memory space, 376 * PHYS must be aligned based on the SIZE 377 */ 378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 379 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 381 382 /* slave core release by master*/ 383 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 384 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 385 386 /* 387 * SRIO_PCIE_BOOT - SLAVE 388 */ 389 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 390 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 391 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 392 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 393 #endif 394 395 /* 396 * eSPI - Enhanced SPI 397 */ 398 #define CONFIG_SF_DEFAULT_SPEED 10000000 399 #define CONFIG_SF_DEFAULT_MODE 0 400 401 /* 402 * General PCI 403 * Memory space is mapped 1-1, but I/O space must start from 0. 404 */ 405 406 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 407 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 410 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 411 #else 412 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 413 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 414 #endif 415 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 416 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 417 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 420 #else 421 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 422 #endif 423 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 424 425 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 426 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 429 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 430 #else 431 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 432 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 433 #endif 434 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 435 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 436 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 439 #else 440 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 441 #endif 442 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 443 444 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 445 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 448 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 449 #else 450 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 451 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 452 #endif 453 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 454 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 455 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 456 #ifdef CONFIG_PHYS_64BIT 457 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 458 #else 459 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 460 #endif 461 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 462 463 /* Qman/Bman */ 464 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 465 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 466 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 469 #else 470 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 471 #endif 472 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 473 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 474 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 475 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 476 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 477 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 478 CONFIG_SYS_BMAN_CENA_SIZE) 479 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 480 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 481 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 482 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 483 #ifdef CONFIG_PHYS_64BIT 484 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 485 #else 486 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 487 #endif 488 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 489 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 490 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 491 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 492 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 493 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 494 CONFIG_SYS_QMAN_CENA_SIZE) 495 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 496 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 497 498 #define CONFIG_SYS_DPAA_FMAN 499 #define CONFIG_SYS_DPAA_PME 500 /* Default address of microcode for the Linux Fman driver */ 501 #if defined(CONFIG_SPIFLASH) 502 /* 503 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 504 * env, so we got 0x110000. 505 */ 506 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 507 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 508 #elif defined(CONFIG_SDCARD) 509 /* 510 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 511 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 512 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 513 */ 514 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 515 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 516 #elif defined(CONFIG_NAND) 517 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 518 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 519 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 520 /* 521 * Slave has no ucode locally, it can fetch this from remote. When implementing 522 * in two corenet boards, slave's ucode could be stored in master's memory 523 * space, the address can be mapped from slave TLB->slave LAW-> 524 * slave SRIO or PCIE outbound window->master inbound window-> 525 * master LAW->the ucode address in master's memory space. 526 */ 527 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 528 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 529 #else 530 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 531 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 532 #endif 533 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 534 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 535 536 #ifdef CONFIG_SYS_DPAA_FMAN 537 #define CONFIG_FMAN_ENET 538 #define CONFIG_PHYLIB_10G 539 #define CONFIG_PHY_VITESSE 540 #define CONFIG_PHY_TERANETICS 541 #endif 542 543 #ifdef CONFIG_PCI 544 #define CONFIG_PCI_INDIRECT_BRIDGE 545 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 546 547 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 548 #define CONFIG_DOS_PARTITION 549 #endif /* CONFIG_PCI */ 550 551 /* SATA */ 552 #define CONFIG_FSL_SATA_V2 553 554 #ifdef CONFIG_FSL_SATA_V2 555 #define CONFIG_FSL_SATA 556 #define CONFIG_LIBATA 557 558 #define CONFIG_SYS_SATA_MAX_DEVICE 2 559 #define CONFIG_SATA1 560 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 561 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 562 #define CONFIG_SATA2 563 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 564 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 565 566 #define CONFIG_LBA48 567 #define CONFIG_CMD_SATA 568 #define CONFIG_DOS_PARTITION 569 #endif 570 571 #ifdef CONFIG_FMAN_ENET 572 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 573 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 574 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 575 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 576 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 577 578 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 579 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 580 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 581 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 582 583 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 584 585 #define CONFIG_SYS_TBIPA_VALUE 8 586 #define CONFIG_MII /* MII PHY management */ 587 #define CONFIG_ETHPRIME "FM1@DTSEC1" 588 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 589 #endif 590 591 /* 592 * Environment 593 */ 594 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 595 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 596 597 /* 598 * Command line configuration. 599 */ 600 #define CONFIG_CMD_ERRATA 601 #define CONFIG_CMD_IRQ 602 603 #ifdef CONFIG_PCI 604 #define CONFIG_CMD_PCI 605 #endif 606 607 /* 608 * USB 609 */ 610 #define CONFIG_HAS_FSL_DR_USB 611 #define CONFIG_HAS_FSL_MPH_USB 612 613 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 614 #define CONFIG_USB_EHCI 615 #define CONFIG_USB_EHCI_FSL 616 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 617 #endif 618 619 #define CONFIG_MMC 620 621 #ifdef CONFIG_MMC 622 #define CONFIG_FSL_ESDHC 623 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 624 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 625 #define CONFIG_GENERIC_MMC 626 #define CONFIG_DOS_PARTITION 627 #endif 628 629 /* Hash command with SHA acceleration supported in hardware */ 630 #ifdef CONFIG_FSL_CAAM 631 #define CONFIG_CMD_HASH 632 #define CONFIG_SHA_HW_ACCEL 633 #endif 634 635 /* 636 * Miscellaneous configurable options 637 */ 638 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 639 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 640 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 641 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 642 #ifdef CONFIG_CMD_KGDB 643 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 644 #else 645 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 646 #endif 647 /* Print Buffer Size */ 648 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 649 sizeof(CONFIG_SYS_PROMPT)+16) 650 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 651 /* Boot Argument Buffer Size */ 652 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 653 654 /* 655 * For booting Linux, the board info and command line data 656 * have to be in the first 64 MB of memory, since this is 657 * the maximum mapped by the Linux kernel during initialization. 658 */ 659 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 660 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 661 662 #ifdef CONFIG_CMD_KGDB 663 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 664 #endif 665 666 /* 667 * Environment Configuration 668 */ 669 #define CONFIG_ROOTPATH "/opt/nfsroot" 670 #define CONFIG_BOOTFILE "uImage" 671 #define CONFIG_UBOOTPATH u-boot.bin 672 673 /* default location for tftp and bootm */ 674 #define CONFIG_LOADADDR 1000000 675 676 677 #define CONFIG_BAUDRATE 115200 678 679 #define __USB_PHY_TYPE utmi 680 681 #define CONFIG_EXTRA_ENV_SETTINGS \ 682 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 683 "bank_intlv=cs0_cs1\0" \ 684 "netdev=eth0\0" \ 685 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 686 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 687 "tftpflash=tftpboot $loadaddr $uboot && " \ 688 "protect off $ubootaddr +$filesize && " \ 689 "erase $ubootaddr +$filesize && " \ 690 "cp.b $loadaddr $ubootaddr $filesize && " \ 691 "protect on $ubootaddr +$filesize && " \ 692 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 693 "consoledev=ttyS0\0" \ 694 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 695 "usb_dr_mode=host\0" \ 696 "ramdiskaddr=2000000\0" \ 697 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 698 "fdtaddr=1e00000\0" \ 699 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 700 "bdev=sda3\0" 701 702 #define CONFIG_HDBOOT \ 703 "setenv bootargs root=/dev/$bdev rw " \ 704 "console=$consoledev,$baudrate $othbootargs;" \ 705 "tftp $loadaddr $bootfile;" \ 706 "tftp $fdtaddr $fdtfile;" \ 707 "bootm $loadaddr - $fdtaddr" 708 709 #define CONFIG_NFSBOOTCOMMAND \ 710 "setenv bootargs root=/dev/nfs rw " \ 711 "nfsroot=$serverip:$rootpath " \ 712 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 713 "console=$consoledev,$baudrate $othbootargs;" \ 714 "tftp $loadaddr $bootfile;" \ 715 "tftp $fdtaddr $fdtfile;" \ 716 "bootm $loadaddr - $fdtaddr" 717 718 #define CONFIG_RAMBOOTCOMMAND \ 719 "setenv bootargs root=/dev/ram rw " \ 720 "console=$consoledev,$baudrate $othbootargs;" \ 721 "tftp $ramdiskaddr $ramdiskfile;" \ 722 "tftp $loadaddr $bootfile;" \ 723 "tftp $fdtaddr $fdtfile;" \ 724 "bootm $loadaddr $ramdiskaddr $fdtaddr" 725 726 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 727 728 #include <asm/fsl_secure_boot.h> 729 730 #endif /* __CONFIG_H */ 731