1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * P2041 RDB board configuration file 25 * Also supports P2040 RDB 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #define CONFIG_P2041RDB 31 #define CONFIG_PHYS_64BIT 32 #define CONFIG_PPC_P2041 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #define CONFIG_SYS_NO_FLASH 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_BOOKE 50 #define CONFIG_E500 /* BOOKE e500 family */ 51 #define CONFIG_E500MC /* BOOKE e500mc family */ 52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 53 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 54 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 55 #define CONFIG_MP /* support multiple processors */ 56 57 #ifndef CONFIG_SYS_TEXT_BASE 58 #define CONFIG_SYS_TEXT_BASE 0xeff80000 59 #endif 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 63 #endif 64 65 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 66 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 67 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 68 #define CONFIG_PCI /* Enable PCI/PCIE */ 69 #define CONFIG_PCIE1 /* PCIE controler 1 */ 70 #define CONFIG_PCIE2 /* PCIE controler 2 */ 71 #define CONFIG_PCIE3 /* PCIE controler 3 */ 72 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 74 75 #define CONFIG_SYS_SRIO 76 #define CONFIG_SRIO1 /* SRIO port 1 */ 77 #define CONFIG_SRIO2 /* SRIO port 2 */ 78 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 79 80 #define CONFIG_FSL_LAW /* Use common FSL init code */ 81 82 #define CONFIG_ENV_OVERWRITE 83 84 #ifdef CONFIG_SYS_NO_FLASH 85 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 86 #define CONFIG_ENV_IS_NOWHERE 87 #endif 88 #else 89 #define CONFIG_FLASH_CFI_DRIVER 90 #define CONFIG_SYS_FLASH_CFI 91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 92 #endif 93 94 #if defined(CONFIG_SPIFLASH) 95 #define CONFIG_SYS_EXTRA_ENV_RELOC 96 #define CONFIG_ENV_IS_IN_SPI_FLASH 97 #define CONFIG_ENV_SPI_BUS 0 98 #define CONFIG_ENV_SPI_CS 0 99 #define CONFIG_ENV_SPI_MAX_HZ 10000000 100 #define CONFIG_ENV_SPI_MODE 0 101 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 102 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 103 #define CONFIG_ENV_SECT_SIZE 0x10000 104 #elif defined(CONFIG_SDCARD) 105 #define CONFIG_SYS_EXTRA_ENV_RELOC 106 #define CONFIG_ENV_IS_IN_MMC 107 #define CONFIG_FSL_FIXED_MMC_LOCATION 108 #define CONFIG_SYS_MMC_ENV_DEV 0 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_OFFSET (512 * 1097) 111 #elif defined(CONFIG_NAND) 112 #define CONFIG_SYS_EXTRA_ENV_RELOC 113 #define CONFIG_ENV_IS_IN_NAND 114 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 115 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 116 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 117 #define CONFIG_ENV_IS_IN_REMOTE 118 #define CONFIG_ENV_ADDR 0xffe20000 119 #define CONFIG_ENV_SIZE 0x2000 120 #elif defined(CONFIG_ENV_IS_NOWHERE) 121 #define CONFIG_ENV_SIZE 0x2000 122 #else 123 #define CONFIG_ENV_IS_IN_FLASH 124 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 125 - CONFIG_ENV_SECT_SIZE) 126 #define CONFIG_ENV_SIZE 0x2000 127 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 128 #endif 129 130 #ifndef __ASSEMBLY__ 131 unsigned long get_board_sys_clk(unsigned long dummy); 132 #endif 133 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 134 135 /* 136 * These can be toggled for performance analysis, otherwise use default. 137 */ 138 #define CONFIG_SYS_CACHE_STASHING 139 #define CONFIG_BACKSIDE_L2_CACHE 140 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 141 #define CONFIG_BTB /* toggle branch predition */ 142 143 #define CONFIG_ENABLE_36BIT_PHYS 144 145 #ifdef CONFIG_PHYS_64BIT 146 #define CONFIG_ADDR_MAP 147 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 148 #endif 149 150 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 151 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 152 #define CONFIG_SYS_MEMTEST_END 0x00400000 153 #define CONFIG_SYS_ALT_MEMTEST 154 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 155 156 /* 157 * Config the L3 Cache as L3 SRAM 158 */ 159 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 162 CONFIG_RAMBOOT_TEXT_BASE) 163 #else 164 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 165 #endif 166 #define CONFIG_SYS_L3_SIZE (1024 << 10) 167 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 168 169 #ifdef CONFIG_PHYS_64BIT 170 #define CONFIG_SYS_DCSRBAR 0xf0000000 171 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 172 #endif 173 174 /* EEPROM */ 175 #define CONFIG_ID_EEPROM 176 #define CONFIG_SYS_I2C_EEPROM_NXID 177 #define CONFIG_SYS_EEPROM_BUS_NUM 0 178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 180 181 /* 182 * DDR Setup 183 */ 184 #define CONFIG_VERY_BIG_RAM 185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 186 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 187 188 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 189 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 190 191 #define CONFIG_DDR_SPD 192 #define CONFIG_FSL_DDR3 193 194 #define CONFIG_SYS_SPD_BUS_NUM 0 195 #define SPD_EEPROM_ADDRESS 0x52 196 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 197 198 /* 199 * Local Bus Definitions 200 */ 201 202 /* Set the local bus clock 1/8 of platform clock */ 203 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 204 205 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ 206 #ifdef CONFIG_PHYS_64BIT 207 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 208 #else 209 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 210 #endif 211 212 #define CONFIG_SYS_FLASH_BR_PRELIM \ 213 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 214 #define CONFIG_SYS_FLASH_OR_PRELIM \ 215 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 216 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 217 218 #define CONFIG_FSL_CPLD 219 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 220 #ifdef CONFIG_PHYS_64BIT 221 #define CPLD_BASE_PHYS 0xfffdf0000ull 222 #else 223 #define CPLD_BASE_PHYS CPLD_BASE 224 #endif 225 226 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 227 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 228 229 #define PIXIS_LBMAP_SWITCH 7 230 #define PIXIS_LBMAP_MASK 0xf0 231 #define PIXIS_LBMAP_SHIFT 4 232 #define PIXIS_LBMAP_ALTBANK 0x40 233 234 #define CONFIG_SYS_FLASH_QUIET_TEST 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 241 242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 243 244 #if defined(CONFIG_RAMBOOT_PBL) 245 #define CONFIG_SYS_RAMBOOT 246 #endif 247 248 #define CONFIG_NAND_FSL_ELBC 249 /* Nand Flash */ 250 #ifdef CONFIG_NAND_FSL_ELBC 251 #define CONFIG_SYS_NAND_BASE 0xffa00000 252 #ifdef CONFIG_PHYS_64BIT 253 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 254 #else 255 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 256 #endif 257 258 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 259 #define CONFIG_SYS_MAX_NAND_DEVICE 1 260 #define CONFIG_MTD_NAND_VERIFY_WRITE 261 #define CONFIG_CMD_NAND 262 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 263 264 /* NAND flash config */ 265 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 266 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 267 | BR_PS_8 /* Port Size = 8 bit */ \ 268 | BR_MS_FCM /* MSEL = FCM */ \ 269 | BR_V) /* valid */ 270 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 271 | OR_FCM_PGS /* Large Page*/ \ 272 | OR_FCM_CSCT \ 273 | OR_FCM_CST \ 274 | OR_FCM_CHT \ 275 | OR_FCM_SCY_1 \ 276 | OR_FCM_TRLX \ 277 | OR_FCM_EHTR) 278 279 #ifdef CONFIG_NAND 280 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 281 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 282 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 283 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 284 #else 285 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 286 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 287 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 288 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 289 #endif 290 #else 291 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 292 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 293 #endif /* CONFIG_NAND_FSL_ELBC */ 294 295 #define CONFIG_SYS_FLASH_EMPTY_INFO 296 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 297 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 298 299 #define CONFIG_BOARD_EARLY_INIT_F 300 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 301 #define CONFIG_MISC_INIT_R 302 303 #define CONFIG_HWCONFIG 304 305 /* define to use L1 as initial stack */ 306 #define CONFIG_L1_INIT_RAM 307 #define CONFIG_SYS_INIT_RAM_LOCK 308 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 309 #ifdef CONFIG_PHYS_64BIT 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 312 /* The assembler doesn't like typecast */ 313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 314 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 315 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 316 #else 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 318 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 320 #endif 321 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 322 323 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 324 GENERATED_GBL_DATA_SIZE) 325 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 326 327 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 328 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 329 330 /* Serial Port - controlled on board with jumper J8 331 * open - index 2 332 * shorted - index 1 333 */ 334 #define CONFIG_CONS_INDEX 1 335 #define CONFIG_SYS_NS16550 336 #define CONFIG_SYS_NS16550_SERIAL 337 #define CONFIG_SYS_NS16550_REG_SIZE 1 338 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 339 340 #define CONFIG_SYS_BAUDRATE_TABLE \ 341 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 342 343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 345 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 346 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 347 348 /* Use the HUSH parser */ 349 #define CONFIG_SYS_HUSH_PARSER 350 351 /* pass open firmware flat tree */ 352 #define CONFIG_OF_LIBFDT 353 #define CONFIG_OF_BOARD_SETUP 354 #define CONFIG_OF_STDOUT_VIA_ALIAS 355 356 /* new uImage format support */ 357 #define CONFIG_FIT 358 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 359 360 /* I2C */ 361 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 362 #define CONFIG_HARD_I2C /* I2C with hardware support */ 363 #define CONFIG_I2C_MULTI_BUS 364 #define CONFIG_I2C_CMD_TREE 365 #define CONFIG_SYS_I2C_SPEED 400000 366 #define CONFIG_SYS_I2C_SLAVE 0x7F 367 #define CONFIG_SYS_I2C_OFFSET 0x118000 368 #define CONFIG_SYS_I2C2_OFFSET 0x118100 369 370 /* 371 * RapidIO 372 */ 373 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 374 #ifdef CONFIG_PHYS_64BIT 375 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 376 #else 377 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 378 #endif 379 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 380 381 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 382 #ifdef CONFIG_PHYS_64BIT 383 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 384 #else 385 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 386 #endif 387 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 388 389 /* 390 * for slave u-boot IMAGE instored in master memory space, 391 * PHYS must be aligned based on the SIZE 392 */ 393 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 394 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 395 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 396 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 397 /* 398 * for slave UCODE and ENV instored in master memory space, 399 * PHYS must be aligned based on the SIZE 400 */ 401 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 402 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 403 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 404 405 /* slave core release by master*/ 406 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 407 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 408 409 /* 410 * SRIO_PCIE_BOOT - SLAVE 411 */ 412 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 413 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 414 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 415 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 416 #endif 417 418 /* 419 * eSPI - Enhanced SPI 420 */ 421 #define CONFIG_FSL_ESPI 422 #define CONFIG_SPI_FLASH 423 #define CONFIG_SPI_FLASH_SPANSION 424 #define CONFIG_CMD_SF 425 #define CONFIG_SF_DEFAULT_SPEED 10000000 426 #define CONFIG_SF_DEFAULT_MODE 0 427 428 /* 429 * General PCI 430 * Memory space is mapped 1-1, but I/O space must start from 0. 431 */ 432 433 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 434 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 437 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 438 #else 439 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 441 #endif 442 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 443 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 444 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 447 #else 448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 449 #endif 450 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 451 452 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 453 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 454 #ifdef CONFIG_PHYS_64BIT 455 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 456 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 457 #else 458 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 459 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 460 #endif 461 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 462 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 463 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 466 #else 467 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 468 #endif 469 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 470 471 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 472 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 473 #ifdef CONFIG_PHYS_64BIT 474 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 475 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 476 #else 477 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 478 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 479 #endif 480 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 481 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 482 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 483 #ifdef CONFIG_PHYS_64BIT 484 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 485 #else 486 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 487 #endif 488 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 489 490 /* Qman/Bman */ 491 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 492 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 493 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 494 #ifdef CONFIG_PHYS_64BIT 495 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 496 #else 497 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 498 #endif 499 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 500 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 501 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 502 #ifdef CONFIG_PHYS_64BIT 503 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 504 #else 505 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 506 #endif 507 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 508 509 #define CONFIG_SYS_DPAA_FMAN 510 #define CONFIG_SYS_DPAA_PME 511 /* Default address of microcode for the Linux Fman driver */ 512 #if defined(CONFIG_SPIFLASH) 513 /* 514 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 515 * env, so we got 0x110000. 516 */ 517 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 518 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 519 #elif defined(CONFIG_SDCARD) 520 /* 521 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 522 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 523 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 524 */ 525 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 526 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 527 #elif defined(CONFIG_NAND) 528 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 529 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 530 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 531 /* 532 * Slave has no ucode locally, it can fetch this from remote. When implementing 533 * in two corenet boards, slave's ucode could be stored in master's memory 534 * space, the address can be mapped from slave TLB->slave LAW-> 535 * slave SRIO or PCIE outbound window->master inbound window-> 536 * master LAW->the ucode address in master's memory space. 537 */ 538 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 539 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 540 #else 541 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 542 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 543 #endif 544 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 545 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 546 547 #ifdef CONFIG_SYS_DPAA_FMAN 548 #define CONFIG_FMAN_ENET 549 #define CONFIG_PHYLIB_10G 550 #define CONFIG_PHY_VITESSE 551 #define CONFIG_PHY_TERANETICS 552 #endif 553 554 #ifdef CONFIG_PCI 555 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 556 #define CONFIG_E1000 557 558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 559 #define CONFIG_DOS_PARTITION 560 #endif /* CONFIG_PCI */ 561 562 /* SATA */ 563 #define CONFIG_FSL_SATA 564 #ifdef CONFIG_FSL_SATA 565 #define CONFIG_LIBATA 566 567 #define CONFIG_SYS_SATA_MAX_DEVICE 2 568 #define CONFIG_SATA1 569 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 570 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 571 #define CONFIG_SATA2 572 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 573 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 574 575 #define CONFIG_LBA48 576 #define CONFIG_CMD_SATA 577 #define CONFIG_DOS_PARTITION 578 #define CONFIG_CMD_EXT2 579 #endif 580 581 #ifdef CONFIG_FMAN_ENET 582 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 583 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 584 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 585 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 586 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 587 588 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 589 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 590 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 591 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 592 593 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 594 595 #define CONFIG_SYS_TBIPA_VALUE 8 596 #define CONFIG_MII /* MII PHY management */ 597 #define CONFIG_ETHPRIME "FM1@DTSEC1" 598 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 599 #endif 600 601 /* 602 * Environment 603 */ 604 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 605 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 606 607 /* 608 * Command line configuration. 609 */ 610 #include <config_cmd_default.h> 611 612 #define CONFIG_CMD_DHCP 613 #define CONFIG_CMD_ELF 614 #define CONFIG_CMD_ERRATA 615 #define CONFIG_CMD_GREPENV 616 #define CONFIG_CMD_IRQ 617 #define CONFIG_CMD_I2C 618 #define CONFIG_CMD_MII 619 #define CONFIG_CMD_PING 620 #define CONFIG_CMD_SETEXPR 621 622 #ifdef CONFIG_PCI 623 #define CONFIG_CMD_PCI 624 #define CONFIG_CMD_NET 625 #endif 626 627 /* 628 * USB 629 */ 630 #define CONFIG_HAS_FSL_DR_USB 631 #define CONFIG_HAS_FSL_MPH_USB 632 633 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 634 #define CONFIG_CMD_USB 635 #define CONFIG_USB_STORAGE 636 #define CONFIG_USB_EHCI 637 #define CONFIG_USB_EHCI_FSL 638 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 639 #endif 640 641 #define CONFIG_CMD_EXT2 642 643 #define CONFIG_MMC 644 645 #ifdef CONFIG_MMC 646 #define CONFIG_FSL_ESDHC 647 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 648 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 649 #define CONFIG_CMD_MMC 650 #define CONFIG_GENERIC_MMC 651 #define CONFIG_CMD_EXT2 652 #define CONFIG_CMD_FAT 653 #define CONFIG_DOS_PARTITION 654 #endif 655 656 /* 657 * Miscellaneous configurable options 658 */ 659 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 660 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 661 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 662 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 663 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 664 #ifdef CONFIG_CMD_KGDB 665 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 666 #else 667 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 668 #endif 669 /* Print Buffer Size */ 670 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 671 sizeof(CONFIG_SYS_PROMPT)+16) 672 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 673 /* Boot Argument Buffer Size */ 674 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 675 #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ 676 677 /* 678 * For booting Linux, the board info and command line data 679 * have to be in the first 64 MB of memory, since this is 680 * the maximum mapped by the Linux kernel during initialization. 681 */ 682 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 683 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 684 685 #ifdef CONFIG_CMD_KGDB 686 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 687 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 688 #endif 689 690 /* 691 * Environment Configuration 692 */ 693 #define CONFIG_ROOTPATH "/opt/nfsroot" 694 #define CONFIG_BOOTFILE "uImage" 695 #define CONFIG_UBOOTPATH u-boot.bin 696 697 /* default location for tftp and bootm */ 698 #define CONFIG_LOADADDR 1000000 699 700 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 701 702 #define CONFIG_BAUDRATE 115200 703 704 #define __USB_PHY_TYPE utmi 705 706 #define CONFIG_EXTRA_ENV_SETTINGS \ 707 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 708 "bank_intlv=cs0_cs1\0" \ 709 "netdev=eth0\0" \ 710 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 711 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 712 "tftpflash=tftpboot $loadaddr $uboot && " \ 713 "protect off $ubootaddr +$filesize && " \ 714 "erase $ubootaddr +$filesize && " \ 715 "cp.b $loadaddr $ubootaddr $filesize && " \ 716 "protect on $ubootaddr +$filesize && " \ 717 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 718 "consoledev=ttyS0\0" \ 719 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 720 "usb_dr_mode=host\0" \ 721 "ramdiskaddr=2000000\0" \ 722 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 723 "fdtaddr=c00000\0" \ 724 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 725 "bdev=sda3\0" \ 726 "c=ffe\0" 727 728 #define CONFIG_HDBOOT \ 729 "setenv bootargs root=/dev/$bdev rw " \ 730 "console=$consoledev,$baudrate $othbootargs;" \ 731 "tftp $loadaddr $bootfile;" \ 732 "tftp $fdtaddr $fdtfile;" \ 733 "bootm $loadaddr - $fdtaddr" 734 735 #define CONFIG_NFSBOOTCOMMAND \ 736 "setenv bootargs root=/dev/nfs rw " \ 737 "nfsroot=$serverip:$rootpath " \ 738 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 739 "console=$consoledev,$baudrate $othbootargs;" \ 740 "tftp $loadaddr $bootfile;" \ 741 "tftp $fdtaddr $fdtfile;" \ 742 "bootm $loadaddr - $fdtaddr" 743 744 #define CONFIG_RAMBOOTCOMMAND \ 745 "setenv bootargs root=/dev/ram rw " \ 746 "console=$consoledev,$baudrate $othbootargs;" \ 747 "tftp $ramdiskaddr $ramdiskfile;" \ 748 "tftp $loadaddr $bootfile;" \ 749 "tftp $fdtaddr $fdtfile;" \ 750 "bootm $loadaddr $ramdiskaddr $fdtaddr" 751 752 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 753 754 #ifdef CONFIG_SECURE_BOOT 755 #include <asm/fsl_secure_boot.h> 756 #endif 757 758 #endif /* __CONFIG_H */ 759