1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Authors: Roy Zang <tie-fei.zang@freescale.com> 5 * Chunhe Lan <Chunhe.Lan@freescale.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff80000 31 #endif 32 33 #ifndef CONFIG_SYS_MONITOR_BASE 34 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 35 #endif 36 37 #ifndef CONFIG_RESET_VECTOR_ADDRESS 38 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 39 #endif 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE /* BOOKE */ 43 #define CONFIG_E500 /* BOOKE e500 family */ 44 #define CONFIG_MPC85xx 45 #define CONFIG_P1023 46 #define CONFIG_MP /* support multiple processors */ 47 48 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 49 #define CONFIG_PCI /* Enable PCI/PCIE */ 50 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 51 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 52 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 53 #define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ 54 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 55 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 #define CONFIG_FSL_LAW /* Use common FSL init code */ 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_clock_freq(void); 61 #endif 62 63 #define CONFIG_SYS_CLK_FREQ 66666666 64 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 #define CONFIG_HWCONFIG 72 73 #define CONFIG_ENABLE_36BIT_PHYS 74 75 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 76 #define CONFIG_SYS_MEMTEST_END 0x02000000 77 78 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 79 80 /* Implement conversion of addresses in the LBC */ 81 #define CONFIG_SYS_LBC_LBCR 0x00000000 82 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 83 84 /* DDR Setup */ 85 #define CONFIG_VERY_BIG_RAM 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 90 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 91 92 #define CONFIG_DDR_SPD 93 #define CONFIG_FSL_DDR3 94 #define CONFIG_FSL_DDR_INTERACTIVE 95 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 96 #define CONFIG_SYS_SPD_BUS_NUM 0 97 #define SPD_EEPROM_ADDRESS 0x50 98 #define CONFIG_SYS_DDR_RAW_TIMING 99 100 /* 101 * Memory map 102 * 103 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 104 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 105 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 106 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 107 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 108 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 109 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 110 * 111 * Localbus non-cacheable 112 * 113 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 114 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 115 */ 116 117 /* 118 * Local Bus Definitions 119 */ 120 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 121 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 122 123 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 124 | BR_PS_16 | BR_V) 125 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 126 127 #define CONFIG_FLASH_CFI_DRIVER 128 #define CONFIG_SYS_FLASH_CFI 129 #define CONFIG_SYS_FLASH_EMPTY_INFO 130 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 131 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 132 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 133 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 134 135 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ 136 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 137 138 #define CONFIG_SYS_INIT_RAM_LOCK 139 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 140 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 141 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 142 GENERATED_GBL_DATA_SIZE) 143 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 144 145 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 146 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 147 148 #define CONFIG_SYS_NAND_BASE 0xffa00000 149 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 150 151 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 153 #define CONFIG_MTD_NAND_VERIFY_WRITE 154 #define CONFIG_CMD_NAND 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 157 158 /* NAND flash config */ 159 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 160 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 161 | BR_PS_8 /* Port Size = 8bit */ \ 162 | BR_MS_FCM /* MSEL = FCM */ \ 163 | BR_V) /* valid */ 164 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 165 | OR_FCM_PGS \ 166 | OR_FCM_CSCT \ 167 | OR_FCM_CST \ 168 | OR_FCM_CHT \ 169 | OR_FCM_SCY_1 \ 170 | OR_FCM_TRLX \ 171 | OR_FCM_EHTR) 172 173 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 174 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 175 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 176 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 177 178 /* Serial Port */ 179 #define CONFIG_CONS_INDEX 1 180 #undef CONFIG_SERIAL_SOFTWARE_FIFO 181 #define CONFIG_SYS_NS16550 182 #define CONFIG_SYS_NS16550_SERIAL 183 #define CONFIG_SYS_NS16550_REG_SIZE 1 184 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 185 186 #define CONFIG_SYS_BAUDRATE_TABLE \ 187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 188 189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 191 192 /* Use the HUSH parser */ 193 #define CONFIG_SYS_HUSH_PARSER 194 195 /* 196 * Pass open firmware flat tree 197 */ 198 #define CONFIG_OF_LIBFDT 199 #define CONFIG_OF_BOARD_SETUP 200 #define CONFIG_OF_STDOUT_VIA_ALIAS 201 202 /* new uImage format support */ 203 #define CONFIG_FIT 204 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 205 206 /* I2C */ 207 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 208 #define CONFIG_HARD_I2C /* I2C with hardware support */ 209 #define CONFIG_I2C_MULTI_BUS 210 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 211 #define CONFIG_SYS_I2C_SLAVE 0x7F 212 #define CONFIG_SYS_I2C_OFFSET 0x3000 213 #define CONFIG_SYS_I2C2_OFFSET 0x3100 214 215 /* 216 * I2C2 EEPROM 217 */ 218 #define CONFIG_ID_EEPROM 219 #ifdef CONFIG_ID_EEPROM 220 #define CONFIG_SYS_I2C_EEPROM_NXID 221 #endif 222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 224 #define CONFIG_SYS_EEPROM_BUS_NUM 0 225 226 #define CONFIG_CMD_I2C 227 228 /* 229 * General PCI 230 * Memory space is mapped 1-1, but I/O space must start from 0. 231 */ 232 233 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 234 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 235 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 236 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 237 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 238 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 239 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 240 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 241 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 242 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 243 244 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 245 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 246 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 247 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 248 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 249 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 250 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 251 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 252 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 253 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 254 255 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 256 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 257 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 258 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 259 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 260 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 261 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 262 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 263 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 264 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 265 266 #if defined(CONFIG_PCI) 267 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card */ 268 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 269 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 270 #endif /* CONFIG_PCI */ 271 272 /* 273 * Environment 274 */ 275 #define CONFIG_ENV_OVERWRITE 276 277 #define CONFIG_ENV_IS_IN_FLASH 278 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 279 #define CONFIG_ENV_ADDR 0xfff80000 280 #else 281 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 282 #endif 283 #define CONFIG_ENV_SIZE 0x2000 284 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 285 286 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 287 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 288 289 /* 290 * Command line configuration. 291 */ 292 #include <config_cmd_default.h> 293 294 #define CONFIG_CMD_IRQ 295 #define CONFIG_CMD_PING 296 #define CONFIG_CMD_MII 297 #define CONFIG_CMD_SETEXPR 298 #define CONFIG_CMD_REGINFO 299 300 #if defined(CONFIG_PCI) 301 #define CONFIG_CMD_PCI 302 #define CONFIG_CMD_NET 303 #endif 304 305 /* 306 * USB 307 */ 308 #define CONFIG_HAS_FSL_DR_USB 309 #ifdef CONFIG_HAS_FSL_DR_USB 310 #define CONFIG_USB_EHCI 311 312 #ifdef CONFIG_USB_EHCI 313 #define CONFIG_CMD_USB 314 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 315 #define CONFIG_USB_EHCI_FSL 316 #define CONFIG_USB_STORAGE 317 #define CONFIG_CMD_FAT 318 #define CONFIG_CMD_EXT2 319 #define CONFIG_CMD_FAT 320 #define CONFIG_DOS_PARTITION 321 #endif 322 #endif 323 324 /* 325 * Miscellaneous configurable options 326 */ 327 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 328 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 329 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 330 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 331 #if defined(CONFIG_CMD_KGDB) 332 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 333 #else 334 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 335 #endif 336 /* Print Buffer Size */ 337 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 338 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 339 /* Boot Argument Buffer Size */ 340 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 341 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 342 343 /* 344 * For booting Linux, the board info and command line data 345 * have to be in the first 64 MB of memory, since this is 346 * the maximum mapped by the Linux kernel during initialization. 347 */ 348 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 349 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 350 351 /* 352 * Environment Configuration 353 */ 354 #define CONFIG_BOOTFILE "uImage" 355 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 356 357 /* default location for tftp and bootm */ 358 #define CONFIG_LOADADDR 1000000 359 360 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 361 362 #define CONFIG_BAUDRATE 115200 363 364 /* Qman/Bman */ 365 #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ 366 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 367 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 368 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 369 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 370 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 371 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 372 373 /* For FM */ 374 #define CONFIG_SYS_DPAA_FMAN 375 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 376 377 #ifdef CONFIG_SYS_DPAA_FMAN 378 #define CONFIG_FMAN_ENET 379 #define CONFIG_PHY_ATHEROS 380 #endif 381 382 /* Default address of microcode for the Linux Fman driver */ 383 /* QE microcode/firmware address */ 384 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 385 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000 386 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 387 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 388 389 #ifdef CONFIG_FMAN_ENET 390 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 391 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 392 393 #define CONFIG_SYS_TBIPA_VALUE 8 394 #define CONFIG_MII /* MII PHY management */ 395 #define CONFIG_ETHPRIME "FM1@DTSEC1" 396 #endif 397 398 #define CONFIG_EXTRA_ENV_SETTINGS \ 399 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 400 401 #endif /* __CONFIG_H */ 402