1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * Authors: Roy Zang <tie-fei.zang@freescale.com> 6 * Chunhe Lan <Chunhe.Lan@freescale.com> 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #ifndef CONFIG_SYS_MONITOR_BASE 13 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 14 #endif 15 16 #ifndef CONFIG_RESET_VECTOR_ADDRESS 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 18 #endif 19 20 /* High Level Configuration Options */ 21 22 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 23 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 24 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 25 #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ 26 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 27 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 28 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 29 30 #ifndef __ASSEMBLY__ 31 extern unsigned long get_clock_freq(void); 32 #endif 33 34 #define CONFIG_SYS_CLK_FREQ 66666666 35 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 36 37 /* 38 * These can be toggled for performance analysis, otherwise use default. 39 */ 40 #define CONFIG_L2_CACHE /* toggle L2 cache */ 41 #define CONFIG_BTB /* toggle branch predition */ 42 #define CONFIG_HWCONFIG 43 44 #define CONFIG_ENABLE_36BIT_PHYS 45 46 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 47 #define CONFIG_SYS_MEMTEST_END 0x02000000 48 49 /* Implement conversion of addresses in the LBC */ 50 #define CONFIG_SYS_LBC_LBCR 0x00000000 51 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 52 53 /* DDR Setup */ 54 #define CONFIG_VERY_BIG_RAM 55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 57 58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 59 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 60 61 #define CONFIG_DDR_SPD 62 #define CONFIG_FSL_DDR_INTERACTIVE 63 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 64 #define CONFIG_SYS_SPD_BUS_NUM 0 65 #define SPD_EEPROM_ADDRESS 0x50 66 #define CONFIG_SYS_DDR_RAW_TIMING 67 68 /* 69 * Memory map 70 * 71 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 72 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 73 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 74 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 75 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 76 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 77 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 78 * 79 * Localbus non-cacheable 80 * 81 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 82 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 83 */ 84 85 /* 86 * Local Bus Definitions 87 */ 88 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 89 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 90 91 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 92 | BR_PS_16 | BR_V) 93 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 94 95 #define CONFIG_SYS_FLASH_EMPTY_INFO 96 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 97 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 98 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 99 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 100 101 #define CONFIG_SYS_INIT_RAM_LOCK 102 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 103 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 104 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 105 GENERATED_GBL_DATA_SIZE) 106 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 107 108 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ 109 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 110 111 #define CONFIG_SYS_NAND_BASE 0xffa00000 112 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 113 114 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 115 #define CONFIG_SYS_MAX_NAND_DEVICE 1 116 #define CONFIG_NAND_FSL_ELBC 117 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 118 119 /* NAND flash config */ 120 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 121 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 122 | BR_PS_8 /* Port Size = 8bit */ \ 123 | BR_MS_FCM /* MSEL = FCM */ \ 124 | BR_V) /* valid */ 125 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 126 | OR_FCM_PGS \ 127 | OR_FCM_CSCT \ 128 | OR_FCM_CST \ 129 | OR_FCM_CHT \ 130 | OR_FCM_SCY_1 \ 131 | OR_FCM_TRLX \ 132 | OR_FCM_EHTR) 133 134 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 135 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 136 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 137 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 138 139 /* Serial Port */ 140 #undef CONFIG_SERIAL_SOFTWARE_FIFO 141 #define CONFIG_SYS_NS16550_SERIAL 142 #define CONFIG_SYS_NS16550_REG_SIZE 1 143 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 144 145 #define CONFIG_SYS_BAUDRATE_TABLE \ 146 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 147 148 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 149 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 150 151 /* I2C */ 152 #define CONFIG_SYS_I2C 153 #define CONFIG_SYS_I2C_FSL 154 #define CONFIG_SYS_FSL_I2C_SPEED 400000 155 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 156 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 157 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 158 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 159 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 160 161 /* 162 * I2C2 EEPROM 163 */ 164 #define CONFIG_ID_EEPROM 165 #ifdef CONFIG_ID_EEPROM 166 #define CONFIG_SYS_I2C_EEPROM_NXID 167 #endif 168 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 169 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 170 #define CONFIG_SYS_EEPROM_BUS_NUM 0 171 172 /* 173 * General PCI 174 * Memory space is mapped 1-1, but I/O space must start from 0. 175 */ 176 177 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 178 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 179 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 180 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 181 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 182 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 183 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 184 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 185 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 186 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 187 188 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 189 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 190 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 191 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 192 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 193 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 194 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 195 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 196 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 197 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 198 199 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 200 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 201 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 202 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 203 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 204 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 206 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 207 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 208 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 209 210 #if defined(CONFIG_PCI) 211 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 212 #endif /* CONFIG_PCI */ 213 214 /* 215 * Environment 216 */ 217 #define CONFIG_ENV_OVERWRITE 218 219 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 220 #define CONFIG_ENV_SIZE 0x2000 221 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 222 223 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 224 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 225 226 /* 227 * USB 228 */ 229 #define CONFIG_HAS_FSL_DR_USB 230 #ifdef CONFIG_HAS_FSL_DR_USB 231 #ifdef CONFIG_USB_EHCI_HCD 232 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 233 #define CONFIG_USB_EHCI_FSL 234 #endif 235 #endif 236 237 /* 238 * Miscellaneous configurable options 239 */ 240 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 241 242 /* 243 * For booting Linux, the board info and command line data 244 * have to be in the first 64 MB of memory, since this is 245 * the maximum mapped by the Linux kernel during initialization. 246 */ 247 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 248 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 249 250 /* 251 * Environment Configuration 252 */ 253 #define CONFIG_BOOTFILE "uImage" 254 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 255 256 /* default location for tftp and bootm */ 257 #define CONFIG_LOADADDR 1000000 258 259 /* Qman/Bman */ 260 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 261 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 262 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 263 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 264 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 265 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 266 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 267 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 268 CONFIG_SYS_QMAN_CENA_SIZE) 269 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 270 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 271 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 272 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 273 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 274 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 275 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 276 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 277 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 278 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 279 CONFIG_SYS_BMAN_CENA_SIZE) 280 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 281 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 282 283 /* For FM */ 284 #define CONFIG_SYS_DPAA_FMAN 285 286 #ifdef CONFIG_SYS_DPAA_FMAN 287 #define CONFIG_FMAN_ENET 288 #define CONFIG_PHY_ATHEROS 289 #endif 290 291 /* Default address of microcode for the Linux Fman driver */ 292 /* QE microcode/firmware address */ 293 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 294 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 295 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 296 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 297 298 #ifdef CONFIG_FMAN_ENET 299 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 300 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 301 302 #define CONFIG_SYS_TBIPA_VALUE 8 303 #define CONFIG_ETHPRIME "FM1@DTSEC1" 304 #endif 305 306 #define CONFIG_EXTRA_ENV_SETTINGS \ 307 "netdev=eth0\0" \ 308 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 309 "loadaddr=1000000\0" \ 310 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 311 "tftpflash=tftpboot $loadaddr $uboot; " \ 312 "protect off $ubootaddr +$filesize; " \ 313 "erase $ubootaddr +$filesize; " \ 314 "cp.b $loadaddr $ubootaddr $filesize; " \ 315 "protect on $ubootaddr +$filesize; " \ 316 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 317 "consoledev=ttyS0\0" \ 318 "ramdiskaddr=2000000\0" \ 319 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 320 "fdtaddr=1e00000\0" \ 321 "fdtfile=p1023rdb.dtb\0" \ 322 "othbootargs=ramdisk_size=600000\0" \ 323 "bdev=sda1\0" \ 324 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 325 326 #define CONFIG_HDBOOT \ 327 "setenv bootargs root=/dev/$bdev rw " \ 328 "console=$consoledev,$baudrate $othbootargs;" \ 329 "tftp $loadaddr $bootfile;" \ 330 "tftp $fdtaddr $fdtfile;" \ 331 "bootm $loadaddr - $fdtaddr" 332 333 #define CONFIG_NFSBOOTCOMMAND \ 334 "setenv bootargs root=/dev/nfs rw " \ 335 "nfsroot=$serverip:$rootpath " \ 336 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 337 "console=$consoledev,$baudrate $othbootargs;" \ 338 "tftp $loadaddr $bootfile;" \ 339 "tftp $fdtaddr $fdtfile;" \ 340 "bootm $loadaddr - $fdtaddr" 341 342 #define CONFIG_RAMBOOTCOMMAND \ 343 "setenv bootargs root=/dev/ram rw " \ 344 "console=$consoledev,$baudrate $othbootargs;" \ 345 "tftp $ramdiskaddr $ramdiskfile;" \ 346 "tftp $loadaddr $bootfile;" \ 347 "tftp $fdtaddr $fdtfile;" \ 348 "bootm $loadaddr $ramdiskaddr $fdtaddr" 349 350 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 351 352 #endif /* __CONFIG_H */ 353