1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * Authors: Roy Zang <tie-fei.zang@freescale.com> 6 * Chunhe Lan <Chunhe.Lan@freescale.com> 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #ifndef CONFIG_SYS_MONITOR_BASE 13 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 14 #endif 15 16 #ifndef CONFIG_RESET_VECTOR_ADDRESS 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 18 #endif 19 20 /* High Level Configuration Options */ 21 22 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 23 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 24 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 25 #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ 26 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 27 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 28 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 29 30 #ifndef __ASSEMBLY__ 31 extern unsigned long get_clock_freq(void); 32 #endif 33 34 #define CONFIG_SYS_CLK_FREQ 66666666 35 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 36 37 /* 38 * These can be toggled for performance analysis, otherwise use default. 39 */ 40 #define CONFIG_L2_CACHE /* toggle L2 cache */ 41 #define CONFIG_BTB /* toggle branch predition */ 42 #define CONFIG_HWCONFIG 43 44 #define CONFIG_ENABLE_36BIT_PHYS 45 46 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 47 #define CONFIG_SYS_MEMTEST_END 0x02000000 48 49 /* Implement conversion of addresses in the LBC */ 50 #define CONFIG_SYS_LBC_LBCR 0x00000000 51 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 52 53 /* DDR Setup */ 54 #define CONFIG_VERY_BIG_RAM 55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 57 58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 59 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 60 61 #define CONFIG_DDR_SPD 62 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 63 #define CONFIG_SYS_SPD_BUS_NUM 0 64 #define SPD_EEPROM_ADDRESS 0x50 65 #define CONFIG_SYS_DDR_RAW_TIMING 66 67 /* 68 * Memory map 69 * 70 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 71 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 72 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 73 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 74 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 75 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 76 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 77 * 78 * Localbus non-cacheable 79 * 80 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 81 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 82 */ 83 84 /* 85 * Local Bus Definitions 86 */ 87 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 88 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 89 90 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 91 | BR_PS_16 | BR_V) 92 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 93 94 #define CONFIG_SYS_FLASH_EMPTY_INFO 95 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 96 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 97 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 98 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 99 100 #define CONFIG_SYS_INIT_RAM_LOCK 101 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 102 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 103 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 104 GENERATED_GBL_DATA_SIZE) 105 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 106 107 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ 108 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 109 110 #define CONFIG_SYS_NAND_BASE 0xffa00000 111 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 112 113 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 114 #define CONFIG_SYS_MAX_NAND_DEVICE 1 115 #define CONFIG_NAND_FSL_ELBC 116 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 117 118 /* NAND flash config */ 119 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 120 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 121 | BR_PS_8 /* Port Size = 8bit */ \ 122 | BR_MS_FCM /* MSEL = FCM */ \ 123 | BR_V) /* valid */ 124 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 125 | OR_FCM_PGS \ 126 | OR_FCM_CSCT \ 127 | OR_FCM_CST \ 128 | OR_FCM_CHT \ 129 | OR_FCM_SCY_1 \ 130 | OR_FCM_TRLX \ 131 | OR_FCM_EHTR) 132 133 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 134 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 135 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 136 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 137 138 /* Serial Port */ 139 #undef CONFIG_SERIAL_SOFTWARE_FIFO 140 #define CONFIG_SYS_NS16550_SERIAL 141 #define CONFIG_SYS_NS16550_REG_SIZE 1 142 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 143 144 #define CONFIG_SYS_BAUDRATE_TABLE \ 145 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 146 147 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 148 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 149 150 /* I2C */ 151 #define CONFIG_SYS_I2C 152 #define CONFIG_SYS_I2C_FSL 153 #define CONFIG_SYS_FSL_I2C_SPEED 400000 154 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 155 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 156 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 157 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 158 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 159 160 /* 161 * I2C2 EEPROM 162 */ 163 #define CONFIG_ID_EEPROM 164 #ifdef CONFIG_ID_EEPROM 165 #define CONFIG_SYS_I2C_EEPROM_NXID 166 #endif 167 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 168 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 169 #define CONFIG_SYS_EEPROM_BUS_NUM 0 170 171 /* 172 * General PCI 173 * Memory space is mapped 1-1, but I/O space must start from 0. 174 */ 175 176 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 177 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 178 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 179 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 180 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 181 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 182 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 183 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 184 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 185 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 186 187 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 188 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 189 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 190 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 191 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 192 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 193 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 194 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 195 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 196 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 197 198 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 199 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 200 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 201 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 202 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 203 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 204 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 205 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 206 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 207 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 208 209 #if defined(CONFIG_PCI) 210 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 211 #endif /* CONFIG_PCI */ 212 213 /* 214 * Environment 215 */ 216 #define CONFIG_ENV_OVERWRITE 217 218 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 219 #define CONFIG_ENV_SIZE 0x2000 220 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 221 222 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 223 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 224 225 /* 226 * USB 227 */ 228 #define CONFIG_HAS_FSL_DR_USB 229 #ifdef CONFIG_HAS_FSL_DR_USB 230 #ifdef CONFIG_USB_EHCI_HCD 231 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 232 #define CONFIG_USB_EHCI_FSL 233 #endif 234 #endif 235 236 /* 237 * Miscellaneous configurable options 238 */ 239 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 240 241 /* 242 * For booting Linux, the board info and command line data 243 * have to be in the first 64 MB of memory, since this is 244 * the maximum mapped by the Linux kernel during initialization. 245 */ 246 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 247 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 248 249 /* 250 * Environment Configuration 251 */ 252 #define CONFIG_BOOTFILE "uImage" 253 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 254 255 /* default location for tftp and bootm */ 256 #define CONFIG_LOADADDR 1000000 257 258 /* Qman/Bman */ 259 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 260 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 261 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 262 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 263 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 264 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 265 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 266 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 267 CONFIG_SYS_QMAN_CENA_SIZE) 268 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 269 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 270 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 271 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 272 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 273 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 274 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 275 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 276 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 277 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 278 CONFIG_SYS_BMAN_CENA_SIZE) 279 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 280 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 281 282 /* For FM */ 283 #define CONFIG_SYS_DPAA_FMAN 284 285 #ifdef CONFIG_SYS_DPAA_FMAN 286 #define CONFIG_FMAN_ENET 287 #define CONFIG_PHY_ATHEROS 288 #endif 289 290 /* Default address of microcode for the Linux Fman driver */ 291 /* QE microcode/firmware address */ 292 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 293 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 294 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 295 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 296 297 #ifdef CONFIG_FMAN_ENET 298 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 299 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 300 301 #define CONFIG_SYS_TBIPA_VALUE 8 302 #define CONFIG_ETHPRIME "FM1@DTSEC1" 303 #endif 304 305 #define CONFIG_EXTRA_ENV_SETTINGS \ 306 "netdev=eth0\0" \ 307 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 308 "loadaddr=1000000\0" \ 309 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 310 "tftpflash=tftpboot $loadaddr $uboot; " \ 311 "protect off $ubootaddr +$filesize; " \ 312 "erase $ubootaddr +$filesize; " \ 313 "cp.b $loadaddr $ubootaddr $filesize; " \ 314 "protect on $ubootaddr +$filesize; " \ 315 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 316 "consoledev=ttyS0\0" \ 317 "ramdiskaddr=2000000\0" \ 318 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 319 "fdtaddr=1e00000\0" \ 320 "fdtfile=p1023rdb.dtb\0" \ 321 "othbootargs=ramdisk_size=600000\0" \ 322 "bdev=sda1\0" \ 323 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 324 325 #define CONFIG_HDBOOT \ 326 "setenv bootargs root=/dev/$bdev rw " \ 327 "console=$consoledev,$baudrate $othbootargs;" \ 328 "tftp $loadaddr $bootfile;" \ 329 "tftp $fdtaddr $fdtfile;" \ 330 "bootm $loadaddr - $fdtaddr" 331 332 #define CONFIG_NFSBOOTCOMMAND \ 333 "setenv bootargs root=/dev/nfs rw " \ 334 "nfsroot=$serverip:$rootpath " \ 335 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 336 "console=$consoledev,$baudrate $othbootargs;" \ 337 "tftp $loadaddr $bootfile;" \ 338 "tftp $fdtaddr $fdtfile;" \ 339 "bootm $loadaddr - $fdtaddr" 340 341 #define CONFIG_RAMBOOTCOMMAND \ 342 "setenv bootargs root=/dev/ram rw " \ 343 "console=$consoledev,$baudrate $othbootargs;" \ 344 "tftp $ramdiskaddr $ramdiskfile;" \ 345 "tftp $loadaddr $bootfile;" \ 346 "tftp $fdtaddr $fdtfile;" \ 347 "bootm $loadaddr $ramdiskaddr $fdtaddr" 348 349 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 350 351 #endif /* __CONFIG_H */ 352