1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Authors: Roy Zang <tie-fei.zang@freescale.com> 5 * Chunhe Lan <Chunhe.Lan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #ifndef CONFIG_SYS_TEXT_BASE 16 #define CONFIG_SYS_TEXT_BASE 0xeff40000 17 #endif 18 19 #ifndef CONFIG_SYS_MONITOR_BASE 20 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 21 #endif 22 23 #ifndef CONFIG_RESET_VECTOR_ADDRESS 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 25 #endif 26 27 /* High Level Configuration Options */ 28 #define CONFIG_BOOKE /* BOOKE */ 29 #define CONFIG_E500 /* BOOKE e500 family */ 30 #define CONFIG_P1023 31 #define CONFIG_MP /* support multiple processors */ 32 33 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 34 #define CONFIG_PCI /* Enable PCI/PCIE */ 35 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 36 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 37 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 38 #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ 39 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 40 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 41 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 42 #define CONFIG_FSL_LAW /* Use common FSL init code */ 43 44 #ifndef __ASSEMBLY__ 45 extern unsigned long get_clock_freq(void); 46 #endif 47 48 #define CONFIG_SYS_CLK_FREQ 66666666 49 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 50 51 /* 52 * These can be toggled for performance analysis, otherwise use default. 53 */ 54 #define CONFIG_L2_CACHE /* toggle L2 cache */ 55 #define CONFIG_BTB /* toggle branch predition */ 56 #define CONFIG_HWCONFIG 57 58 #define CONFIG_ENABLE_36BIT_PHYS 59 60 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 61 #define CONFIG_SYS_MEMTEST_END 0x02000000 62 63 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 64 65 /* Implement conversion of addresses in the LBC */ 66 #define CONFIG_SYS_LBC_LBCR 0x00000000 67 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 68 69 /* DDR Setup */ 70 #define CONFIG_VERY_BIG_RAM 71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 73 74 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 75 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 76 77 #define CONFIG_DDR_SPD 78 #define CONFIG_SYS_FSL_DDR3 79 #define CONFIG_FSL_DDR_INTERACTIVE 80 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 81 #define CONFIG_SYS_SPD_BUS_NUM 0 82 #define SPD_EEPROM_ADDRESS 0x50 83 #define CONFIG_SYS_DDR_RAW_TIMING 84 85 /* 86 * Memory map 87 * 88 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 89 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 90 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 91 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 92 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 93 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 94 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 95 * 96 * Localbus non-cacheable 97 * 98 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 99 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 100 */ 101 102 /* 103 * Local Bus Definitions 104 */ 105 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 106 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 107 108 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 109 | BR_PS_16 | BR_V) 110 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 111 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_FLASH_CFI 114 #define CONFIG_SYS_FLASH_EMPTY_INFO 115 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 116 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 117 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 118 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 119 120 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ 121 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 122 123 #define CONFIG_SYS_INIT_RAM_LOCK 124 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 125 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 126 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 127 GENERATED_GBL_DATA_SIZE) 128 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 129 130 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ 131 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 132 133 #define CONFIG_SYS_NAND_BASE 0xffa00000 134 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 135 136 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 137 #define CONFIG_SYS_MAX_NAND_DEVICE 1 138 #define CONFIG_CMD_NAND 139 #define CONFIG_NAND_FSL_ELBC 140 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 141 142 /* NAND flash config */ 143 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 144 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 145 | BR_PS_8 /* Port Size = 8bit */ \ 146 | BR_MS_FCM /* MSEL = FCM */ \ 147 | BR_V) /* valid */ 148 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 149 | OR_FCM_PGS \ 150 | OR_FCM_CSCT \ 151 | OR_FCM_CST \ 152 | OR_FCM_CHT \ 153 | OR_FCM_SCY_1 \ 154 | OR_FCM_TRLX \ 155 | OR_FCM_EHTR) 156 157 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 158 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 159 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 160 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 161 162 /* Serial Port */ 163 #define CONFIG_CONS_INDEX 1 164 #undef CONFIG_SERIAL_SOFTWARE_FIFO 165 #define CONFIG_SYS_NS16550_SERIAL 166 #define CONFIG_SYS_NS16550_REG_SIZE 1 167 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 168 169 #define CONFIG_SYS_BAUDRATE_TABLE \ 170 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 171 172 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 173 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 174 175 /* I2C */ 176 #define CONFIG_SYS_I2C 177 #define CONFIG_SYS_I2C_FSL 178 #define CONFIG_SYS_FSL_I2C_SPEED 400000 179 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 180 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 181 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 182 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 183 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 184 185 /* 186 * I2C2 EEPROM 187 */ 188 #define CONFIG_ID_EEPROM 189 #ifdef CONFIG_ID_EEPROM 190 #define CONFIG_SYS_I2C_EEPROM_NXID 191 #endif 192 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 194 #define CONFIG_SYS_EEPROM_BUS_NUM 0 195 196 /* 197 * General PCI 198 * Memory space is mapped 1-1, but I/O space must start from 0. 199 */ 200 201 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 202 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 203 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 204 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 205 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 206 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 207 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 208 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 209 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 210 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 211 212 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 213 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 214 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 215 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 216 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 217 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 218 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 219 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 220 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 221 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 222 223 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 224 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 225 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 226 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 227 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 228 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 229 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 230 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 231 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 232 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 233 234 #if defined(CONFIG_PCI) 235 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 236 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 237 #endif /* CONFIG_PCI */ 238 239 /* 240 * Environment 241 */ 242 #define CONFIG_ENV_OVERWRITE 243 244 #define CONFIG_ENV_IS_IN_FLASH 245 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 246 #define CONFIG_ENV_SIZE 0x2000 247 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 248 249 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 250 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 251 252 /* 253 * Command line configuration. 254 */ 255 #define CONFIG_CMD_IRQ 256 #define CONFIG_CMD_REGINFO 257 258 #if defined(CONFIG_PCI) 259 #define CONFIG_CMD_PCI 260 #endif 261 262 /* 263 * USB 264 */ 265 #define CONFIG_HAS_FSL_DR_USB 266 #ifdef CONFIG_HAS_FSL_DR_USB 267 #define CONFIG_USB_EHCI 268 269 #ifdef CONFIG_USB_EHCI 270 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 271 #define CONFIG_USB_EHCI_FSL 272 #define CONFIG_DOS_PARTITION 273 #endif 274 #endif 275 276 /* 277 * Miscellaneous configurable options 278 */ 279 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 280 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 281 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 282 #if defined(CONFIG_CMD_KGDB) 283 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 284 #else 285 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 286 #endif 287 /* Print Buffer Size */ 288 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 289 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 290 /* Boot Argument Buffer Size */ 291 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 292 293 /* 294 * For booting Linux, the board info and command line data 295 * have to be in the first 64 MB of memory, since this is 296 * the maximum mapped by the Linux kernel during initialization. 297 */ 298 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 299 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 300 301 /* 302 * Environment Configuration 303 */ 304 #define CONFIG_BOOTFILE "uImage" 305 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 306 307 /* default location for tftp and bootm */ 308 #define CONFIG_LOADADDR 1000000 309 310 311 #define CONFIG_BAUDRATE 115200 312 313 /* Qman/Bman */ 314 #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ 315 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 316 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 317 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 318 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 319 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 320 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 321 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 322 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 323 CONFIG_SYS_QMAN_CENA_SIZE) 324 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 325 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 326 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 327 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 328 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 329 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 330 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 331 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 332 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 333 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 334 CONFIG_SYS_BMAN_CENA_SIZE) 335 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 336 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 337 338 /* For FM */ 339 #define CONFIG_SYS_DPAA_FMAN 340 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 341 342 #ifdef CONFIG_SYS_DPAA_FMAN 343 #define CONFIG_FMAN_ENET 344 #define CONFIG_PHY_ATHEROS 345 #endif 346 347 /* Default address of microcode for the Linux Fman driver */ 348 /* QE microcode/firmware address */ 349 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 350 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 351 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 352 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 353 354 #ifdef CONFIG_FMAN_ENET 355 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 356 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 357 358 #define CONFIG_SYS_TBIPA_VALUE 8 359 #define CONFIG_MII /* MII PHY management */ 360 #define CONFIG_ETHPRIME "FM1@DTSEC1" 361 #endif 362 363 #define CONFIG_EXTRA_ENV_SETTINGS \ 364 "netdev=eth0\0" \ 365 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 366 "loadaddr=1000000\0" \ 367 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 368 "tftpflash=tftpboot $loadaddr $uboot; " \ 369 "protect off $ubootaddr +$filesize; " \ 370 "erase $ubootaddr +$filesize; " \ 371 "cp.b $loadaddr $ubootaddr $filesize; " \ 372 "protect on $ubootaddr +$filesize; " \ 373 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 374 "consoledev=ttyS0\0" \ 375 "ramdiskaddr=2000000\0" \ 376 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 377 "fdtaddr=1e00000\0" \ 378 "fdtfile=p1023rdb.dtb\0" \ 379 "othbootargs=ramdisk_size=600000\0" \ 380 "bdev=sda1\0" \ 381 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 382 383 #define CONFIG_HDBOOT \ 384 "setenv bootargs root=/dev/$bdev rw " \ 385 "console=$consoledev,$baudrate $othbootargs;" \ 386 "tftp $loadaddr $bootfile;" \ 387 "tftp $fdtaddr $fdtfile;" \ 388 "bootm $loadaddr - $fdtaddr" 389 390 #define CONFIG_NFSBOOTCOMMAND \ 391 "setenv bootargs root=/dev/nfs rw " \ 392 "nfsroot=$serverip:$rootpath " \ 393 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 394 "console=$consoledev,$baudrate $othbootargs;" \ 395 "tftp $loadaddr $bootfile;" \ 396 "tftp $fdtaddr $fdtfile;" \ 397 "bootm $loadaddr - $fdtaddr" 398 399 #define CONFIG_RAMBOOTCOMMAND \ 400 "setenv bootargs root=/dev/ram rw " \ 401 "console=$consoledev,$baudrate $othbootargs;" \ 402 "tftp $ramdiskaddr $ramdiskfile;" \ 403 "tftp $loadaddr $bootfile;" \ 404 "tftp $fdtaddr $fdtfile;" \ 405 "bootm $loadaddr $ramdiskaddr $fdtaddr" 406 407 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 408 409 #endif /* __CONFIG_H */ 410