1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Authors: Roy Zang <tie-fei.zang@freescale.com> 5 * Chunhe Lan <Chunhe.Lan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifndef CONFIG_SYS_TEXT_BASE 14 #define CONFIG_SYS_TEXT_BASE 0xeff40000 15 #endif 16 17 #ifndef CONFIG_SYS_MONITOR_BASE 18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 19 #endif 20 21 #ifndef CONFIG_RESET_VECTOR_ADDRESS 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 23 #endif 24 25 /* High Level Configuration Options */ 26 #define CONFIG_MP /* support multiple processors */ 27 28 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 29 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 30 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 31 #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ 32 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 33 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 34 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 35 36 #ifndef __ASSEMBLY__ 37 extern unsigned long get_clock_freq(void); 38 #endif 39 40 #define CONFIG_SYS_CLK_FREQ 66666666 41 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 42 43 /* 44 * These can be toggled for performance analysis, otherwise use default. 45 */ 46 #define CONFIG_L2_CACHE /* toggle L2 cache */ 47 #define CONFIG_BTB /* toggle branch predition */ 48 #define CONFIG_HWCONFIG 49 50 #define CONFIG_ENABLE_36BIT_PHYS 51 52 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 53 #define CONFIG_SYS_MEMTEST_END 0x02000000 54 55 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 56 57 /* Implement conversion of addresses in the LBC */ 58 #define CONFIG_SYS_LBC_LBCR 0x00000000 59 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 60 61 /* DDR Setup */ 62 #define CONFIG_VERY_BIG_RAM 63 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 64 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 65 66 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 67 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 68 69 #define CONFIG_DDR_SPD 70 #define CONFIG_FSL_DDR_INTERACTIVE 71 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 72 #define CONFIG_SYS_SPD_BUS_NUM 0 73 #define SPD_EEPROM_ADDRESS 0x50 74 #define CONFIG_SYS_DDR_RAW_TIMING 75 76 /* 77 * Memory map 78 * 79 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 80 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 81 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 82 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 83 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 84 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 85 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 86 * 87 * Localbus non-cacheable 88 * 89 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 90 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 91 */ 92 93 /* 94 * Local Bus Definitions 95 */ 96 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 97 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 98 99 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 100 | BR_PS_16 | BR_V) 101 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 102 103 #define CONFIG_FLASH_CFI_DRIVER 104 #define CONFIG_SYS_FLASH_CFI 105 #define CONFIG_SYS_FLASH_EMPTY_INFO 106 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 107 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 108 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 109 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 110 111 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 112 113 #define CONFIG_SYS_INIT_RAM_LOCK 114 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 115 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 116 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 117 GENERATED_GBL_DATA_SIZE) 118 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 119 120 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ 121 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 122 123 #define CONFIG_SYS_NAND_BASE 0xffa00000 124 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 125 126 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 127 #define CONFIG_SYS_MAX_NAND_DEVICE 1 128 #define CONFIG_NAND_FSL_ELBC 129 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 130 131 /* NAND flash config */ 132 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 133 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 134 | BR_PS_8 /* Port Size = 8bit */ \ 135 | BR_MS_FCM /* MSEL = FCM */ \ 136 | BR_V) /* valid */ 137 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 138 | OR_FCM_PGS \ 139 | OR_FCM_CSCT \ 140 | OR_FCM_CST \ 141 | OR_FCM_CHT \ 142 | OR_FCM_SCY_1 \ 143 | OR_FCM_TRLX \ 144 | OR_FCM_EHTR) 145 146 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 147 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 148 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 149 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 150 151 /* Serial Port */ 152 #define CONFIG_CONS_INDEX 1 153 #undef CONFIG_SERIAL_SOFTWARE_FIFO 154 #define CONFIG_SYS_NS16550_SERIAL 155 #define CONFIG_SYS_NS16550_REG_SIZE 1 156 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 157 158 #define CONFIG_SYS_BAUDRATE_TABLE \ 159 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 160 161 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 162 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 163 164 /* I2C */ 165 #define CONFIG_SYS_I2C 166 #define CONFIG_SYS_I2C_FSL 167 #define CONFIG_SYS_FSL_I2C_SPEED 400000 168 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 169 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 170 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 171 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 172 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 173 174 /* 175 * I2C2 EEPROM 176 */ 177 #define CONFIG_ID_EEPROM 178 #ifdef CONFIG_ID_EEPROM 179 #define CONFIG_SYS_I2C_EEPROM_NXID 180 #endif 181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 183 #define CONFIG_SYS_EEPROM_BUS_NUM 0 184 185 /* 186 * General PCI 187 * Memory space is mapped 1-1, but I/O space must start from 0. 188 */ 189 190 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 191 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 192 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 193 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 194 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 195 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 196 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 197 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 198 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 199 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 200 201 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 202 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 203 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 204 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 205 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 206 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 207 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 208 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 209 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 210 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 211 212 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 213 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 214 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 215 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 216 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 217 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 218 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 219 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 220 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 221 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 222 223 #if defined(CONFIG_PCI) 224 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 225 #endif /* CONFIG_PCI */ 226 227 /* 228 * Environment 229 */ 230 #define CONFIG_ENV_OVERWRITE 231 232 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 233 #define CONFIG_ENV_SIZE 0x2000 234 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 235 236 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 237 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 238 239 /* 240 * Command line configuration. 241 */ 242 #define CONFIG_CMD_REGINFO 243 244 #if defined(CONFIG_PCI) 245 #define CONFIG_CMD_PCI 246 #endif 247 248 /* 249 * USB 250 */ 251 #define CONFIG_HAS_FSL_DR_USB 252 #ifdef CONFIG_HAS_FSL_DR_USB 253 #ifdef CONFIG_USB_EHCI_HCD 254 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 255 #define CONFIG_USB_EHCI_FSL 256 #endif 257 #endif 258 259 /* 260 * Miscellaneous configurable options 261 */ 262 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 263 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 264 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 265 #if defined(CONFIG_CMD_KGDB) 266 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 267 #else 268 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 269 #endif 270 /* Print Buffer Size */ 271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 272 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 273 /* Boot Argument Buffer Size */ 274 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 275 276 /* 277 * For booting Linux, the board info and command line data 278 * have to be in the first 64 MB of memory, since this is 279 * the maximum mapped by the Linux kernel during initialization. 280 */ 281 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 282 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 283 284 /* 285 * Environment Configuration 286 */ 287 #define CONFIG_BOOTFILE "uImage" 288 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 289 290 /* default location for tftp and bootm */ 291 #define CONFIG_LOADADDR 1000000 292 293 /* Qman/Bman */ 294 #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ 295 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 296 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 297 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 298 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 299 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 300 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 301 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 302 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 303 CONFIG_SYS_QMAN_CENA_SIZE) 304 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 305 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 306 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 307 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 308 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 309 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 310 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 311 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 312 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 313 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 314 CONFIG_SYS_BMAN_CENA_SIZE) 315 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 316 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 317 318 /* For FM */ 319 #define CONFIG_SYS_DPAA_FMAN 320 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 321 322 #ifdef CONFIG_SYS_DPAA_FMAN 323 #define CONFIG_FMAN_ENET 324 #define CONFIG_PHY_ATHEROS 325 #endif 326 327 /* Default address of microcode for the Linux Fman driver */ 328 /* QE microcode/firmware address */ 329 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 330 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 331 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 332 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 333 334 #ifdef CONFIG_FMAN_ENET 335 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 336 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 337 338 #define CONFIG_SYS_TBIPA_VALUE 8 339 #define CONFIG_MII /* MII PHY management */ 340 #define CONFIG_ETHPRIME "FM1@DTSEC1" 341 #endif 342 343 #define CONFIG_EXTRA_ENV_SETTINGS \ 344 "netdev=eth0\0" \ 345 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 346 "loadaddr=1000000\0" \ 347 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 348 "tftpflash=tftpboot $loadaddr $uboot; " \ 349 "protect off $ubootaddr +$filesize; " \ 350 "erase $ubootaddr +$filesize; " \ 351 "cp.b $loadaddr $ubootaddr $filesize; " \ 352 "protect on $ubootaddr +$filesize; " \ 353 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 354 "consoledev=ttyS0\0" \ 355 "ramdiskaddr=2000000\0" \ 356 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 357 "fdtaddr=1e00000\0" \ 358 "fdtfile=p1023rdb.dtb\0" \ 359 "othbootargs=ramdisk_size=600000\0" \ 360 "bdev=sda1\0" \ 361 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 362 363 #define CONFIG_HDBOOT \ 364 "setenv bootargs root=/dev/$bdev rw " \ 365 "console=$consoledev,$baudrate $othbootargs;" \ 366 "tftp $loadaddr $bootfile;" \ 367 "tftp $fdtaddr $fdtfile;" \ 368 "bootm $loadaddr - $fdtaddr" 369 370 #define CONFIG_NFSBOOTCOMMAND \ 371 "setenv bootargs root=/dev/nfs rw " \ 372 "nfsroot=$serverip:$rootpath " \ 373 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 374 "console=$consoledev,$baudrate $othbootargs;" \ 375 "tftp $loadaddr $bootfile;" \ 376 "tftp $fdtaddr $fdtfile;" \ 377 "bootm $loadaddr - $fdtaddr" 378 379 #define CONFIG_RAMBOOTCOMMAND \ 380 "setenv bootargs root=/dev/ram rw " \ 381 "console=$consoledev,$baudrate $othbootargs;" \ 382 "tftp $ramdiskaddr $ramdiskfile;" \ 383 "tftp $loadaddr $bootfile;" \ 384 "tftp $fdtaddr $fdtfile;" \ 385 "bootm $loadaddr $ramdiskaddr $fdtaddr" 386 387 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 388 389 #endif /* __CONFIG_H */ 390