1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Authors: Roy Zang <tie-fei.zang@freescale.com> 5 * Chunhe Lan <Chunhe.Lan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifndef CONFIG_SYS_TEXT_BASE 14 #define CONFIG_SYS_TEXT_BASE 0xeff80000 15 #endif 16 17 #ifndef CONFIG_SYS_MONITOR_BASE 18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 19 #endif 20 21 #ifndef CONFIG_RESET_VECTOR_ADDRESS 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 23 #endif 24 25 /* High Level Configuration Options */ 26 #define CONFIG_BOOKE /* BOOKE */ 27 #define CONFIG_E500 /* BOOKE e500 family */ 28 #define CONFIG_MPC85xx 29 #define CONFIG_P1023 30 #define CONFIG_MP /* support multiple processors */ 31 32 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 33 #define CONFIG_PCI /* Enable PCI/PCIE */ 34 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 35 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 36 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 37 #define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ 38 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 39 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 40 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 41 #define CONFIG_FSL_LAW /* Use common FSL init code */ 42 43 #ifndef __ASSEMBLY__ 44 extern unsigned long get_clock_freq(void); 45 #endif 46 47 #define CONFIG_SYS_CLK_FREQ 66666666 48 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 49 50 /* 51 * These can be toggled for performance analysis, otherwise use default. 52 */ 53 #define CONFIG_L2_CACHE /* toggle L2 cache */ 54 #define CONFIG_BTB /* toggle branch predition */ 55 #define CONFIG_HWCONFIG 56 57 #define CONFIG_ENABLE_36BIT_PHYS 58 59 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 60 #define CONFIG_SYS_MEMTEST_END 0x02000000 61 62 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 63 64 /* Implement conversion of addresses in the LBC */ 65 #define CONFIG_SYS_LBC_LBCR 0x00000000 66 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 67 68 /* DDR Setup */ 69 #define CONFIG_VERY_BIG_RAM 70 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 71 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 72 73 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 74 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 75 76 #define CONFIG_DDR_SPD 77 #define CONFIG_SYS_FSL_DDR3 78 #define CONFIG_FSL_DDR_INTERACTIVE 79 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 80 #define CONFIG_SYS_SPD_BUS_NUM 0 81 #define SPD_EEPROM_ADDRESS 0x50 82 #define CONFIG_SYS_DDR_RAW_TIMING 83 84 /* 85 * Memory map 86 * 87 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 88 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 89 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 90 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 91 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 92 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 93 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 94 * 95 * Localbus non-cacheable 96 * 97 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 98 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 99 */ 100 101 /* 102 * Local Bus Definitions 103 */ 104 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 105 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 106 107 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 108 | BR_PS_16 | BR_V) 109 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 110 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_SYS_FLASH_EMPTY_INFO 114 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 116 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 118 119 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ 120 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 121 122 #define CONFIG_SYS_INIT_RAM_LOCK 123 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 124 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 125 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 126 GENERATED_GBL_DATA_SIZE) 127 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 128 129 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 130 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 131 132 #define CONFIG_SYS_NAND_BASE 0xffa00000 133 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 134 135 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 137 #define CONFIG_MTD_NAND_VERIFY_WRITE 138 #define CONFIG_CMD_NAND 139 #define CONFIG_NAND_FSL_ELBC 140 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 141 142 /* NAND flash config */ 143 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 144 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 145 | BR_PS_8 /* Port Size = 8bit */ \ 146 | BR_MS_FCM /* MSEL = FCM */ \ 147 | BR_V) /* valid */ 148 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 149 | OR_FCM_PGS \ 150 | OR_FCM_CSCT \ 151 | OR_FCM_CST \ 152 | OR_FCM_CHT \ 153 | OR_FCM_SCY_1 \ 154 | OR_FCM_TRLX \ 155 | OR_FCM_EHTR) 156 157 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 158 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 159 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 160 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 161 162 /* Serial Port */ 163 #define CONFIG_CONS_INDEX 1 164 #undef CONFIG_SERIAL_SOFTWARE_FIFO 165 #define CONFIG_SYS_NS16550 166 #define CONFIG_SYS_NS16550_SERIAL 167 #define CONFIG_SYS_NS16550_REG_SIZE 1 168 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 169 170 #define CONFIG_SYS_BAUDRATE_TABLE \ 171 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 172 173 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 174 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 175 176 /* Use the HUSH parser */ 177 #define CONFIG_SYS_HUSH_PARSER 178 179 /* 180 * Pass open firmware flat tree 181 */ 182 #define CONFIG_OF_LIBFDT 183 #define CONFIG_OF_BOARD_SETUP 184 #define CONFIG_OF_STDOUT_VIA_ALIAS 185 186 /* new uImage format support */ 187 #define CONFIG_FIT 188 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 189 190 /* I2C */ 191 #define CONFIG_SYS_I2C 192 #define CONFIG_SYS_I2C_FSL 193 #define CONFIG_SYS_FSL_I2C_SPEED 400000 194 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 195 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 196 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 197 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 198 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 199 200 /* 201 * I2C2 EEPROM 202 */ 203 #define CONFIG_ID_EEPROM 204 #ifdef CONFIG_ID_EEPROM 205 #define CONFIG_SYS_I2C_EEPROM_NXID 206 #endif 207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 208 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 209 #define CONFIG_SYS_EEPROM_BUS_NUM 0 210 211 #define CONFIG_CMD_I2C 212 213 /* 214 * General PCI 215 * Memory space is mapped 1-1, but I/O space must start from 0. 216 */ 217 218 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 219 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 220 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 221 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 222 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 223 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 224 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 225 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 226 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 227 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 228 229 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 230 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 231 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 232 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 233 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 234 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 235 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 236 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 237 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 238 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 239 240 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 241 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 242 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 243 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 244 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 245 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 246 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 247 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 248 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 249 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 250 251 #if defined(CONFIG_PCI) 252 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card */ 253 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 254 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 255 #endif /* CONFIG_PCI */ 256 257 /* 258 * Environment 259 */ 260 #define CONFIG_ENV_OVERWRITE 261 262 #define CONFIG_ENV_IS_IN_FLASH 263 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 264 #define CONFIG_ENV_ADDR 0xfff80000 265 #else 266 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 267 #endif 268 #define CONFIG_ENV_SIZE 0x2000 269 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 270 271 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 272 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 273 274 /* 275 * Command line configuration. 276 */ 277 #include <config_cmd_default.h> 278 279 #define CONFIG_CMD_IRQ 280 #define CONFIG_CMD_PING 281 #define CONFIG_CMD_MII 282 #define CONFIG_CMD_SETEXPR 283 #define CONFIG_CMD_REGINFO 284 285 #if defined(CONFIG_PCI) 286 #define CONFIG_CMD_PCI 287 #define CONFIG_CMD_NET 288 #endif 289 290 /* 291 * USB 292 */ 293 #define CONFIG_HAS_FSL_DR_USB 294 #ifdef CONFIG_HAS_FSL_DR_USB 295 #define CONFIG_USB_EHCI 296 297 #ifdef CONFIG_USB_EHCI 298 #define CONFIG_CMD_USB 299 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 300 #define CONFIG_USB_EHCI_FSL 301 #define CONFIG_USB_STORAGE 302 #define CONFIG_CMD_FAT 303 #define CONFIG_CMD_EXT2 304 #define CONFIG_CMD_FAT 305 #define CONFIG_DOS_PARTITION 306 #endif 307 #endif 308 309 /* 310 * Miscellaneous configurable options 311 */ 312 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 313 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 314 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 315 #if defined(CONFIG_CMD_KGDB) 316 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 317 #else 318 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 319 #endif 320 /* Print Buffer Size */ 321 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 322 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 323 /* Boot Argument Buffer Size */ 324 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 325 326 /* 327 * For booting Linux, the board info and command line data 328 * have to be in the first 64 MB of memory, since this is 329 * the maximum mapped by the Linux kernel during initialization. 330 */ 331 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 332 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 333 334 /* 335 * Environment Configuration 336 */ 337 #define CONFIG_BOOTFILE "uImage" 338 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 339 340 /* default location for tftp and bootm */ 341 #define CONFIG_LOADADDR 1000000 342 343 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 344 345 #define CONFIG_BAUDRATE 115200 346 347 /* Qman/Bman */ 348 #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ 349 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 350 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 351 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 352 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 353 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 354 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 355 356 /* For FM */ 357 #define CONFIG_SYS_DPAA_FMAN 358 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 359 360 #ifdef CONFIG_SYS_DPAA_FMAN 361 #define CONFIG_FMAN_ENET 362 #define CONFIG_PHY_ATHEROS 363 #endif 364 365 /* Default address of microcode for the Linux Fman driver */ 366 /* QE microcode/firmware address */ 367 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 368 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000 369 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 370 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 371 372 #ifdef CONFIG_FMAN_ENET 373 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 374 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 375 376 #define CONFIG_SYS_TBIPA_VALUE 8 377 #define CONFIG_MII /* MII PHY management */ 378 #define CONFIG_ETHPRIME "FM1@DTSEC1" 379 #endif 380 381 #define CONFIG_EXTRA_ENV_SETTINGS \ 382 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 383 384 #endif /* __CONFIG_H */ 385