1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * Authors: Roy Zang <tie-fei.zang@freescale.com> 5 * Chunhe Lan <Chunhe.Lan@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifndef CONFIG_SYS_TEXT_BASE 14 #define CONFIG_SYS_TEXT_BASE 0xeff40000 15 #endif 16 17 #ifndef CONFIG_SYS_MONITOR_BASE 18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 19 #endif 20 21 #ifndef CONFIG_RESET_VECTOR_ADDRESS 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 23 #endif 24 25 /* High Level Configuration Options */ 26 #define CONFIG_BOOKE /* BOOKE */ 27 #define CONFIG_E500 /* BOOKE e500 family */ 28 #define CONFIG_P1023 29 #define CONFIG_MP /* support multiple processors */ 30 31 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 32 #define CONFIG_PCI /* Enable PCI/PCIE */ 33 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 34 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 35 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 36 #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ 37 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 38 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 39 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 40 #define CONFIG_FSL_LAW /* Use common FSL init code */ 41 42 #ifndef __ASSEMBLY__ 43 extern unsigned long get_clock_freq(void); 44 #endif 45 46 #define CONFIG_SYS_CLK_FREQ 66666666 47 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 48 49 /* 50 * These can be toggled for performance analysis, otherwise use default. 51 */ 52 #define CONFIG_L2_CACHE /* toggle L2 cache */ 53 #define CONFIG_BTB /* toggle branch predition */ 54 #define CONFIG_HWCONFIG 55 56 #define CONFIG_ENABLE_36BIT_PHYS 57 58 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 59 #define CONFIG_SYS_MEMTEST_END 0x02000000 60 61 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 62 63 /* Implement conversion of addresses in the LBC */ 64 #define CONFIG_SYS_LBC_LBCR 0x00000000 65 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 66 67 /* DDR Setup */ 68 #define CONFIG_VERY_BIG_RAM 69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 71 72 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 73 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 74 75 #define CONFIG_DDR_SPD 76 #define CONFIG_SYS_FSL_DDR3 77 #define CONFIG_FSL_DDR_INTERACTIVE 78 #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ 79 #define CONFIG_SYS_SPD_BUS_NUM 0 80 #define SPD_EEPROM_ADDRESS 0x50 81 #define CONFIG_SYS_DDR_RAW_TIMING 82 83 /* 84 * Memory map 85 * 86 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable 87 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 88 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 89 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 90 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable 91 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable 92 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 93 * 94 * Localbus non-cacheable 95 * 96 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable 97 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 98 */ 99 100 /* 101 * Local Bus Definitions 102 */ 103 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ 104 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 105 106 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 107 | BR_PS_16 | BR_V) 108 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 109 110 #define CONFIG_FLASH_CFI_DRIVER 111 #define CONFIG_SYS_FLASH_CFI 112 #define CONFIG_SYS_FLASH_EMPTY_INFO 113 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 114 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 115 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 116 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 117 118 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ 119 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 120 121 #define CONFIG_SYS_INIT_RAM_LOCK 122 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 123 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ 124 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 125 GENERATED_GBL_DATA_SIZE) 126 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 127 128 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ 129 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 130 131 #define CONFIG_SYS_NAND_BASE 0xffa00000 132 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 133 134 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 136 #define CONFIG_CMD_NAND 137 #define CONFIG_NAND_FSL_ELBC 138 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 139 140 /* NAND flash config */ 141 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 142 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 143 | BR_PS_8 /* Port Size = 8bit */ \ 144 | BR_MS_FCM /* MSEL = FCM */ \ 145 | BR_V) /* valid */ 146 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 147 | OR_FCM_PGS \ 148 | OR_FCM_CSCT \ 149 | OR_FCM_CST \ 150 | OR_FCM_CHT \ 151 | OR_FCM_SCY_1 \ 152 | OR_FCM_TRLX \ 153 | OR_FCM_EHTR) 154 155 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 156 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 157 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 158 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 159 160 /* Serial Port */ 161 #define CONFIG_CONS_INDEX 1 162 #undef CONFIG_SERIAL_SOFTWARE_FIFO 163 #define CONFIG_SYS_NS16550_SERIAL 164 #define CONFIG_SYS_NS16550_REG_SIZE 1 165 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 166 167 #define CONFIG_SYS_BAUDRATE_TABLE \ 168 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 169 170 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 171 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 172 173 /* I2C */ 174 #define CONFIG_SYS_I2C 175 #define CONFIG_SYS_I2C_FSL 176 #define CONFIG_SYS_FSL_I2C_SPEED 400000 177 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 178 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 179 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 180 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 181 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 182 183 /* 184 * I2C2 EEPROM 185 */ 186 #define CONFIG_ID_EEPROM 187 #ifdef CONFIG_ID_EEPROM 188 #define CONFIG_SYS_I2C_EEPROM_NXID 189 #endif 190 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 191 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 192 #define CONFIG_SYS_EEPROM_BUS_NUM 0 193 194 /* 195 * General PCI 196 * Memory space is mapped 1-1, but I/O space must start from 0. 197 */ 198 199 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 200 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 201 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 202 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 203 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 204 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 206 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 207 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 208 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 209 210 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 211 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 212 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 213 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 214 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 215 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 216 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 217 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 218 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 219 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 220 221 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 222 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 223 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 224 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 225 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 226 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 227 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 228 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 229 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 230 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 231 232 #if defined(CONFIG_PCI) 233 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 234 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 235 #endif /* CONFIG_PCI */ 236 237 /* 238 * Environment 239 */ 240 #define CONFIG_ENV_OVERWRITE 241 242 #define CONFIG_ENV_IS_IN_FLASH 243 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 244 #define CONFIG_ENV_SIZE 0x2000 245 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 246 247 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 248 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 249 250 /* 251 * Command line configuration. 252 */ 253 #define CONFIG_CMD_IRQ 254 #define CONFIG_CMD_REGINFO 255 256 #if defined(CONFIG_PCI) 257 #define CONFIG_CMD_PCI 258 #endif 259 260 /* 261 * USB 262 */ 263 #define CONFIG_HAS_FSL_DR_USB 264 #ifdef CONFIG_HAS_FSL_DR_USB 265 #define CONFIG_USB_EHCI 266 267 #ifdef CONFIG_USB_EHCI 268 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 269 #define CONFIG_USB_EHCI_FSL 270 #define CONFIG_DOS_PARTITION 271 #endif 272 #endif 273 274 /* 275 * Miscellaneous configurable options 276 */ 277 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 278 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 279 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 280 #if defined(CONFIG_CMD_KGDB) 281 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 282 #else 283 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 284 #endif 285 /* Print Buffer Size */ 286 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) 287 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 288 /* Boot Argument Buffer Size */ 289 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 290 291 /* 292 * For booting Linux, the board info and command line data 293 * have to be in the first 64 MB of memory, since this is 294 * the maximum mapped by the Linux kernel during initialization. 295 */ 296 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 297 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 298 299 /* 300 * Environment Configuration 301 */ 302 #define CONFIG_BOOTFILE "uImage" 303 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ 304 305 /* default location for tftp and bootm */ 306 #define CONFIG_LOADADDR 1000000 307 308 309 #define CONFIG_BAUDRATE 115200 310 311 /* Qman/Bman */ 312 #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ 313 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 314 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 315 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 316 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 317 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 318 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 319 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 320 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 321 CONFIG_SYS_QMAN_CENA_SIZE) 322 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 323 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 324 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 325 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 326 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 327 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 328 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 329 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 330 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 331 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 332 CONFIG_SYS_BMAN_CENA_SIZE) 333 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 334 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 335 336 /* For FM */ 337 #define CONFIG_SYS_DPAA_FMAN 338 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 339 340 #ifdef CONFIG_SYS_DPAA_FMAN 341 #define CONFIG_FMAN_ENET 342 #define CONFIG_PHY_ATHEROS 343 #endif 344 345 /* Default address of microcode for the Linux Fman driver */ 346 /* QE microcode/firmware address */ 347 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 348 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 349 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 350 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 351 352 #ifdef CONFIG_FMAN_ENET 353 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 354 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 355 356 #define CONFIG_SYS_TBIPA_VALUE 8 357 #define CONFIG_MII /* MII PHY management */ 358 #define CONFIG_ETHPRIME "FM1@DTSEC1" 359 #endif 360 361 #define CONFIG_EXTRA_ENV_SETTINGS \ 362 "netdev=eth0\0" \ 363 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 364 "loadaddr=1000000\0" \ 365 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 366 "tftpflash=tftpboot $loadaddr $uboot; " \ 367 "protect off $ubootaddr +$filesize; " \ 368 "erase $ubootaddr +$filesize; " \ 369 "cp.b $loadaddr $ubootaddr $filesize; " \ 370 "protect on $ubootaddr +$filesize; " \ 371 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 372 "consoledev=ttyS0\0" \ 373 "ramdiskaddr=2000000\0" \ 374 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 375 "fdtaddr=1e00000\0" \ 376 "fdtfile=p1023rdb.dtb\0" \ 377 "othbootargs=ramdisk_size=600000\0" \ 378 "bdev=sda1\0" \ 379 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 380 381 #define CONFIG_HDBOOT \ 382 "setenv bootargs root=/dev/$bdev rw " \ 383 "console=$consoledev,$baudrate $othbootargs;" \ 384 "tftp $loadaddr $bootfile;" \ 385 "tftp $fdtaddr $fdtfile;" \ 386 "bootm $loadaddr - $fdtaddr" 387 388 #define CONFIG_NFSBOOTCOMMAND \ 389 "setenv bootargs root=/dev/nfs rw " \ 390 "nfsroot=$serverip:$rootpath " \ 391 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 392 "console=$consoledev,$baudrate $othbootargs;" \ 393 "tftp $loadaddr $bootfile;" \ 394 "tftp $fdtaddr $fdtfile;" \ 395 "bootm $loadaddr - $fdtaddr" 396 397 #define CONFIG_RAMBOOTCOMMAND \ 398 "setenv bootargs root=/dev/ram rw " \ 399 "console=$consoledev,$baudrate $othbootargs;" \ 400 "tftp $ramdiskaddr $ramdiskfile;" \ 401 "tftp $loadaddr $bootfile;" \ 402 "tftp $fdtaddr $fdtfile;" \ 403 "bootm $loadaddr $ramdiskaddr $fdtaddr" 404 405 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 406 407 #endif /* __CONFIG_H */ 408