xref: /openbmc/u-boot/include/configs/P1023RDB.h (revision 103e83a1)
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
5  *	     Chunhe Lan <Chunhe.Lan@freescale.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #ifndef CONFIG_SYS_TEXT_BASE
14 #define CONFIG_SYS_TEXT_BASE	0xeff40000
15 #endif
16 
17 #ifndef CONFIG_SYS_MONITOR_BASE
18 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
19 #endif
20 
21 #ifndef CONFIG_RESET_VECTOR_ADDRESS
22 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
23 #endif
24 
25 /* High Level Configuration Options */
26 #define CONFIG_BOOKE		/* BOOKE */
27 #define CONFIG_E500		/* BOOKE e500 family */
28 #define CONFIG_MP		/* support multiple processors */
29 
30 #define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
31 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
32 #define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
33 #define CONFIG_PCIE2		/* PCIE controller 2 (slot 2) */
34 #define CONFIG_PCIE3		/* PCIE controller 3 (slot 3) */
35 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
36 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
37 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
38 
39 #ifndef __ASSEMBLY__
40 extern unsigned long get_clock_freq(void);
41 #endif
42 
43 #define CONFIG_SYS_CLK_FREQ	66666666
44 #define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
45 
46 /*
47  * These can be toggled for performance analysis, otherwise use default.
48  */
49 #define CONFIG_L2_CACHE			/* toggle L2 cache */
50 #define CONFIG_BTB			/* toggle branch predition */
51 #define CONFIG_HWCONFIG
52 
53 #define CONFIG_ENABLE_36BIT_PHYS
54 
55 #define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
56 #define CONFIG_SYS_MEMTEST_END		0x02000000
57 
58 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
59 
60 /* Implement conversion of addresses in the LBC */
61 #define CONFIG_SYS_LBC_LBCR		0x00000000
62 #define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
63 
64 /* DDR Setup */
65 #define CONFIG_VERY_BIG_RAM
66 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
67 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
68 
69 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
70 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
71 
72 #define CONFIG_DDR_SPD
73 #define CONFIG_SYS_FSL_DDR3
74 #define CONFIG_FSL_DDR_INTERACTIVE
75 #define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
76 #define CONFIG_SYS_SPD_BUS_NUM          0
77 #define SPD_EEPROM_ADDRESS              0x50
78 #define CONFIG_SYS_DDR_RAW_TIMING
79 
80 /*
81  * Memory map
82  *
83  * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
84  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
85  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
86  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
87  * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
88  * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
89  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
90  *
91  * Localbus non-cacheable
92  *
93  * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
94  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
95  */
96 
97 /*
98  * Local Bus Definitions
99  */
100 #define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
101 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
102 
103 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
104 				| BR_PS_16 | BR_V)
105 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
106 
107 #define CONFIG_FLASH_CFI_DRIVER
108 #define CONFIG_SYS_FLASH_CFI
109 #define CONFIG_SYS_FLASH_EMPTY_INFO
110 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
111 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
112 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
113 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
114 
115 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f function */
116 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
117 
118 #define CONFIG_SYS_INIT_RAM_LOCK
119 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
120 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
121 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
122 					GENERATED_GBL_DATA_SIZE)
123 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
124 
125 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)	  /* Reserve 512 kB for Mon */
126 #define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */
127 
128 #define CONFIG_SYS_NAND_BASE		0xffa00000
129 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
130 
131 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
132 #define CONFIG_SYS_MAX_NAND_DEVICE	1
133 #define CONFIG_CMD_NAND
134 #define CONFIG_NAND_FSL_ELBC
135 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
136 
137 /* NAND flash config */
138 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
139 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
140 				| BR_PS_8		/* Port Size = 8bit */ \
141 				| BR_MS_FCM		/* MSEL = FCM */ \
142 				| BR_V)			/* valid */
143 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
144 				| OR_FCM_PGS \
145 				| OR_FCM_CSCT \
146 				| OR_FCM_CST \
147 				| OR_FCM_CHT \
148 				| OR_FCM_SCY_1 \
149 				| OR_FCM_TRLX \
150 				| OR_FCM_EHTR)
151 
152 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
153 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
154 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
155 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
156 
157 /* Serial Port */
158 #define CONFIG_CONS_INDEX		1
159 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
160 #define CONFIG_SYS_NS16550_SERIAL
161 #define CONFIG_SYS_NS16550_REG_SIZE	1
162 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
163 
164 #define CONFIG_SYS_BAUDRATE_TABLE	\
165 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
166 
167 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
168 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
169 
170 /* I2C */
171 #define CONFIG_SYS_I2C
172 #define CONFIG_SYS_I2C_FSL
173 #define CONFIG_SYS_FSL_I2C_SPEED	400000
174 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
175 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
176 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
177 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
178 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
179 
180 /*
181  * I2C2 EEPROM
182  */
183 #define CONFIG_ID_EEPROM
184 #ifdef CONFIG_ID_EEPROM
185 #define CONFIG_SYS_I2C_EEPROM_NXID
186 #endif
187 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
189 #define CONFIG_SYS_EEPROM_BUS_NUM		0
190 
191 /*
192  * General PCI
193  * Memory space is mapped 1-1, but I/O space must start from 0.
194  */
195 
196 /* controller 3, Slot 1, tgtid 3, Base address b000 */
197 #define CONFIG_SYS_PCIE3_NAME		"Slot 3"
198 #define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
199 #define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
200 #define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
201 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
202 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
203 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
204 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
205 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
206 
207 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
208 #define CONFIG_SYS_PCIE2_NAME		"Slot 2"
209 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
210 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
211 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
212 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
213 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
214 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
215 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
216 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
217 
218 /* controller 1, Slot 2, tgtid 1, Base address a000 */
219 #define CONFIG_SYS_PCIE1_NAME		"Slot 1"
220 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
221 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
222 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
223 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
224 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
225 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
226 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
227 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
228 
229 #if defined(CONFIG_PCI)
230 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
231 #endif	/* CONFIG_PCI */
232 
233 /*
234  * Environment
235  */
236 #define CONFIG_ENV_OVERWRITE
237 
238 #define CONFIG_ENV_IS_IN_FLASH
239 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
240 #define CONFIG_ENV_SIZE		0x2000
241 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
242 
243 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
244 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
245 
246 /*
247  * Command line configuration.
248  */
249 #define CONFIG_CMD_IRQ
250 #define CONFIG_CMD_REGINFO
251 
252 #if defined(CONFIG_PCI)
253 #define CONFIG_CMD_PCI
254 #endif
255 
256 /*
257  * USB
258  */
259 #define CONFIG_HAS_FSL_DR_USB
260 #ifdef CONFIG_HAS_FSL_DR_USB
261 #define CONFIG_USB_EHCI
262 
263 #ifdef CONFIG_USB_EHCI
264 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
265 #define CONFIG_USB_EHCI_FSL
266 #define CONFIG_DOS_PARTITION
267 #endif
268 #endif
269 
270 /*
271  * Miscellaneous configurable options
272  */
273 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
274 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
275 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
276 #if defined(CONFIG_CMD_KGDB)
277 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
278 #else
279 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
280 #endif
281 /* Print Buffer Size */
282 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
283 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
284 /* Boot Argument Buffer Size */
285 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
286 
287 /*
288  * For booting Linux, the board info and command line data
289  * have to be in the first 64 MB of memory, since this is
290  * the maximum mapped by the Linux kernel during initialization.
291  */
292 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
293 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */
294 
295 /*
296  * Environment Configuration
297  */
298 #define CONFIG_BOOTFILE		"uImage"
299 #define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */
300 
301 /* default location for tftp and bootm */
302 #define CONFIG_LOADADDR		1000000
303 
304 
305 #define CONFIG_BAUDRATE	115200
306 
307 /* Qman/Bman */
308 #define CONFIG_SYS_DPAA_QBMAN		/* support Q/Bman */
309 #define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
310 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
311 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
312 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
313 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
314 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
315 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
316 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
317 					CONFIG_SYS_QMAN_CENA_SIZE)
318 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
319 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
320 #define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
321 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
322 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
323 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
324 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
325 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
326 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
327 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
328 					CONFIG_SYS_BMAN_CENA_SIZE)
329 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
330 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
331 
332 /* For FM */
333 #define CONFIG_SYS_DPAA_FMAN
334 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
335 
336 #ifdef CONFIG_SYS_DPAA_FMAN
337 #define CONFIG_FMAN_ENET
338 #define CONFIG_PHY_ATHEROS
339 #endif
340 
341 /* Default address of microcode for the Linux Fman driver */
342 /* QE microcode/firmware address */
343 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
344 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
345 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
346 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
347 
348 #ifdef CONFIG_FMAN_ENET
349 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
350 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2
351 
352 #define CONFIG_SYS_TBIPA_VALUE	8
353 #define CONFIG_MII		/* MII PHY management */
354 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
355 #endif
356 
357 #define CONFIG_EXTRA_ENV_SETTINGS	\
358 	"netdev=eth0\0"						\
359 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
360 	"loadaddr=1000000\0"					\
361 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
362 	"tftpflash=tftpboot $loadaddr $uboot; "			\
363 		"protect off $ubootaddr +$filesize; "		\
364 		"erase $ubootaddr +$filesize; "			\
365 		"cp.b $loadaddr $ubootaddr $filesize; "		\
366 		"protect on $ubootaddr +$filesize; "		\
367 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
368 	"consoledev=ttyS0\0"					\
369 	"ramdiskaddr=2000000\0"					\
370 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
371 	"fdtaddr=1e00000\0"					\
372 	"fdtfile=p1023rdb.dtb\0"				\
373 	"othbootargs=ramdisk_size=600000\0"			\
374 	"bdev=sda1\0"						\
375 	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
376 
377 #define CONFIG_HDBOOT					\
378 	"setenv bootargs root=/dev/$bdev rw "		\
379 	"console=$consoledev,$baudrate $othbootargs;"	\
380 	"tftp $loadaddr $bootfile;"			\
381 	"tftp $fdtaddr $fdtfile;"			\
382 	"bootm $loadaddr - $fdtaddr"
383 
384 #define CONFIG_NFSBOOTCOMMAND						\
385 	"setenv bootargs root=/dev/nfs rw "				\
386 	"nfsroot=$serverip:$rootpath "					\
387 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
388 	"console=$consoledev,$baudrate $othbootargs;"			\
389 	"tftp $loadaddr $bootfile;"					\
390 	"tftp $fdtaddr $fdtfile;"					\
391 	"bootm $loadaddr - $fdtaddr"
392 
393 #define CONFIG_RAMBOOTCOMMAND						\
394 	"setenv bootargs root=/dev/ram rw "				\
395 	"console=$consoledev,$baudrate $othbootargs;"			\
396 	"tftp $ramdiskaddr $ramdiskfile;"				\
397 	"tftp $loadaddr $bootfile;"					\
398 	"tftp $fdtaddr $fdtfile;"					\
399 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
400 
401 #define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
402 
403 #endif	/* __CONFIG_H */
404