xref: /openbmc/u-boot/include/configs/P1023RDB.h (revision 0a61ee88)
1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
5  *	     Chunhe Lan <Chunhe.Lan@freescale.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #define CONFIG_DISPLAY_BOARDINFO
14 
15 #ifndef CONFIG_SYS_TEXT_BASE
16 #define CONFIG_SYS_TEXT_BASE	0xeff40000
17 #endif
18 
19 #ifndef CONFIG_SYS_MONITOR_BASE
20 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
21 #endif
22 
23 #ifndef CONFIG_RESET_VECTOR_ADDRESS
24 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
25 #endif
26 
27 /* High Level Configuration Options */
28 #define CONFIG_BOOKE		/* BOOKE */
29 #define CONFIG_E500		/* BOOKE e500 family */
30 #define CONFIG_P1023
31 #define CONFIG_MP		/* support multiple processors */
32 
33 #define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
34 #define CONFIG_PCI		/* Enable PCI/PCIE */
35 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
36 #define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
37 #define CONFIG_PCIE2		/* PCIE controler 2 (slot 2) */
38 #define CONFIG_PCIE3		/* PCIE controler 3 (slot 3) */
39 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
40 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
41 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
42 #define CONFIG_FSL_LAW		/* Use common FSL init code */
43 
44 #ifndef __ASSEMBLY__
45 extern unsigned long get_clock_freq(void);
46 #endif
47 
48 #define CONFIG_SYS_CLK_FREQ	66666666
49 #define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
50 
51 /*
52  * These can be toggled for performance analysis, otherwise use default.
53  */
54 #define CONFIG_L2_CACHE			/* toggle L2 cache */
55 #define CONFIG_BTB			/* toggle branch predition */
56 #define CONFIG_HWCONFIG
57 
58 #define CONFIG_ENABLE_36BIT_PHYS
59 
60 #define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
61 #define CONFIG_SYS_MEMTEST_END		0x02000000
62 
63 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
64 
65 /* Implement conversion of addresses in the LBC */
66 #define CONFIG_SYS_LBC_LBCR		0x00000000
67 #define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
68 
69 /* DDR Setup */
70 #define CONFIG_VERY_BIG_RAM
71 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
72 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
73 
74 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
75 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
76 
77 #define CONFIG_DDR_SPD
78 #define CONFIG_SYS_FSL_DDR3
79 #define CONFIG_FSL_DDR_INTERACTIVE
80 #define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
81 #define CONFIG_SYS_SPD_BUS_NUM          0
82 #define SPD_EEPROM_ADDRESS              0x50
83 #define CONFIG_SYS_DDR_RAW_TIMING
84 
85 /*
86  * Memory map
87  *
88  * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
89  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
90  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
91  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
92  * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
93  * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
94  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
95  *
96  * Localbus non-cacheable
97  *
98  * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
99  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
100  */
101 
102 /*
103  * Local Bus Definitions
104  */
105 #define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
106 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
107 
108 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
109 				| BR_PS_16 | BR_V)
110 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
111 
112 #define CONFIG_FLASH_CFI_DRIVER
113 #define CONFIG_SYS_FLASH_CFI
114 #define CONFIG_SYS_FLASH_EMPTY_INFO
115 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
116 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
117 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
118 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
119 
120 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f function */
121 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
122 
123 #define CONFIG_SYS_INIT_RAM_LOCK
124 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
125 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
126 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
127 					GENERATED_GBL_DATA_SIZE)
128 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
129 
130 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)	  /* Reserve 512 kB for Mon */
131 #define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */
132 
133 #define CONFIG_SYS_NAND_BASE		0xffa00000
134 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
135 
136 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
137 #define CONFIG_SYS_MAX_NAND_DEVICE	1
138 #define CONFIG_CMD_NAND
139 #define CONFIG_NAND_FSL_ELBC
140 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
141 
142 /* NAND flash config */
143 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
144 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
145 				| BR_PS_8		/* Port Size = 8bit */ \
146 				| BR_MS_FCM		/* MSEL = FCM */ \
147 				| BR_V)			/* valid */
148 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
149 				| OR_FCM_PGS \
150 				| OR_FCM_CSCT \
151 				| OR_FCM_CST \
152 				| OR_FCM_CHT \
153 				| OR_FCM_SCY_1 \
154 				| OR_FCM_TRLX \
155 				| OR_FCM_EHTR)
156 
157 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
158 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
159 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
160 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
161 
162 /* Serial Port */
163 #define CONFIG_CONS_INDEX		1
164 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
165 #define CONFIG_SYS_NS16550_SERIAL
166 #define CONFIG_SYS_NS16550_REG_SIZE	1
167 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
168 
169 #define CONFIG_SYS_BAUDRATE_TABLE	\
170 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
171 
172 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
173 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
174 
175 /* Use the HUSH parser */
176 #define CONFIG_SYS_HUSH_PARSER
177 
178 /*
179  * Pass open firmware flat tree
180  */
181 #define CONFIG_OF_LIBFDT
182 #define CONFIG_OF_BOARD_SETUP
183 #define CONFIG_OF_STDOUT_VIA_ALIAS
184 
185 /* new uImage format support */
186 #define CONFIG_FIT
187 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
188 
189 /* I2C */
190 #define CONFIG_SYS_I2C
191 #define CONFIG_SYS_I2C_FSL
192 #define CONFIG_SYS_FSL_I2C_SPEED	400000
193 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
194 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
195 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
196 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
197 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
198 
199 /*
200  * I2C2 EEPROM
201  */
202 #define CONFIG_ID_EEPROM
203 #ifdef CONFIG_ID_EEPROM
204 #define CONFIG_SYS_I2C_EEPROM_NXID
205 #endif
206 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
207 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
208 #define CONFIG_SYS_EEPROM_BUS_NUM		0
209 
210 #define CONFIG_CMD_I2C
211 
212 /*
213  * General PCI
214  * Memory space is mapped 1-1, but I/O space must start from 0.
215  */
216 
217 /* controller 3, Slot 1, tgtid 3, Base address b000 */
218 #define CONFIG_SYS_PCIE3_NAME		"Slot 3"
219 #define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
220 #define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
221 #define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
222 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
223 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
224 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
225 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
226 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
227 
228 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
229 #define CONFIG_SYS_PCIE2_NAME		"Slot 2"
230 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
231 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
232 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
233 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
234 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
235 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
236 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
237 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
238 
239 /* controller 1, Slot 2, tgtid 1, Base address a000 */
240 #define CONFIG_SYS_PCIE1_NAME		"Slot 1"
241 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
242 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
243 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
244 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
245 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
246 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
247 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
248 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
249 
250 #if defined(CONFIG_PCI)
251 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
252 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
253 #endif	/* CONFIG_PCI */
254 
255 /*
256  * Environment
257  */
258 #define CONFIG_ENV_OVERWRITE
259 
260 #define CONFIG_ENV_IS_IN_FLASH
261 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
262 #define CONFIG_ENV_SIZE		0x2000
263 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
264 
265 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
266 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
267 
268 /*
269  * Command line configuration.
270  */
271 #define CONFIG_CMD_IRQ
272 #define CONFIG_CMD_PING
273 #define CONFIG_CMD_MII
274 #define CONFIG_CMD_REGINFO
275 
276 #if defined(CONFIG_PCI)
277 #define CONFIG_CMD_PCI
278 #endif
279 
280 /*
281  * USB
282  */
283 #define CONFIG_HAS_FSL_DR_USB
284 #ifdef CONFIG_HAS_FSL_DR_USB
285 #define CONFIG_USB_EHCI
286 
287 #ifdef CONFIG_USB_EHCI
288 #define CONFIG_CMD_USB
289 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
290 #define CONFIG_USB_EHCI_FSL
291 #define CONFIG_USB_STORAGE
292 #define CONFIG_CMD_FAT
293 #define CONFIG_CMD_EXT2
294 #define CONFIG_CMD_FAT
295 #define CONFIG_DOS_PARTITION
296 #endif
297 #endif
298 
299 /*
300  * Miscellaneous configurable options
301  */
302 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
303 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
304 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
305 #if defined(CONFIG_CMD_KGDB)
306 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
307 #else
308 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
309 #endif
310 /* Print Buffer Size */
311 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
312 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
313 /* Boot Argument Buffer Size */
314 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
315 
316 /*
317  * For booting Linux, the board info and command line data
318  * have to be in the first 64 MB of memory, since this is
319  * the maximum mapped by the Linux kernel during initialization.
320  */
321 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
322 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */
323 
324 /*
325  * Environment Configuration
326  */
327 #define CONFIG_BOOTFILE		"uImage"
328 #define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */
329 
330 /* default location for tftp and bootm */
331 #define CONFIG_LOADADDR		1000000
332 
333 #define CONFIG_BOOTDELAY -1	/* -1 disables auto-boot */
334 
335 #define CONFIG_BAUDRATE	115200
336 
337 /* Qman/Bman */
338 #define CONFIG_SYS_DPAA_QBMAN		/* support Q/Bman */
339 #define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
340 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
341 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
342 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
343 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
344 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
345 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
346 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
347 					CONFIG_SYS_QMAN_CENA_SIZE)
348 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
349 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
350 #define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
351 #define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
352 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
353 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
354 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
355 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
356 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
357 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
358 					CONFIG_SYS_BMAN_CENA_SIZE)
359 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
360 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
361 
362 /* For FM */
363 #define CONFIG_SYS_DPAA_FMAN
364 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
365 
366 #ifdef CONFIG_SYS_DPAA_FMAN
367 #define CONFIG_FMAN_ENET
368 #define CONFIG_PHY_ATHEROS
369 #endif
370 
371 /* Default address of microcode for the Linux Fman driver */
372 /* QE microcode/firmware address */
373 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
374 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
375 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
376 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
377 
378 #ifdef CONFIG_FMAN_ENET
379 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
380 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2
381 
382 #define CONFIG_SYS_TBIPA_VALUE	8
383 #define CONFIG_MII		/* MII PHY management */
384 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
385 #endif
386 
387 #define CONFIG_EXTRA_ENV_SETTINGS	\
388 	"netdev=eth0\0"						\
389 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
390 	"loadaddr=1000000\0"					\
391 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
392 	"tftpflash=tftpboot $loadaddr $uboot; "			\
393 		"protect off $ubootaddr +$filesize; "		\
394 		"erase $ubootaddr +$filesize; "			\
395 		"cp.b $loadaddr $ubootaddr $filesize; "		\
396 		"protect on $ubootaddr +$filesize; "		\
397 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
398 	"consoledev=ttyS0\0"					\
399 	"ramdiskaddr=2000000\0"					\
400 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
401 	"fdtaddr=c00000\0"					\
402 	"fdtfile=p1023rdb.dtb\0"				\
403 	"othbootargs=ramdisk_size=600000\0"			\
404 	"bdev=sda1\0"						\
405 	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
406 
407 #define CONFIG_HDBOOT					\
408 	"setenv bootargs root=/dev/$bdev rw "		\
409 	"console=$consoledev,$baudrate $othbootargs;"	\
410 	"tftp $loadaddr $bootfile;"			\
411 	"tftp $fdtaddr $fdtfile;"			\
412 	"bootm $loadaddr - $fdtaddr"
413 
414 #define CONFIG_NFSBOOTCOMMAND						\
415 	"setenv bootargs root=/dev/nfs rw "				\
416 	"nfsroot=$serverip:$rootpath "					\
417 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
418 	"console=$consoledev,$baudrate $othbootargs;"			\
419 	"tftp $loadaddr $bootfile;"					\
420 	"tftp $fdtaddr $fdtfile;"					\
421 	"bootm $loadaddr - $fdtaddr"
422 
423 #define CONFIG_RAMBOOTCOMMAND						\
424 	"setenv bootargs root=/dev/ram rw "				\
425 	"console=$consoledev,$baudrate $othbootargs;"			\
426 	"tftp $ramdiskaddr $ramdiskfile;"				\
427 	"tftp $loadaddr $bootfile;"					\
428 	"tftp $fdtaddr $fdtfile;"					\
429 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
430 
431 #define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
432 
433 #endif	/* __CONFIG_H */
434