1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include "../board/freescale/common/ics307_clk.h" 16 17 #ifdef CONFIG_36BIT 18 #define CONFIG_PHYS_64BIT 19 #endif 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE /* BOOKE */ 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 25 #define CONFIG_P1022 26 #define CONFIG_P1022DS 27 #define CONFIG_MP /* support multiple processors */ 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff80000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 38 #define CONFIG_PCI /* Enable PCI/PCIE */ 39 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 44 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 45 46 #ifdef CONFIG_PHYS_64BIT 47 #define CONFIG_ENABLE_36BIT_PHYS 48 #define CONFIG_ADDR_MAP 49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 50 #endif 51 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 56 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE 62 #define CONFIG_BTB 63 64 #define CONFIG_SYS_MEMTEST_START 0x00000000 65 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 66 67 /* 68 * Base addresses -- Note these are effective addresses where the 69 * actual resources get mapped (not physical addresses) 70 */ 71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 72 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 73 #ifdef CONFIG_PHYS_64BIT 74 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull 75 #else 76 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 77 #endif 78 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 79 80 /* DDR Setup */ 81 #define CONFIG_DDR_SPD 82 #define CONFIG_VERY_BIG_RAM 83 #define CONFIG_FSL_DDR3 84 85 #ifdef CONFIG_DDR_ECC 86 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 87 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 88 #endif 89 90 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 92 93 #define CONFIG_NUM_DDR_CONTROLLERS 1 94 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 95 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 96 97 /* I2C addresses of SPD EEPROMs */ 98 #define CONFIG_SYS_SPD_BUS_NUM 1 99 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 100 101 /* 102 * Memory map 103 * 104 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 105 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 106 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 107 * 108 * Localbus cacheable (TBD) 109 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 110 * 111 * Localbus non-cacheable 112 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 113 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 114 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 115 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 116 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 117 */ 118 119 /* 120 * Local Bus Definitions 121 */ 122 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 125 #else 126 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 127 #endif 128 129 #define CONFIG_FLASH_BR_PRELIM \ 130 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 131 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 132 133 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 134 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 135 136 #define CONFIG_SYS_BR1_PRELIM \ 137 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 138 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM 139 140 #define CONFIG_SYS_FLASH_BANKS_LIST \ 141 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 142 #define CONFIG_SYS_FLASH_QUIET_TEST 143 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 144 145 #define CONFIG_SYS_MAX_FLASH_BANKS 2 146 #define CONFIG_SYS_MAX_FLASH_SECT 1024 147 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 149 150 #define CONFIG_FLASH_CFI_DRIVER 151 #define CONFIG_SYS_FLASH_CFI 152 #define CONFIG_SYS_FLASH_EMPTY_INFO 153 154 #define CONFIG_BOARD_EARLY_INIT_F 155 #define CONFIG_BOARD_EARLY_INIT_R 156 #define CONFIG_MISC_INIT_R 157 #define CONFIG_HWCONFIG 158 159 #define CONFIG_FSL_NGPIXIS 160 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 161 #ifdef CONFIG_PHYS_64BIT 162 #define PIXIS_BASE_PHYS 0xfffdf0000ull 163 #else 164 #define PIXIS_BASE_PHYS PIXIS_BASE 165 #endif 166 167 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 168 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 169 170 #define PIXIS_LBMAP_SWITCH 7 171 #define PIXIS_LBMAP_MASK 0xF0 172 #define PIXIS_LBMAP_ALTBANK 0x20 173 174 #define CONFIG_SYS_INIT_RAM_LOCK 175 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 176 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 177 178 #define CONFIG_SYS_GBL_DATA_OFFSET \ 179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 181 182 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 183 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) 184 185 /* 186 * Serial Port 187 */ 188 #define CONFIG_CONS_INDEX 1 189 #define CONFIG_SYS_NS16550 190 #define CONFIG_SYS_NS16550_SERIAL 191 #define CONFIG_SYS_NS16550_REG_SIZE 1 192 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 193 194 #define CONFIG_SYS_BAUDRATE_TABLE \ 195 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 196 197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 199 200 /* Use the HUSH parser */ 201 #define CONFIG_SYS_HUSH_PARSER 202 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 203 204 /* Video */ 205 #ifdef CONFIG_FSL_DIU_FB 206 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 207 #define CONFIG_VIDEO 208 #define CONFIG_CMD_BMP 209 #define CONFIG_CFB_CONSOLE 210 #define CONFIG_VIDEO_SW_CURSOR 211 #define CONFIG_VGA_AS_SINGLE_DEVICE 212 #define CONFIG_VIDEO_LOGO 213 #define CONFIG_VIDEO_BMP_LOGO 214 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 215 /* 216 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 217 * disable empty flash sector detection, which is I/O-intensive. 218 */ 219 #undef CONFIG_SYS_FLASH_EMPTY_INFO 220 #endif 221 222 #ifndef CONFIG_DIU 223 #define CONFIG_ATI 224 #endif 225 226 #ifdef CONFIG_ATI 227 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 228 #define CONFIG_VIDEO 229 #define CONFIG_BIOSEMU 230 #define CONFIG_VIDEO_SW_CURSOR 231 #define CONFIG_ATI_RADEON_FB 232 #define CONFIG_VIDEO_LOGO 233 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 234 #define CONFIG_CFB_CONSOLE 235 #define CONFIG_VGA_AS_SINGLE_DEVICE 236 #endif 237 238 /* 239 * Pass open firmware flat tree 240 */ 241 #define CONFIG_OF_LIBFDT 242 #define CONFIG_OF_BOARD_SETUP 243 #define CONFIG_OF_STDOUT_VIA_ALIAS 244 245 /* new uImage format support */ 246 #define CONFIG_FIT 247 #define CONFIG_FIT_VERBOSE 248 249 /* I2C */ 250 #define CONFIG_FSL_I2C 251 #define CONFIG_HARD_I2C 252 #define CONFIG_I2C_MULTI_BUS 253 #define CONFIG_SYS_I2C_SPEED 400000 254 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 255 #define CONFIG_SYS_I2C_SLAVE 0x7F 256 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 257 #define CONFIG_SYS_I2C_OFFSET 0x3000 258 #define CONFIG_SYS_I2C2_OFFSET 0x3100 259 260 /* 261 * I2C2 EEPROM 262 */ 263 #define CONFIG_ID_EEPROM 264 #define CONFIG_SYS_I2C_EEPROM_NXID 265 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 266 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 267 #define CONFIG_SYS_EEPROM_BUS_NUM 1 268 269 /* 270 * General PCI 271 * Memory space is mapped 1-1, but I/O space must start from 0. 272 */ 273 274 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 275 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 276 #ifdef CONFIG_PHYS_64BIT 277 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 278 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 279 #else 280 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 281 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 282 #endif 283 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 284 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 285 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 288 #else 289 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 290 #endif 291 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 292 293 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 294 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 295 #ifdef CONFIG_PHYS_64BIT 296 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 297 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 298 #else 299 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 300 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 301 #endif 302 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 303 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 304 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 305 #ifdef CONFIG_PHYS_64BIT 306 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 307 #else 308 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 309 #endif 310 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 311 312 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 313 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 316 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 317 #else 318 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 319 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 320 #endif 321 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 322 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 323 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 326 #else 327 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 328 #endif 329 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 330 331 #ifdef CONFIG_PCI 332 #define CONFIG_NET_MULTI 333 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 334 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 335 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 336 #endif 337 338 /* SATA */ 339 #define CONFIG_LIBATA 340 #define CONFIG_FSL_SATA 341 #define CONFIG_FSL_SATA_V2 342 343 #define CONFIG_SYS_SATA_MAX_DEVICE 2 344 #define CONFIG_SATA1 345 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 346 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 347 #define CONFIG_SATA2 348 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 349 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 350 351 #ifdef CONFIG_FSL_SATA 352 #define CONFIG_LBA48 353 #define CONFIG_CMD_SATA 354 #define CONFIG_DOS_PARTITION 355 #define CONFIG_CMD_EXT2 356 #endif 357 358 #define CONFIG_MMC 359 #ifdef CONFIG_MMC 360 #define CONFIG_CMD_MMC 361 #define CONFIG_FSL_ESDHC 362 #define CONFIG_GENERIC_MMC 363 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 364 #endif 365 366 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 367 #define CONFIG_CMD_EXT2 368 #define CONFIG_CMD_FAT 369 #define CONFIG_DOS_PARTITION 370 #endif 371 372 #define CONFIG_TSEC_ENET 373 #ifdef CONFIG_TSEC_ENET 374 375 #define CONFIG_TSECV2 376 #define CONFIG_NET_MULTI 377 378 #define CONFIG_MII /* MII PHY management */ 379 #define CONFIG_TSEC1 1 380 #define CONFIG_TSEC1_NAME "eTSEC1" 381 #define CONFIG_TSEC2 1 382 #define CONFIG_TSEC2_NAME "eTSEC2" 383 384 #define TSEC1_PHY_ADDR 1 385 #define TSEC2_PHY_ADDR 2 386 387 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 388 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 389 390 #define TSEC1_PHYIDX 0 391 #define TSEC2_PHYIDX 0 392 393 #define CONFIG_ETHPRIME "eTSEC1" 394 395 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 396 #endif 397 398 /* 399 * Environment 400 */ 401 #define CONFIG_ENV_IS_IN_FLASH 402 #define CONFIG_ENV_OVERWRITE 403 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 404 #define CONFIG_ENV_SIZE 0x2000 405 #define CONFIG_ENV_SECT_SIZE 0x20000 406 407 #define CONFIG_LOADS_ECHO 408 #define CONFIG_SYS_LOADS_BAUD_CHANGE 409 410 /* 411 * Command line configuration. 412 */ 413 #include <config_cmd_default.h> 414 415 #define CONFIG_CMD_ELF 416 #define CONFIG_CMD_ERRATA 417 #define CONFIG_CMD_IRQ 418 #define CONFIG_CMD_I2C 419 #define CONFIG_CMD_MII 420 #define CONFIG_CMD_PING 421 #define CONFIG_CMD_SETEXPR 422 #define CONFIG_CMD_REGINFO 423 424 #ifdef CONFIG_PCI 425 #define CONFIG_CMD_PCI 426 #define CONFIG_CMD_NET 427 #endif 428 429 /* 430 * USB 431 */ 432 #define CONFIG_USB_EHCI 433 434 #ifdef CONFIG_USB_EHCI 435 #define CONFIG_CMD_USB 436 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 437 #define CONFIG_USB_EHCI_FSL 438 #define CONFIG_USB_STORAGE 439 #define CONFIG_CMD_FAT 440 #endif 441 442 /* 443 * Miscellaneous configurable options 444 */ 445 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 446 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 447 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 448 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 449 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 450 #ifdef CONFIG_CMD_KGDB 451 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 452 #else 453 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 454 #endif 455 /* Print Buffer Size */ 456 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 457 #define CONFIG_SYS_MAXARGS 16 458 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 459 #define CONFIG_SYS_HZ 1000 460 461 /* 462 * For booting Linux, the board info and command line data 463 * have to be in the first 16 MB of memory, since this is 464 * the maximum mapped by the Linux kernel during initialization. 465 */ 466 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 467 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 468 469 #ifdef CONFIG_CMD_KGDB 470 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 471 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 472 #endif 473 474 /* 475 * Environment Configuration 476 */ 477 478 #define CONFIG_HOSTNAME p1022ds 479 #define CONFIG_ROOTPATH /opt/nfsroot 480 #define CONFIG_BOOTFILE uImage 481 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 482 483 #define CONFIG_LOADADDR 1000000 484 485 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 486 #define CONFIG_BOOTARGS 487 488 #define CONFIG_BAUDRATE 115200 489 490 #define CONFIG_EXTRA_ENV_SETTINGS \ 491 "perf_mode=stable\0" \ 492 "memctl_intlv_ctl=2\0" \ 493 "netdev=eth0\0" \ 494 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 495 "tftpflash=tftpboot $loadaddr $uboot; " \ 496 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 497 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 498 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 499 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 500 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 501 "consoledev=ttyS0\0" \ 502 "ramdiskaddr=2000000\0" \ 503 "ramdiskfile=uramdisk\0" \ 504 "fdtaddr=c00000\0" \ 505 "fdtfile=p1022ds.dtb\0" \ 506 "bdev=sda3\0" \ 507 "diuregs=md e002c000 1d\0" \ 508 "dium=mw e002c01c\0" \ 509 "diuerr=md e002c014 1\0" \ 510 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \ 511 "hwconfig=esdhc;audclk:12\0" \ 512 "monitor=0-DVI\0" 513 514 #define CONFIG_HDBOOT \ 515 "setenv bootargs root=/dev/$bdev rw " \ 516 "console=$consoledev,$baudrate $othbootargs;" \ 517 "tftp $loadaddr $bootfile;" \ 518 "tftp $fdtaddr $fdtfile;" \ 519 "bootm $loadaddr - $fdtaddr" 520 521 #define CONFIG_NFSBOOTCOMMAND \ 522 "setenv bootargs root=/dev/nfs rw " \ 523 "nfsroot=$serverip:$rootpath " \ 524 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 525 "console=$consoledev,$baudrate $othbootargs;" \ 526 "tftp $loadaddr $bootfile;" \ 527 "tftp $fdtaddr $fdtfile;" \ 528 "bootm $loadaddr - $fdtaddr" 529 530 #define CONFIG_RAMBOOTCOMMAND \ 531 "setenv bootargs root=/dev/ram rw " \ 532 "console=$consoledev,$baudrate $othbootargs;" \ 533 "tftp $ramdiskaddr $ramdiskfile;" \ 534 "tftp $loadaddr $bootfile;" \ 535 "tftp $fdtaddr $fdtfile;" \ 536 "bootm $loadaddr $ramdiskaddr $fdtaddr" 537 538 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 539 540 #endif 541