1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_SDCARD 15 #define CONFIG_SPL_MMC_MINIMAL 16 #define CONFIG_SPL_FLUSH_IMAGE 17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 18 #define CONFIG_SYS_TEXT_BASE 0x11001000 19 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 20 #define CONFIG_SPL_PAD_TO 0x20000 21 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 28 #define CONFIG_SPL_MMC_BOOT 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #endif 32 #endif 33 34 #ifdef CONFIG_SPIFLASH 35 #define CONFIG_SPL_SPI_FLASH_MINIMAL 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x11001000 39 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 40 #define CONFIG_SPL_PAD_TO 0x20000 41 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 48 #define CONFIG_SPL_SPI_BOOT 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #endif 52 #endif 53 54 #define CONFIG_NAND_FSL_ELBC 55 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 56 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 57 58 #ifdef CONFIG_NAND 59 #ifdef CONFIG_TPL_BUILD 60 #define CONFIG_SPL_NAND_BOOT 61 #define CONFIG_SPL_FLUSH_IMAGE 62 #define CONFIG_SPL_NAND_INIT 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SPL_MAX_SIZE (128 << 10) 65 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 67 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 68 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 69 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 70 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 71 #elif defined(CONFIG_SPL_BUILD) 72 #define CONFIG_SPL_INIT_MINIMAL 73 #define CONFIG_SPL_FLUSH_IMAGE 74 #define CONFIG_SPL_TEXT_BASE 0xff800000 75 #define CONFIG_SPL_MAX_SIZE 4096 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 77 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 78 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 80 #endif 81 #define CONFIG_SPL_PAD_TO 0x20000 82 #define CONFIG_TPL_PAD_TO 0x20000 83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 84 #define CONFIG_SYS_TEXT_BASE 0x11001000 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 86 #endif 87 88 /* High Level Configuration Options */ 89 #define CONFIG_MP /* support multiple processors */ 90 91 #ifndef CONFIG_SYS_TEXT_BASE 92 #define CONFIG_SYS_TEXT_BASE 0xeff40000 93 #endif 94 95 #ifndef CONFIG_RESET_VECTOR_ADDRESS 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 97 #endif 98 99 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 100 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 101 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 102 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 103 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 104 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 105 106 #define CONFIG_ENABLE_36BIT_PHYS 107 108 #ifdef CONFIG_PHYS_64BIT 109 #define CONFIG_ADDR_MAP 110 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 111 #endif 112 113 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 114 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 115 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 116 117 /* 118 * These can be toggled for performance analysis, otherwise use default. 119 */ 120 #define CONFIG_L2_CACHE 121 #define CONFIG_BTB 122 123 #define CONFIG_SYS_MEMTEST_START 0x00000000 124 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 125 126 #define CONFIG_SYS_CCSRBAR 0xffe00000 127 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 128 129 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 130 SPL code*/ 131 #ifdef CONFIG_SPL_BUILD 132 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 133 #endif 134 135 /* DDR Setup */ 136 #define CONFIG_DDR_SPD 137 #define CONFIG_VERY_BIG_RAM 138 139 #ifdef CONFIG_DDR_ECC 140 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 141 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 142 #endif 143 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 148 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 149 150 /* I2C addresses of SPD EEPROMs */ 151 #define CONFIG_SYS_SPD_BUS_NUM 1 152 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 153 154 /* These are used when DDR doesn't use SPD. */ 155 #define CONFIG_SYS_SDRAM_SIZE 2048 156 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 157 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 158 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 159 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 160 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 161 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 162 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 163 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 164 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 165 #define CONFIG_SYS_DDR_MODE_1 0x00441221 166 #define CONFIG_SYS_DDR_MODE_2 0x00000000 167 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 168 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 169 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 170 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 171 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 172 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 173 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 174 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 175 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 176 177 /* 178 * Memory map 179 * 180 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 181 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 182 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 183 * 184 * Localbus cacheable (TBD) 185 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 186 * 187 * Localbus non-cacheable 188 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 189 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 190 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 191 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 194 */ 195 196 /* 197 * Local Bus Definitions 198 */ 199 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 200 #ifdef CONFIG_PHYS_64BIT 201 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 202 #else 203 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 204 #endif 205 206 #define CONFIG_FLASH_BR_PRELIM \ 207 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 208 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 209 210 #ifdef CONFIG_NAND 211 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 212 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 213 #else 214 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 215 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 216 #endif 217 218 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 219 #define CONFIG_SYS_FLASH_QUIET_TEST 220 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 221 222 #define CONFIG_SYS_MAX_FLASH_BANKS 1 223 #define CONFIG_SYS_MAX_FLASH_SECT 1024 224 225 #ifndef CONFIG_SYS_MONITOR_BASE 226 #ifdef CONFIG_SPL_BUILD 227 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 228 #else 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 230 #endif 231 #endif 232 233 #define CONFIG_FLASH_CFI_DRIVER 234 #define CONFIG_SYS_FLASH_CFI 235 #define CONFIG_SYS_FLASH_EMPTY_INFO 236 237 /* Nand Flash */ 238 #if defined(CONFIG_NAND_FSL_ELBC) 239 #define CONFIG_SYS_NAND_BASE 0xff800000 240 #ifdef CONFIG_PHYS_64BIT 241 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 242 #else 243 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 244 #endif 245 246 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 247 #define CONFIG_SYS_MAX_NAND_DEVICE 1 248 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 249 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 250 251 /* NAND flash config */ 252 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 253 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 254 | BR_PS_8 /* Port Size = 8 bit */ \ 255 | BR_MS_FCM /* MSEL = FCM */ \ 256 | BR_V) /* valid */ 257 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 258 | OR_FCM_PGS /* Large Page*/ \ 259 | OR_FCM_CSCT \ 260 | OR_FCM_CST \ 261 | OR_FCM_CHT \ 262 | OR_FCM_SCY_1 \ 263 | OR_FCM_TRLX \ 264 | OR_FCM_EHTR) 265 #ifdef CONFIG_NAND 266 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 267 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 268 #else 269 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 270 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 271 #endif 272 273 #endif /* CONFIG_NAND_FSL_ELBC */ 274 275 #define CONFIG_BOARD_EARLY_INIT_R 276 #define CONFIG_MISC_INIT_R 277 #define CONFIG_HWCONFIG 278 279 #define CONFIG_FSL_NGPIXIS 280 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 281 #ifdef CONFIG_PHYS_64BIT 282 #define PIXIS_BASE_PHYS 0xfffdf0000ull 283 #else 284 #define PIXIS_BASE_PHYS PIXIS_BASE 285 #endif 286 287 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 288 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 289 290 #define PIXIS_LBMAP_SWITCH 7 291 #define PIXIS_LBMAP_MASK 0xF0 292 #define PIXIS_LBMAP_ALTBANK 0x20 293 #define PIXIS_SPD 0x07 294 #define PIXIS_SPD_SYSCLK_MASK 0x07 295 #define PIXIS_ELBC_SPI_MASK 0xc0 296 #define PIXIS_SPI 0x80 297 298 #define CONFIG_SYS_INIT_RAM_LOCK 299 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 300 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 301 302 #define CONFIG_SYS_GBL_DATA_OFFSET \ 303 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 304 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 305 306 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 307 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 308 309 /* 310 * Config the L2 Cache as L2 SRAM 311 */ 312 #if defined(CONFIG_SPL_BUILD) 313 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 314 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 315 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 316 #define CONFIG_SYS_L2_SIZE (256 << 10) 317 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 318 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 319 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 320 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 321 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 322 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 323 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 324 #elif defined(CONFIG_NAND) 325 #ifdef CONFIG_TPL_BUILD 326 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 327 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 328 #define CONFIG_SYS_L2_SIZE (256 << 10) 329 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 330 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 331 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 332 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 333 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 334 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 335 #else 336 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 337 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 338 #define CONFIG_SYS_L2_SIZE (256 << 10) 339 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 340 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 341 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 342 #endif 343 #endif 344 #endif 345 346 /* 347 * Serial Port 348 */ 349 #define CONFIG_CONS_INDEX 1 350 #define CONFIG_SYS_NS16550_SERIAL 351 #define CONFIG_SYS_NS16550_REG_SIZE 1 352 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 353 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 354 #define CONFIG_NS16550_MIN_FUNCTIONS 355 #endif 356 357 #define CONFIG_SYS_BAUDRATE_TABLE \ 358 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 359 360 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 361 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 362 363 /* Video */ 364 365 #ifdef CONFIG_FSL_DIU_FB 366 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 367 #define CONFIG_VIDEO_LOGO 368 #define CONFIG_VIDEO_BMP_LOGO 369 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 370 /* 371 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 372 * disable empty flash sector detection, which is I/O-intensive. 373 */ 374 #undef CONFIG_SYS_FLASH_EMPTY_INFO 375 #endif 376 377 #ifndef CONFIG_FSL_DIU_FB 378 #endif 379 380 #ifdef CONFIG_ATI 381 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 382 #define CONFIG_BIOSEMU 383 #define CONFIG_ATI_RADEON_FB 384 #define CONFIG_VIDEO_LOGO 385 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 386 #endif 387 388 /* I2C */ 389 #define CONFIG_SYS_I2C 390 #define CONFIG_SYS_I2C_FSL 391 #define CONFIG_SYS_FSL_I2C_SPEED 400000 392 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 393 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 394 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 395 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 396 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 397 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 398 399 /* 400 * I2C2 EEPROM 401 */ 402 #define CONFIG_ID_EEPROM 403 #define CONFIG_SYS_I2C_EEPROM_NXID 404 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 405 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 406 #define CONFIG_SYS_EEPROM_BUS_NUM 1 407 408 /* 409 * eSPI - Enhanced SPI 410 */ 411 412 #define CONFIG_HARD_SPI 413 414 #define CONFIG_SF_DEFAULT_SPEED 10000000 415 #define CONFIG_SF_DEFAULT_MODE 0 416 417 /* 418 * General PCI 419 * Memory space is mapped 1-1, but I/O space must start from 0. 420 */ 421 422 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 423 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 426 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 427 #else 428 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 429 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 430 #endif 431 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 432 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 433 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 436 #else 437 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 438 #endif 439 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 440 441 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 442 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 445 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 446 #else 447 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 448 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 449 #endif 450 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 451 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 452 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 455 #else 456 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 457 #endif 458 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 459 460 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 461 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 464 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 465 #else 466 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 467 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 468 #endif 469 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 470 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 471 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 474 #else 475 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 476 #endif 477 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 478 479 #ifdef CONFIG_PCI 480 #define CONFIG_PCI_INDIRECT_BRIDGE 481 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 482 #endif 483 484 /* SATA */ 485 #define CONFIG_LIBATA 486 #define CONFIG_FSL_SATA 487 #define CONFIG_FSL_SATA_V2 488 489 #define CONFIG_SYS_SATA_MAX_DEVICE 2 490 #define CONFIG_SATA1 491 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 492 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 493 #define CONFIG_SATA2 494 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 495 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 496 497 #ifdef CONFIG_FSL_SATA 498 #define CONFIG_LBA48 499 #endif 500 501 #ifdef CONFIG_MMC 502 #define CONFIG_FSL_ESDHC 503 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 504 #endif 505 506 #define CONFIG_TSEC_ENET 507 #ifdef CONFIG_TSEC_ENET 508 509 #define CONFIG_TSECV2 510 511 #define CONFIG_MII /* MII PHY management */ 512 #define CONFIG_TSEC1 1 513 #define CONFIG_TSEC1_NAME "eTSEC1" 514 #define CONFIG_TSEC2 1 515 #define CONFIG_TSEC2_NAME "eTSEC2" 516 517 #define TSEC1_PHY_ADDR 1 518 #define TSEC2_PHY_ADDR 2 519 520 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 521 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 522 523 #define TSEC1_PHYIDX 0 524 #define TSEC2_PHYIDX 0 525 526 #define CONFIG_ETHPRIME "eTSEC1" 527 #endif 528 529 /* 530 * Dynamic MTD Partition support with mtdparts 531 */ 532 #define CONFIG_MTD_DEVICE 533 #define CONFIG_MTD_PARTITIONS 534 #define CONFIG_FLASH_CFI_MTD 535 #ifdef CONFIG_PHYS_64BIT 536 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 537 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 538 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 539 "512k(dtb),768k(u-boot)" 540 #else 541 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 542 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 543 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 544 "512k(dtb),768k(u-boot)" 545 #endif 546 547 /* 548 * Environment 549 */ 550 #ifdef CONFIG_SPIFLASH 551 #define CONFIG_ENV_SPI_BUS 0 552 #define CONFIG_ENV_SPI_CS 0 553 #define CONFIG_ENV_SPI_MAX_HZ 10000000 554 #define CONFIG_ENV_SPI_MODE 0 555 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 556 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 557 #define CONFIG_ENV_SECT_SIZE 0x10000 558 #elif defined(CONFIG_SDCARD) 559 #define CONFIG_FSL_FIXED_MMC_LOCATION 560 #define CONFIG_ENV_SIZE 0x2000 561 #define CONFIG_SYS_MMC_ENV_DEV 0 562 #elif defined(CONFIG_NAND) 563 #ifdef CONFIG_TPL_BUILD 564 #define CONFIG_ENV_SIZE 0x2000 565 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 566 #else 567 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 568 #endif 569 #define CONFIG_ENV_OFFSET (1024 * 1024) 570 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 571 #elif defined(CONFIG_SYS_RAMBOOT) 572 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 573 #define CONFIG_ENV_SIZE 0x2000 574 #else 575 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 576 #define CONFIG_ENV_SIZE 0x2000 577 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 578 #endif 579 580 #define CONFIG_LOADS_ECHO 581 #define CONFIG_SYS_LOADS_BAUD_CHANGE 582 583 /* 584 * USB 585 */ 586 #define CONFIG_HAS_FSL_DR_USB 587 #ifdef CONFIG_HAS_FSL_DR_USB 588 #ifdef CONFIG_USB_EHCI_HCD 589 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 590 #define CONFIG_USB_EHCI_FSL 591 #endif 592 #endif 593 594 /* 595 * Miscellaneous configurable options 596 */ 597 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 598 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 599 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 600 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 601 602 /* 603 * For booting Linux, the board info and command line data 604 * have to be in the first 64 MB of memory, since this is 605 * the maximum mapped by the Linux kernel during initialization. 606 */ 607 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 608 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 609 610 #ifdef CONFIG_CMD_KGDB 611 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 612 #endif 613 614 /* 615 * Environment Configuration 616 */ 617 618 #define CONFIG_HOSTNAME p1022ds 619 #define CONFIG_ROOTPATH "/opt/nfsroot" 620 #define CONFIG_BOOTFILE "uImage" 621 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 622 623 #define CONFIG_LOADADDR 1000000 624 625 #define CONFIG_EXTRA_ENV_SETTINGS \ 626 "netdev=eth0\0" \ 627 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 628 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 629 "tftpflash=tftpboot $loadaddr $uboot && " \ 630 "protect off $ubootaddr +$filesize && " \ 631 "erase $ubootaddr +$filesize && " \ 632 "cp.b $loadaddr $ubootaddr $filesize && " \ 633 "protect on $ubootaddr +$filesize && " \ 634 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 635 "consoledev=ttyS0\0" \ 636 "ramdiskaddr=2000000\0" \ 637 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 638 "fdtaddr=1e00000\0" \ 639 "fdtfile=p1022ds.dtb\0" \ 640 "bdev=sda3\0" \ 641 "hwconfig=esdhc;audclk:12\0" 642 643 #define CONFIG_HDBOOT \ 644 "setenv bootargs root=/dev/$bdev rw " \ 645 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 646 "tftp $loadaddr $bootfile;" \ 647 "tftp $fdtaddr $fdtfile;" \ 648 "bootm $loadaddr - $fdtaddr" 649 650 #define CONFIG_NFSBOOTCOMMAND \ 651 "setenv bootargs root=/dev/nfs rw " \ 652 "nfsroot=$serverip:$rootpath " \ 653 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 654 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 655 "tftp $loadaddr $bootfile;" \ 656 "tftp $fdtaddr $fdtfile;" \ 657 "bootm $loadaddr - $fdtaddr" 658 659 #define CONFIG_RAMBOOTCOMMAND \ 660 "setenv bootargs root=/dev/ram rw " \ 661 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 662 "tftp $ramdiskaddr $ramdiskfile;" \ 663 "tftp $loadaddr $bootfile;" \ 664 "tftp $fdtaddr $fdtfile;" \ 665 "bootm $loadaddr $ramdiskaddr $fdtaddr" 666 667 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 668 669 #endif 670