1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_SDCARD 15 #define CONFIG_SPL_MMC_MINIMAL 16 #define CONFIG_SPL_FLUSH_IMAGE 17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 18 #define CONFIG_SYS_TEXT_BASE 0x11001000 19 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 20 #define CONFIG_SPL_PAD_TO 0x20000 21 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 28 #define CONFIG_SPL_MMC_BOOT 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #endif 32 #endif 33 34 #ifdef CONFIG_SPIFLASH 35 #define CONFIG_SPL_SPI_FLASH_MINIMAL 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x11001000 39 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 40 #define CONFIG_SPL_PAD_TO 0x20000 41 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 48 #define CONFIG_SPL_SPI_BOOT 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #endif 52 #endif 53 54 #define CONFIG_NAND_FSL_ELBC 55 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 56 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 57 58 #ifdef CONFIG_NAND 59 #ifdef CONFIG_TPL_BUILD 60 #define CONFIG_SPL_NAND_BOOT 61 #define CONFIG_SPL_FLUSH_IMAGE 62 #define CONFIG_SPL_NAND_INIT 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SPL_MAX_SIZE (128 << 10) 65 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 67 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 68 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 69 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 70 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 71 #elif defined(CONFIG_SPL_BUILD) 72 #define CONFIG_SPL_INIT_MINIMAL 73 #define CONFIG_SPL_FLUSH_IMAGE 74 #define CONFIG_SPL_TEXT_BASE 0xff800000 75 #define CONFIG_SPL_MAX_SIZE 4096 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 77 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 78 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 80 #endif 81 #define CONFIG_SPL_PAD_TO 0x20000 82 #define CONFIG_TPL_PAD_TO 0x20000 83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 84 #define CONFIG_SYS_TEXT_BASE 0x11001000 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 86 #endif 87 88 /* High Level Configuration Options */ 89 #define CONFIG_MP /* support multiple processors */ 90 91 #ifndef CONFIG_SYS_TEXT_BASE 92 #define CONFIG_SYS_TEXT_BASE 0xeff40000 93 #endif 94 95 #ifndef CONFIG_RESET_VECTOR_ADDRESS 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 97 #endif 98 99 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 100 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 101 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 102 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 103 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 104 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 105 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 106 107 #define CONFIG_ENABLE_36BIT_PHYS 108 109 #ifdef CONFIG_PHYS_64BIT 110 #define CONFIG_ADDR_MAP 111 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 112 #endif 113 114 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 115 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 116 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 117 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_L2_CACHE 122 #define CONFIG_BTB 123 124 #define CONFIG_SYS_MEMTEST_START 0x00000000 125 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 126 127 #define CONFIG_SYS_CCSRBAR 0xffe00000 128 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 129 130 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 131 SPL code*/ 132 #ifdef CONFIG_SPL_BUILD 133 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 134 #endif 135 136 /* DDR Setup */ 137 #define CONFIG_DDR_SPD 138 #define CONFIG_VERY_BIG_RAM 139 140 #ifdef CONFIG_DDR_ECC 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 142 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 143 #endif 144 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 148 #define CONFIG_NUM_DDR_CONTROLLERS 1 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 150 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 151 152 /* I2C addresses of SPD EEPROMs */ 153 #define CONFIG_SYS_SPD_BUS_NUM 1 154 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 155 156 /* These are used when DDR doesn't use SPD. */ 157 #define CONFIG_SYS_SDRAM_SIZE 2048 158 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 159 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 160 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 161 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 162 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 163 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 164 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 165 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 166 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 167 #define CONFIG_SYS_DDR_MODE_1 0x00441221 168 #define CONFIG_SYS_DDR_MODE_2 0x00000000 169 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 170 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 171 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 172 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 173 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 174 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 175 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 176 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 177 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 178 179 /* 180 * Memory map 181 * 182 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 183 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 184 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 185 * 186 * Localbus cacheable (TBD) 187 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 188 * 189 * Localbus non-cacheable 190 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 191 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 192 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 193 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 194 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 195 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 196 */ 197 198 /* 199 * Local Bus Definitions 200 */ 201 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 202 #ifdef CONFIG_PHYS_64BIT 203 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 204 #else 205 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 206 #endif 207 208 #define CONFIG_FLASH_BR_PRELIM \ 209 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 210 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 211 212 #ifdef CONFIG_NAND 213 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 214 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 215 #else 216 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 217 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 218 #endif 219 220 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 221 #define CONFIG_SYS_FLASH_QUIET_TEST 222 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 223 224 #define CONFIG_SYS_MAX_FLASH_BANKS 1 225 #define CONFIG_SYS_MAX_FLASH_SECT 1024 226 227 #ifndef CONFIG_SYS_MONITOR_BASE 228 #ifdef CONFIG_SPL_BUILD 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 230 #else 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 232 #endif 233 #endif 234 235 #define CONFIG_FLASH_CFI_DRIVER 236 #define CONFIG_SYS_FLASH_CFI 237 #define CONFIG_SYS_FLASH_EMPTY_INFO 238 239 /* Nand Flash */ 240 #if defined(CONFIG_NAND_FSL_ELBC) 241 #define CONFIG_SYS_NAND_BASE 0xff800000 242 #ifdef CONFIG_PHYS_64BIT 243 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 244 #else 245 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 246 #endif 247 248 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 249 #define CONFIG_SYS_MAX_NAND_DEVICE 1 250 #define CONFIG_CMD_NAND 1 251 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 252 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 253 254 /* NAND flash config */ 255 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 256 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 257 | BR_PS_8 /* Port Size = 8 bit */ \ 258 | BR_MS_FCM /* MSEL = FCM */ \ 259 | BR_V) /* valid */ 260 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 261 | OR_FCM_PGS /* Large Page*/ \ 262 | OR_FCM_CSCT \ 263 | OR_FCM_CST \ 264 | OR_FCM_CHT \ 265 | OR_FCM_SCY_1 \ 266 | OR_FCM_TRLX \ 267 | OR_FCM_EHTR) 268 #ifdef CONFIG_NAND 269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 271 #else 272 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 273 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 274 #endif 275 276 #endif /* CONFIG_NAND_FSL_ELBC */ 277 278 #define CONFIG_BOARD_EARLY_INIT_F 279 #define CONFIG_BOARD_EARLY_INIT_R 280 #define CONFIG_MISC_INIT_R 281 #define CONFIG_HWCONFIG 282 283 #define CONFIG_FSL_NGPIXIS 284 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 285 #ifdef CONFIG_PHYS_64BIT 286 #define PIXIS_BASE_PHYS 0xfffdf0000ull 287 #else 288 #define PIXIS_BASE_PHYS PIXIS_BASE 289 #endif 290 291 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 292 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 293 294 #define PIXIS_LBMAP_SWITCH 7 295 #define PIXIS_LBMAP_MASK 0xF0 296 #define PIXIS_LBMAP_ALTBANK 0x20 297 #define PIXIS_SPD 0x07 298 #define PIXIS_SPD_SYSCLK_MASK 0x07 299 #define PIXIS_ELBC_SPI_MASK 0xc0 300 #define PIXIS_SPI 0x80 301 302 #define CONFIG_SYS_INIT_RAM_LOCK 303 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 304 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 305 306 #define CONFIG_SYS_GBL_DATA_OFFSET \ 307 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 308 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 309 310 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 311 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 312 313 /* 314 * Config the L2 Cache as L2 SRAM 315 */ 316 #if defined(CONFIG_SPL_BUILD) 317 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 318 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 319 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 320 #define CONFIG_SYS_L2_SIZE (256 << 10) 321 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 322 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 323 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 324 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 325 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 326 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 327 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 328 #elif defined(CONFIG_NAND) 329 #ifdef CONFIG_TPL_BUILD 330 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 331 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 332 #define CONFIG_SYS_L2_SIZE (256 << 10) 333 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 334 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 335 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 336 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 337 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 338 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 339 #else 340 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 341 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 342 #define CONFIG_SYS_L2_SIZE (256 << 10) 343 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 344 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 345 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 346 #endif 347 #endif 348 #endif 349 350 /* 351 * Serial Port 352 */ 353 #define CONFIG_CONS_INDEX 1 354 #define CONFIG_SYS_NS16550_SERIAL 355 #define CONFIG_SYS_NS16550_REG_SIZE 1 356 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 357 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 358 #define CONFIG_NS16550_MIN_FUNCTIONS 359 #endif 360 361 #define CONFIG_SYS_BAUDRATE_TABLE \ 362 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 363 364 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 365 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 366 367 /* Video */ 368 369 #ifdef CONFIG_FSL_DIU_FB 370 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 371 #define CONFIG_CMD_BMP 372 #define CONFIG_VIDEO_LOGO 373 #define CONFIG_VIDEO_BMP_LOGO 374 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 375 /* 376 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 377 * disable empty flash sector detection, which is I/O-intensive. 378 */ 379 #undef CONFIG_SYS_FLASH_EMPTY_INFO 380 #endif 381 382 #ifndef CONFIG_FSL_DIU_FB 383 #endif 384 385 #ifdef CONFIG_ATI 386 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 387 #define CONFIG_BIOSEMU 388 #define CONFIG_ATI_RADEON_FB 389 #define CONFIG_VIDEO_LOGO 390 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 391 #endif 392 393 /* I2C */ 394 #define CONFIG_SYS_I2C 395 #define CONFIG_SYS_I2C_FSL 396 #define CONFIG_SYS_FSL_I2C_SPEED 400000 397 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 398 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 399 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 400 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 401 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 402 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 403 404 /* 405 * I2C2 EEPROM 406 */ 407 #define CONFIG_ID_EEPROM 408 #define CONFIG_SYS_I2C_EEPROM_NXID 409 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 410 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 411 #define CONFIG_SYS_EEPROM_BUS_NUM 1 412 413 /* 414 * eSPI - Enhanced SPI 415 */ 416 417 #define CONFIG_HARD_SPI 418 419 #define CONFIG_SF_DEFAULT_SPEED 10000000 420 #define CONFIG_SF_DEFAULT_MODE 0 421 422 /* 423 * General PCI 424 * Memory space is mapped 1-1, but I/O space must start from 0. 425 */ 426 427 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 428 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 429 #ifdef CONFIG_PHYS_64BIT 430 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 432 #else 433 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 434 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 435 #endif 436 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 437 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 438 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 441 #else 442 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 443 #endif 444 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 445 446 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 447 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 450 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 451 #else 452 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 453 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 454 #endif 455 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 456 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 457 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 460 #else 461 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 462 #endif 463 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 464 465 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 466 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 469 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 470 #else 471 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 472 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 473 #endif 474 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 475 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 476 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 479 #else 480 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 481 #endif 482 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 483 484 #ifdef CONFIG_PCI 485 #define CONFIG_PCI_INDIRECT_BRIDGE 486 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 487 #endif 488 489 /* SATA */ 490 #define CONFIG_LIBATA 491 #define CONFIG_FSL_SATA 492 #define CONFIG_FSL_SATA_V2 493 494 #define CONFIG_SYS_SATA_MAX_DEVICE 2 495 #define CONFIG_SATA1 496 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 497 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 498 #define CONFIG_SATA2 499 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 500 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 501 502 #ifdef CONFIG_FSL_SATA 503 #define CONFIG_LBA48 504 #define CONFIG_CMD_SATA 505 #define CONFIG_DOS_PARTITION 506 #endif 507 508 #ifdef CONFIG_MMC 509 #define CONFIG_FSL_ESDHC 510 #define CONFIG_GENERIC_MMC 511 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 512 #endif 513 514 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 515 #define CONFIG_DOS_PARTITION 516 #endif 517 518 #define CONFIG_TSEC_ENET 519 #ifdef CONFIG_TSEC_ENET 520 521 #define CONFIG_TSECV2 522 523 #define CONFIG_MII /* MII PHY management */ 524 #define CONFIG_TSEC1 1 525 #define CONFIG_TSEC1_NAME "eTSEC1" 526 #define CONFIG_TSEC2 1 527 #define CONFIG_TSEC2_NAME "eTSEC2" 528 529 #define TSEC1_PHY_ADDR 1 530 #define TSEC2_PHY_ADDR 2 531 532 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 533 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 534 535 #define TSEC1_PHYIDX 0 536 #define TSEC2_PHYIDX 0 537 538 #define CONFIG_ETHPRIME "eTSEC1" 539 540 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 541 #endif 542 543 /* 544 * Dynamic MTD Partition support with mtdparts 545 */ 546 #define CONFIG_MTD_DEVICE 547 #define CONFIG_MTD_PARTITIONS 548 #define CONFIG_CMD_MTDPARTS 549 #define CONFIG_FLASH_CFI_MTD 550 #ifdef CONFIG_PHYS_64BIT 551 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 552 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 553 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 554 "512k(dtb),768k(u-boot)" 555 #else 556 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 557 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 558 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 559 "512k(dtb),768k(u-boot)" 560 #endif 561 562 /* 563 * Environment 564 */ 565 #ifdef CONFIG_SPIFLASH 566 #define CONFIG_ENV_IS_IN_SPI_FLASH 567 #define CONFIG_ENV_SPI_BUS 0 568 #define CONFIG_ENV_SPI_CS 0 569 #define CONFIG_ENV_SPI_MAX_HZ 10000000 570 #define CONFIG_ENV_SPI_MODE 0 571 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 572 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 573 #define CONFIG_ENV_SECT_SIZE 0x10000 574 #elif defined(CONFIG_SDCARD) 575 #define CONFIG_ENV_IS_IN_MMC 576 #define CONFIG_FSL_FIXED_MMC_LOCATION 577 #define CONFIG_ENV_SIZE 0x2000 578 #define CONFIG_SYS_MMC_ENV_DEV 0 579 #elif defined(CONFIG_NAND) 580 #ifdef CONFIG_TPL_BUILD 581 #define CONFIG_ENV_SIZE 0x2000 582 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 583 #else 584 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 585 #endif 586 #define CONFIG_ENV_IS_IN_NAND 587 #define CONFIG_ENV_OFFSET (1024 * 1024) 588 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 589 #elif defined(CONFIG_SYS_RAMBOOT) 590 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 591 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 592 #define CONFIG_ENV_SIZE 0x2000 593 #else 594 #define CONFIG_ENV_IS_IN_FLASH 595 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 596 #define CONFIG_ENV_SIZE 0x2000 597 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 598 #endif 599 600 #define CONFIG_LOADS_ECHO 601 #define CONFIG_SYS_LOADS_BAUD_CHANGE 602 603 /* 604 * Command line configuration. 605 */ 606 #define CONFIG_CMD_ERRATA 607 #define CONFIG_CMD_IRQ 608 #define CONFIG_CMD_REGINFO 609 610 #ifdef CONFIG_PCI 611 #define CONFIG_CMD_PCI 612 #endif 613 614 /* 615 * USB 616 */ 617 #define CONFIG_HAS_FSL_DR_USB 618 #ifdef CONFIG_HAS_FSL_DR_USB 619 #define CONFIG_USB_EHCI 620 621 #ifdef CONFIG_USB_EHCI 622 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 623 #define CONFIG_USB_EHCI_FSL 624 #endif 625 #endif 626 627 /* 628 * Miscellaneous configurable options 629 */ 630 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 631 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 632 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 633 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 634 #ifdef CONFIG_CMD_KGDB 635 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 636 #else 637 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 638 #endif 639 /* Print Buffer Size */ 640 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 641 #define CONFIG_SYS_MAXARGS 16 642 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 643 644 /* 645 * For booting Linux, the board info and command line data 646 * have to be in the first 64 MB of memory, since this is 647 * the maximum mapped by the Linux kernel during initialization. 648 */ 649 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 650 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 651 652 #ifdef CONFIG_CMD_KGDB 653 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 654 #endif 655 656 /* 657 * Environment Configuration 658 */ 659 660 #define CONFIG_HOSTNAME p1022ds 661 #define CONFIG_ROOTPATH "/opt/nfsroot" 662 #define CONFIG_BOOTFILE "uImage" 663 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 664 665 #define CONFIG_LOADADDR 1000000 666 667 668 #define CONFIG_BAUDRATE 115200 669 670 #define CONFIG_EXTRA_ENV_SETTINGS \ 671 "netdev=eth0\0" \ 672 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 673 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 674 "tftpflash=tftpboot $loadaddr $uboot && " \ 675 "protect off $ubootaddr +$filesize && " \ 676 "erase $ubootaddr +$filesize && " \ 677 "cp.b $loadaddr $ubootaddr $filesize && " \ 678 "protect on $ubootaddr +$filesize && " \ 679 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 680 "consoledev=ttyS0\0" \ 681 "ramdiskaddr=2000000\0" \ 682 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 683 "fdtaddr=1e00000\0" \ 684 "fdtfile=p1022ds.dtb\0" \ 685 "bdev=sda3\0" \ 686 "hwconfig=esdhc;audclk:12\0" 687 688 #define CONFIG_HDBOOT \ 689 "setenv bootargs root=/dev/$bdev rw " \ 690 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 691 "tftp $loadaddr $bootfile;" \ 692 "tftp $fdtaddr $fdtfile;" \ 693 "bootm $loadaddr - $fdtaddr" 694 695 #define CONFIG_NFSBOOTCOMMAND \ 696 "setenv bootargs root=/dev/nfs rw " \ 697 "nfsroot=$serverip:$rootpath " \ 698 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 699 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 700 "tftp $loadaddr $bootfile;" \ 701 "tftp $fdtaddr $fdtfile;" \ 702 "bootm $loadaddr - $fdtaddr" 703 704 #define CONFIG_RAMBOOTCOMMAND \ 705 "setenv bootargs root=/dev/ram rw " \ 706 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 707 "tftp $ramdiskaddr $ramdiskfile;" \ 708 "tftp $loadaddr $bootfile;" \ 709 "tftp $fdtaddr $fdtfile;" \ 710 "bootm $loadaddr $ramdiskaddr $fdtaddr" 711 712 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 713 714 #endif 715