1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 22 #define CONFIG_SPL_ENV_SUPPORT 23 #define CONFIG_SPL_SERIAL_SUPPORT 24 #define CONFIG_SPL_MMC_SUPPORT 25 #define CONFIG_SPL_MMC_MINIMAL 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_SPL_LIBGENERIC_SUPPORT 29 #define CONFIG_SPL_LIBCOMMON_SUPPORT 30 #define CONFIG_SPL_I2C_SUPPORT 31 #define CONFIG_FSL_LAW /* Use common FSL init code */ 32 #define CONFIG_SYS_TEXT_BASE 0x11001000 33 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 34 #define CONFIG_SPL_PAD_TO 0x20000 35 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 38 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 41 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 42 #define CONFIG_SPL_MMC_BOOT 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_COMMON_INIT_DDR 45 #endif 46 #endif 47 48 #ifdef CONFIG_SPIFLASH 49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 50 #define CONFIG_SPL_ENV_SUPPORT 51 #define CONFIG_SPL_SERIAL_SUPPORT 52 #define CONFIG_SPL_SPI_SUPPORT 53 #define CONFIG_SPL_SPI_FLASH_SUPPORT 54 #define CONFIG_SPL_SPI_FLASH_MINIMAL 55 #define CONFIG_SPL_FLUSH_IMAGE 56 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 57 #define CONFIG_SPL_LIBGENERIC_SUPPORT 58 #define CONFIG_SPL_LIBCOMMON_SUPPORT 59 #define CONFIG_SPL_I2C_SUPPORT 60 #define CONFIG_FSL_LAW /* Use common FSL init code */ 61 #define CONFIG_SYS_TEXT_BASE 0x11001000 62 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 63 #define CONFIG_SPL_PAD_TO 0x20000 64 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 71 #define CONFIG_SPL_SPI_BOOT 72 #ifdef CONFIG_SPL_BUILD 73 #define CONFIG_SPL_COMMON_INIT_DDR 74 #endif 75 #endif 76 77 #define CONFIG_NAND_FSL_ELBC 78 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 79 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 80 81 #ifdef CONFIG_NAND 82 #ifdef CONFIG_TPL_BUILD 83 #define CONFIG_SPL_NAND_BOOT 84 #define CONFIG_SPL_FLUSH_IMAGE 85 #define CONFIG_SPL_ENV_SUPPORT 86 #define CONFIG_SPL_NAND_INIT 87 #define CONFIG_SPL_SERIAL_SUPPORT 88 #define CONFIG_SPL_LIBGENERIC_SUPPORT 89 #define CONFIG_SPL_LIBCOMMON_SUPPORT 90 #define CONFIG_SPL_I2C_SUPPORT 91 #define CONFIG_SPL_NAND_SUPPORT 92 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 93 #define CONFIG_SPL_COMMON_INIT_DDR 94 #define CONFIG_SPL_MAX_SIZE (128 << 10) 95 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 98 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 99 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 100 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 101 #elif defined(CONFIG_SPL_BUILD) 102 #define CONFIG_SPL_INIT_MINIMAL 103 #define CONFIG_SPL_SERIAL_SUPPORT 104 #define CONFIG_SPL_NAND_SUPPORT 105 #define CONFIG_SPL_FLUSH_IMAGE 106 #define CONFIG_SPL_TEXT_BASE 0xff800000 107 #define CONFIG_SPL_MAX_SIZE 4096 108 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 109 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 110 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 111 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 112 #endif 113 #define CONFIG_SPL_PAD_TO 0x20000 114 #define CONFIG_TPL_PAD_TO 0x20000 115 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 116 #define CONFIG_SYS_TEXT_BASE 0x11001000 117 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 118 #endif 119 120 /* High Level Configuration Options */ 121 #define CONFIG_BOOKE /* BOOKE */ 122 #define CONFIG_E500 /* BOOKE e500 family */ 123 #define CONFIG_P1022 124 #define CONFIG_P1022DS 125 #define CONFIG_MP /* support multiple processors */ 126 127 #ifndef CONFIG_SYS_TEXT_BASE 128 #define CONFIG_SYS_TEXT_BASE 0xeff40000 129 #endif 130 131 #ifndef CONFIG_RESET_VECTOR_ADDRESS 132 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 133 #endif 134 135 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 136 #define CONFIG_PCI /* Enable PCI/PCIE */ 137 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 138 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 139 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 140 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 141 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 142 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 143 144 #define CONFIG_ENABLE_36BIT_PHYS 145 146 #ifdef CONFIG_PHYS_64BIT 147 #define CONFIG_ADDR_MAP 148 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 149 #endif 150 151 #define CONFIG_FSL_LAW /* Use common FSL init code */ 152 153 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 154 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 155 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 156 157 /* 158 * These can be toggled for performance analysis, otherwise use default. 159 */ 160 #define CONFIG_L2_CACHE 161 #define CONFIG_BTB 162 163 #define CONFIG_SYS_MEMTEST_START 0x00000000 164 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 165 166 #define CONFIG_SYS_CCSRBAR 0xffe00000 167 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 168 169 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 170 SPL code*/ 171 #ifdef CONFIG_SPL_BUILD 172 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 173 #endif 174 175 176 /* DDR Setup */ 177 #define CONFIG_DDR_SPD 178 #define CONFIG_VERY_BIG_RAM 179 #define CONFIG_SYS_FSL_DDR3 180 181 #ifdef CONFIG_DDR_ECC 182 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 183 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 184 #endif 185 186 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 187 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 188 189 #define CONFIG_NUM_DDR_CONTROLLERS 1 190 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 191 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 192 193 /* I2C addresses of SPD EEPROMs */ 194 #define CONFIG_SYS_SPD_BUS_NUM 1 195 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 196 197 /* These are used when DDR doesn't use SPD. */ 198 #define CONFIG_SYS_SDRAM_SIZE 2048 199 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 200 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 201 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 202 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 203 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 204 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 205 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 206 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 207 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 208 #define CONFIG_SYS_DDR_MODE_1 0x00441221 209 #define CONFIG_SYS_DDR_MODE_2 0x00000000 210 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 211 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 212 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 213 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 214 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 215 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 216 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 217 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 218 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 219 220 221 /* 222 * Memory map 223 * 224 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 225 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 226 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 227 * 228 * Localbus cacheable (TBD) 229 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 230 * 231 * Localbus non-cacheable 232 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 233 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 234 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 235 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 236 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 237 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 238 */ 239 240 /* 241 * Local Bus Definitions 242 */ 243 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 244 #ifdef CONFIG_PHYS_64BIT 245 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 246 #else 247 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 248 #endif 249 250 #define CONFIG_FLASH_BR_PRELIM \ 251 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 252 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 253 254 #ifdef CONFIG_NAND 255 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 256 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 257 #else 258 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 259 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 260 #endif 261 262 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 263 #define CONFIG_SYS_FLASH_QUIET_TEST 264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 265 266 #define CONFIG_SYS_MAX_FLASH_BANKS 1 267 #define CONFIG_SYS_MAX_FLASH_SECT 1024 268 269 #ifndef CONFIG_SYS_MONITOR_BASE 270 #ifdef CONFIG_SPL_BUILD 271 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 272 #else 273 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 274 #endif 275 #endif 276 277 #define CONFIG_FLASH_CFI_DRIVER 278 #define CONFIG_SYS_FLASH_CFI 279 #define CONFIG_SYS_FLASH_EMPTY_INFO 280 281 /* Nand Flash */ 282 #if defined(CONFIG_NAND_FSL_ELBC) 283 #define CONFIG_SYS_NAND_BASE 0xff800000 284 #ifdef CONFIG_PHYS_64BIT 285 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 286 #else 287 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 288 #endif 289 290 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 291 #define CONFIG_SYS_MAX_NAND_DEVICE 1 292 #define CONFIG_CMD_NAND 1 293 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 294 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 295 296 /* NAND flash config */ 297 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 298 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 299 | BR_PS_8 /* Port Size = 8 bit */ \ 300 | BR_MS_FCM /* MSEL = FCM */ \ 301 | BR_V) /* valid */ 302 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 303 | OR_FCM_PGS /* Large Page*/ \ 304 | OR_FCM_CSCT \ 305 | OR_FCM_CST \ 306 | OR_FCM_CHT \ 307 | OR_FCM_SCY_1 \ 308 | OR_FCM_TRLX \ 309 | OR_FCM_EHTR) 310 #ifdef CONFIG_NAND 311 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 312 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 313 #else 314 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 315 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 316 #endif 317 318 #endif /* CONFIG_NAND_FSL_ELBC */ 319 320 #define CONFIG_BOARD_EARLY_INIT_F 321 #define CONFIG_BOARD_EARLY_INIT_R 322 #define CONFIG_MISC_INIT_R 323 #define CONFIG_HWCONFIG 324 325 #define CONFIG_FSL_NGPIXIS 326 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 327 #ifdef CONFIG_PHYS_64BIT 328 #define PIXIS_BASE_PHYS 0xfffdf0000ull 329 #else 330 #define PIXIS_BASE_PHYS PIXIS_BASE 331 #endif 332 333 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 334 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 335 336 #define PIXIS_LBMAP_SWITCH 7 337 #define PIXIS_LBMAP_MASK 0xF0 338 #define PIXIS_LBMAP_ALTBANK 0x20 339 #define PIXIS_SPD 0x07 340 #define PIXIS_SPD_SYSCLK_MASK 0x07 341 #define PIXIS_ELBC_SPI_MASK 0xc0 342 #define PIXIS_SPI 0x80 343 344 #define CONFIG_SYS_INIT_RAM_LOCK 345 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 346 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 347 348 #define CONFIG_SYS_GBL_DATA_OFFSET \ 349 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 350 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 351 352 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 353 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 354 355 /* 356 * Config the L2 Cache as L2 SRAM 357 */ 358 #if defined(CONFIG_SPL_BUILD) 359 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 360 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 361 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 362 #define CONFIG_SYS_L2_SIZE (256 << 10) 363 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 364 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 365 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 366 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 367 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 368 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 369 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 370 #elif defined(CONFIG_NAND) 371 #ifdef CONFIG_TPL_BUILD 372 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 373 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 374 #define CONFIG_SYS_L2_SIZE (256 << 10) 375 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 376 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 377 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 378 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 379 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 380 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 381 #else 382 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 383 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 384 #define CONFIG_SYS_L2_SIZE (256 << 10) 385 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 386 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 387 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 388 #endif 389 #endif 390 #endif 391 392 /* 393 * Serial Port 394 */ 395 #define CONFIG_CONS_INDEX 1 396 #define CONFIG_SYS_NS16550 397 #define CONFIG_SYS_NS16550_SERIAL 398 #define CONFIG_SYS_NS16550_REG_SIZE 1 399 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 400 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 401 #define CONFIG_NS16550_MIN_FUNCTIONS 402 #endif 403 404 #define CONFIG_SYS_BAUDRATE_TABLE \ 405 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 406 407 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 408 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 409 410 /* Use the HUSH parser */ 411 #define CONFIG_SYS_HUSH_PARSER 412 413 /* Video */ 414 415 #ifdef CONFIG_FSL_DIU_FB 416 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 417 #define CONFIG_VIDEO 418 #define CONFIG_CMD_BMP 419 #define CONFIG_CFB_CONSOLE 420 #define CONFIG_VIDEO_SW_CURSOR 421 #define CONFIG_VGA_AS_SINGLE_DEVICE 422 #define CONFIG_VIDEO_LOGO 423 #define CONFIG_VIDEO_BMP_LOGO 424 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 425 /* 426 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 427 * disable empty flash sector detection, which is I/O-intensive. 428 */ 429 #undef CONFIG_SYS_FLASH_EMPTY_INFO 430 #endif 431 432 #ifndef CONFIG_FSL_DIU_FB 433 #endif 434 435 #ifdef CONFIG_ATI 436 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 437 #define CONFIG_VIDEO 438 #define CONFIG_BIOSEMU 439 #define CONFIG_VIDEO_SW_CURSOR 440 #define CONFIG_ATI_RADEON_FB 441 #define CONFIG_VIDEO_LOGO 442 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 443 #define CONFIG_CFB_CONSOLE 444 #define CONFIG_VGA_AS_SINGLE_DEVICE 445 #endif 446 447 /* 448 * Pass open firmware flat tree 449 */ 450 #define CONFIG_OF_LIBFDT 451 #define CONFIG_OF_BOARD_SETUP 452 #define CONFIG_OF_STDOUT_VIA_ALIAS 453 454 /* new uImage format support */ 455 #define CONFIG_FIT 456 #define CONFIG_FIT_VERBOSE 457 458 /* I2C */ 459 #define CONFIG_SYS_I2C 460 #define CONFIG_SYS_I2C_FSL 461 #define CONFIG_SYS_FSL_I2C_SPEED 400000 462 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 463 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 464 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 465 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 466 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 467 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 468 469 /* 470 * I2C2 EEPROM 471 */ 472 #define CONFIG_ID_EEPROM 473 #define CONFIG_SYS_I2C_EEPROM_NXID 474 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 475 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 476 #define CONFIG_SYS_EEPROM_BUS_NUM 1 477 478 /* 479 * eSPI - Enhanced SPI 480 */ 481 #define CONFIG_SPI_FLASH_SPANSION 482 483 #define CONFIG_HARD_SPI 484 #define CONFIG_FSL_ESPI 485 486 #define CONFIG_CMD_SF 487 #define CONFIG_SF_DEFAULT_SPEED 10000000 488 #define CONFIG_SF_DEFAULT_MODE 0 489 490 /* 491 * General PCI 492 * Memory space is mapped 1-1, but I/O space must start from 0. 493 */ 494 495 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 496 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 497 #ifdef CONFIG_PHYS_64BIT 498 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 499 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 500 #else 501 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 502 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 503 #endif 504 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 505 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 506 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 507 #ifdef CONFIG_PHYS_64BIT 508 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 509 #else 510 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 511 #endif 512 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 513 514 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 515 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 516 #ifdef CONFIG_PHYS_64BIT 517 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 518 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 519 #else 520 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 521 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 522 #endif 523 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 524 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 525 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 526 #ifdef CONFIG_PHYS_64BIT 527 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 528 #else 529 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 530 #endif 531 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 532 533 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 534 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 535 #ifdef CONFIG_PHYS_64BIT 536 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 537 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 538 #else 539 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 540 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 541 #endif 542 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 543 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 544 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 545 #ifdef CONFIG_PHYS_64BIT 546 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 547 #else 548 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 549 #endif 550 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 551 552 #ifdef CONFIG_PCI 553 #define CONFIG_PCI_INDIRECT_BRIDGE 554 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 555 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 556 #endif 557 558 /* SATA */ 559 #define CONFIG_LIBATA 560 #define CONFIG_FSL_SATA 561 #define CONFIG_FSL_SATA_V2 562 563 #define CONFIG_SYS_SATA_MAX_DEVICE 2 564 #define CONFIG_SATA1 565 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 566 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 567 #define CONFIG_SATA2 568 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 569 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 570 571 #ifdef CONFIG_FSL_SATA 572 #define CONFIG_LBA48 573 #define CONFIG_CMD_SATA 574 #define CONFIG_DOS_PARTITION 575 #define CONFIG_CMD_EXT2 576 #endif 577 578 #define CONFIG_MMC 579 #ifdef CONFIG_MMC 580 #define CONFIG_CMD_MMC 581 #define CONFIG_FSL_ESDHC 582 #define CONFIG_GENERIC_MMC 583 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 584 #endif 585 586 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 587 #define CONFIG_CMD_EXT2 588 #define CONFIG_CMD_FAT 589 #define CONFIG_DOS_PARTITION 590 #endif 591 592 #define CONFIG_TSEC_ENET 593 #ifdef CONFIG_TSEC_ENET 594 595 #define CONFIG_TSECV2 596 597 #define CONFIG_MII /* MII PHY management */ 598 #define CONFIG_TSEC1 1 599 #define CONFIG_TSEC1_NAME "eTSEC1" 600 #define CONFIG_TSEC2 1 601 #define CONFIG_TSEC2_NAME "eTSEC2" 602 603 #define TSEC1_PHY_ADDR 1 604 #define TSEC2_PHY_ADDR 2 605 606 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 607 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 608 609 #define TSEC1_PHYIDX 0 610 #define TSEC2_PHYIDX 0 611 612 #define CONFIG_ETHPRIME "eTSEC1" 613 614 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 615 #endif 616 617 /* 618 * Dynamic MTD Partition support with mtdparts 619 */ 620 #define CONFIG_MTD_DEVICE 621 #define CONFIG_MTD_PARTITIONS 622 #define CONFIG_CMD_MTDPARTS 623 #define CONFIG_FLASH_CFI_MTD 624 #ifdef CONFIG_PHYS_64BIT 625 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 626 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 627 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 628 "512k(dtb),768k(u-boot)" 629 #else 630 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 631 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 632 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 633 "512k(dtb),768k(u-boot)" 634 #endif 635 636 /* 637 * Environment 638 */ 639 #ifdef CONFIG_SPIFLASH 640 #define CONFIG_ENV_IS_IN_SPI_FLASH 641 #define CONFIG_ENV_SPI_BUS 0 642 #define CONFIG_ENV_SPI_CS 0 643 #define CONFIG_ENV_SPI_MAX_HZ 10000000 644 #define CONFIG_ENV_SPI_MODE 0 645 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 646 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 647 #define CONFIG_ENV_SECT_SIZE 0x10000 648 #elif defined(CONFIG_SDCARD) 649 #define CONFIG_ENV_IS_IN_MMC 650 #define CONFIG_FSL_FIXED_MMC_LOCATION 651 #define CONFIG_ENV_SIZE 0x2000 652 #define CONFIG_SYS_MMC_ENV_DEV 0 653 #elif defined(CONFIG_NAND) 654 #ifdef CONFIG_TPL_BUILD 655 #define CONFIG_ENV_SIZE 0x2000 656 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 657 #else 658 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 659 #endif 660 #define CONFIG_ENV_IS_IN_NAND 661 #define CONFIG_ENV_OFFSET (1024 * 1024) 662 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 663 #elif defined(CONFIG_SYS_RAMBOOT) 664 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 665 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 666 #define CONFIG_ENV_SIZE 0x2000 667 #else 668 #define CONFIG_ENV_IS_IN_FLASH 669 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 670 #define CONFIG_ENV_SIZE 0x2000 671 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 672 #endif 673 674 #define CONFIG_LOADS_ECHO 675 #define CONFIG_SYS_LOADS_BAUD_CHANGE 676 677 /* 678 * Command line configuration. 679 */ 680 #define CONFIG_CMD_ERRATA 681 #define CONFIG_CMD_IRQ 682 #define CONFIG_CMD_I2C 683 #define CONFIG_CMD_MII 684 #define CONFIG_CMD_PING 685 #define CONFIG_CMD_REGINFO 686 687 #ifdef CONFIG_PCI 688 #define CONFIG_CMD_PCI 689 #endif 690 691 /* 692 * USB 693 */ 694 #define CONFIG_HAS_FSL_DR_USB 695 #ifdef CONFIG_HAS_FSL_DR_USB 696 #define CONFIG_USB_EHCI 697 698 #ifdef CONFIG_USB_EHCI 699 #define CONFIG_CMD_USB 700 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 701 #define CONFIG_USB_EHCI_FSL 702 #define CONFIG_USB_STORAGE 703 #define CONFIG_CMD_FAT 704 #endif 705 #endif 706 707 /* 708 * Miscellaneous configurable options 709 */ 710 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 711 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 712 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 713 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 714 #ifdef CONFIG_CMD_KGDB 715 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 716 #else 717 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 718 #endif 719 /* Print Buffer Size */ 720 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 721 #define CONFIG_SYS_MAXARGS 16 722 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 723 724 /* 725 * For booting Linux, the board info and command line data 726 * have to be in the first 64 MB of memory, since this is 727 * the maximum mapped by the Linux kernel during initialization. 728 */ 729 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 730 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 731 732 #ifdef CONFIG_CMD_KGDB 733 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 734 #endif 735 736 /* 737 * Environment Configuration 738 */ 739 740 #define CONFIG_HOSTNAME p1022ds 741 #define CONFIG_ROOTPATH "/opt/nfsroot" 742 #define CONFIG_BOOTFILE "uImage" 743 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 744 745 #define CONFIG_LOADADDR 1000000 746 747 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 748 749 #define CONFIG_BAUDRATE 115200 750 751 #define CONFIG_EXTRA_ENV_SETTINGS \ 752 "netdev=eth0\0" \ 753 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 754 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 755 "tftpflash=tftpboot $loadaddr $uboot && " \ 756 "protect off $ubootaddr +$filesize && " \ 757 "erase $ubootaddr +$filesize && " \ 758 "cp.b $loadaddr $ubootaddr $filesize && " \ 759 "protect on $ubootaddr +$filesize && " \ 760 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 761 "consoledev=ttyS0\0" \ 762 "ramdiskaddr=2000000\0" \ 763 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 764 "fdtaddr=c00000\0" \ 765 "fdtfile=p1022ds.dtb\0" \ 766 "bdev=sda3\0" \ 767 "hwconfig=esdhc;audclk:12\0" 768 769 #define CONFIG_HDBOOT \ 770 "setenv bootargs root=/dev/$bdev rw " \ 771 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 772 "tftp $loadaddr $bootfile;" \ 773 "tftp $fdtaddr $fdtfile;" \ 774 "bootm $loadaddr - $fdtaddr" 775 776 #define CONFIG_NFSBOOTCOMMAND \ 777 "setenv bootargs root=/dev/nfs rw " \ 778 "nfsroot=$serverip:$rootpath " \ 779 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 780 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 781 "tftp $loadaddr $bootfile;" \ 782 "tftp $fdtaddr $fdtfile;" \ 783 "bootm $loadaddr - $fdtaddr" 784 785 #define CONFIG_RAMBOOTCOMMAND \ 786 "setenv bootargs root=/dev/ram rw " \ 787 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 788 "tftp $ramdiskaddr $ramdiskfile;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr $ramdiskaddr $fdtaddr" 792 793 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 794 795 #endif 796