1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_SDCARD 15 #define CONFIG_SPL_MMC_MINIMAL 16 #define CONFIG_SPL_FLUSH_IMAGE 17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 18 #define CONFIG_FSL_LAW /* Use common FSL init code */ 19 #define CONFIG_SYS_TEXT_BASE 0x11001000 20 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 21 #define CONFIG_SPL_PAD_TO 0x20000 22 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 28 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 29 #define CONFIG_SPL_MMC_BOOT 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_COMMON_INIT_DDR 32 #endif 33 #endif 34 35 #ifdef CONFIG_SPIFLASH 36 #define CONFIG_SPL_SPI_FLASH_MINIMAL 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 39 #define CONFIG_FSL_LAW /* Use common FSL init code */ 40 #define CONFIG_SYS_TEXT_BASE 0x11001000 41 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 42 #define CONFIG_SPL_PAD_TO 0x20000 43 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 50 #define CONFIG_SPL_SPI_BOOT 51 #ifdef CONFIG_SPL_BUILD 52 #define CONFIG_SPL_COMMON_INIT_DDR 53 #endif 54 #endif 55 56 #define CONFIG_NAND_FSL_ELBC 57 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 58 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 59 60 #ifdef CONFIG_NAND 61 #ifdef CONFIG_TPL_BUILD 62 #define CONFIG_SPL_NAND_BOOT 63 #define CONFIG_SPL_FLUSH_IMAGE 64 #define CONFIG_SPL_NAND_INIT 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #define CONFIG_SPL_MAX_SIZE (128 << 10) 67 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 70 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 71 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 73 #elif defined(CONFIG_SPL_BUILD) 74 #define CONFIG_SPL_INIT_MINIMAL 75 #define CONFIG_SPL_FLUSH_IMAGE 76 #define CONFIG_SPL_TEXT_BASE 0xff800000 77 #define CONFIG_SPL_MAX_SIZE 4096 78 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 79 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 80 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 81 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 82 #endif 83 #define CONFIG_SPL_PAD_TO 0x20000 84 #define CONFIG_TPL_PAD_TO 0x20000 85 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 86 #define CONFIG_SYS_TEXT_BASE 0x11001000 87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 88 #endif 89 90 /* High Level Configuration Options */ 91 #define CONFIG_BOOKE /* BOOKE */ 92 #define CONFIG_E500 /* BOOKE e500 family */ 93 #define CONFIG_MP /* support multiple processors */ 94 95 #ifndef CONFIG_SYS_TEXT_BASE 96 #define CONFIG_SYS_TEXT_BASE 0xeff40000 97 #endif 98 99 #ifndef CONFIG_RESET_VECTOR_ADDRESS 100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 101 #endif 102 103 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 104 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 105 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 106 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 107 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 108 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 109 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 110 111 #define CONFIG_ENABLE_36BIT_PHYS 112 113 #ifdef CONFIG_PHYS_64BIT 114 #define CONFIG_ADDR_MAP 115 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 116 #endif 117 118 #define CONFIG_FSL_LAW /* Use common FSL init code */ 119 120 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 121 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 122 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 123 124 /* 125 * These can be toggled for performance analysis, otherwise use default. 126 */ 127 #define CONFIG_L2_CACHE 128 #define CONFIG_BTB 129 130 #define CONFIG_SYS_MEMTEST_START 0x00000000 131 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 132 133 #define CONFIG_SYS_CCSRBAR 0xffe00000 134 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 135 136 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 137 SPL code*/ 138 #ifdef CONFIG_SPL_BUILD 139 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 140 #endif 141 142 /* DDR Setup */ 143 #define CONFIG_DDR_SPD 144 #define CONFIG_VERY_BIG_RAM 145 #define CONFIG_SYS_FSL_DDR3 146 147 #ifdef CONFIG_DDR_ECC 148 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 149 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 150 #endif 151 152 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 153 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 154 155 #define CONFIG_NUM_DDR_CONTROLLERS 1 156 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 157 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 158 159 /* I2C addresses of SPD EEPROMs */ 160 #define CONFIG_SYS_SPD_BUS_NUM 1 161 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 162 163 /* These are used when DDR doesn't use SPD. */ 164 #define CONFIG_SYS_SDRAM_SIZE 2048 165 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 166 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 167 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 168 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 169 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 170 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 171 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 172 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 173 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 174 #define CONFIG_SYS_DDR_MODE_1 0x00441221 175 #define CONFIG_SYS_DDR_MODE_2 0x00000000 176 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 177 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 178 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 179 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 180 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 181 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 182 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 183 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 184 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 185 186 /* 187 * Memory map 188 * 189 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 190 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 191 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 192 * 193 * Localbus cacheable (TBD) 194 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 195 * 196 * Localbus non-cacheable 197 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 198 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 199 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 200 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 201 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 202 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 203 */ 204 205 /* 206 * Local Bus Definitions 207 */ 208 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 209 #ifdef CONFIG_PHYS_64BIT 210 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 211 #else 212 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 213 #endif 214 215 #define CONFIG_FLASH_BR_PRELIM \ 216 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 217 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 218 219 #ifdef CONFIG_NAND 220 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 221 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 222 #else 223 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 224 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 225 #endif 226 227 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 228 #define CONFIG_SYS_FLASH_QUIET_TEST 229 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 230 231 #define CONFIG_SYS_MAX_FLASH_BANKS 1 232 #define CONFIG_SYS_MAX_FLASH_SECT 1024 233 234 #ifndef CONFIG_SYS_MONITOR_BASE 235 #ifdef CONFIG_SPL_BUILD 236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 237 #else 238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 239 #endif 240 #endif 241 242 #define CONFIG_FLASH_CFI_DRIVER 243 #define CONFIG_SYS_FLASH_CFI 244 #define CONFIG_SYS_FLASH_EMPTY_INFO 245 246 /* Nand Flash */ 247 #if defined(CONFIG_NAND_FSL_ELBC) 248 #define CONFIG_SYS_NAND_BASE 0xff800000 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 251 #else 252 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 253 #endif 254 255 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 256 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_CMD_NAND 1 258 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 259 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 260 261 /* NAND flash config */ 262 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 263 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 264 | BR_PS_8 /* Port Size = 8 bit */ \ 265 | BR_MS_FCM /* MSEL = FCM */ \ 266 | BR_V) /* valid */ 267 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 268 | OR_FCM_PGS /* Large Page*/ \ 269 | OR_FCM_CSCT \ 270 | OR_FCM_CST \ 271 | OR_FCM_CHT \ 272 | OR_FCM_SCY_1 \ 273 | OR_FCM_TRLX \ 274 | OR_FCM_EHTR) 275 #ifdef CONFIG_NAND 276 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 277 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 278 #else 279 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 280 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 281 #endif 282 283 #endif /* CONFIG_NAND_FSL_ELBC */ 284 285 #define CONFIG_BOARD_EARLY_INIT_F 286 #define CONFIG_BOARD_EARLY_INIT_R 287 #define CONFIG_MISC_INIT_R 288 #define CONFIG_HWCONFIG 289 290 #define CONFIG_FSL_NGPIXIS 291 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 292 #ifdef CONFIG_PHYS_64BIT 293 #define PIXIS_BASE_PHYS 0xfffdf0000ull 294 #else 295 #define PIXIS_BASE_PHYS PIXIS_BASE 296 #endif 297 298 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 299 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 300 301 #define PIXIS_LBMAP_SWITCH 7 302 #define PIXIS_LBMAP_MASK 0xF0 303 #define PIXIS_LBMAP_ALTBANK 0x20 304 #define PIXIS_SPD 0x07 305 #define PIXIS_SPD_SYSCLK_MASK 0x07 306 #define PIXIS_ELBC_SPI_MASK 0xc0 307 #define PIXIS_SPI 0x80 308 309 #define CONFIG_SYS_INIT_RAM_LOCK 310 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 311 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 312 313 #define CONFIG_SYS_GBL_DATA_OFFSET \ 314 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 315 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 316 317 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 318 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 319 320 /* 321 * Config the L2 Cache as L2 SRAM 322 */ 323 #if defined(CONFIG_SPL_BUILD) 324 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 325 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 326 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 327 #define CONFIG_SYS_L2_SIZE (256 << 10) 328 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 329 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 330 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 331 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 332 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 333 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 334 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 335 #elif defined(CONFIG_NAND) 336 #ifdef CONFIG_TPL_BUILD 337 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 338 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 339 #define CONFIG_SYS_L2_SIZE (256 << 10) 340 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 341 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 342 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 343 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 344 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 345 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 346 #else 347 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 348 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 349 #define CONFIG_SYS_L2_SIZE (256 << 10) 350 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 351 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 352 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 353 #endif 354 #endif 355 #endif 356 357 /* 358 * Serial Port 359 */ 360 #define CONFIG_CONS_INDEX 1 361 #define CONFIG_SYS_NS16550_SERIAL 362 #define CONFIG_SYS_NS16550_REG_SIZE 1 363 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 364 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 365 #define CONFIG_NS16550_MIN_FUNCTIONS 366 #endif 367 368 #define CONFIG_SYS_BAUDRATE_TABLE \ 369 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 370 371 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 372 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 373 374 /* Video */ 375 376 #ifdef CONFIG_FSL_DIU_FB 377 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 378 #define CONFIG_CMD_BMP 379 #define CONFIG_VIDEO_LOGO 380 #define CONFIG_VIDEO_BMP_LOGO 381 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 382 /* 383 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 384 * disable empty flash sector detection, which is I/O-intensive. 385 */ 386 #undef CONFIG_SYS_FLASH_EMPTY_INFO 387 #endif 388 389 #ifndef CONFIG_FSL_DIU_FB 390 #endif 391 392 #ifdef CONFIG_ATI 393 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 394 #define CONFIG_BIOSEMU 395 #define CONFIG_ATI_RADEON_FB 396 #define CONFIG_VIDEO_LOGO 397 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 398 #endif 399 400 /* I2C */ 401 #define CONFIG_SYS_I2C 402 #define CONFIG_SYS_I2C_FSL 403 #define CONFIG_SYS_FSL_I2C_SPEED 400000 404 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 405 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 406 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 407 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 408 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 409 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 410 411 /* 412 * I2C2 EEPROM 413 */ 414 #define CONFIG_ID_EEPROM 415 #define CONFIG_SYS_I2C_EEPROM_NXID 416 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 417 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 418 #define CONFIG_SYS_EEPROM_BUS_NUM 1 419 420 /* 421 * eSPI - Enhanced SPI 422 */ 423 424 #define CONFIG_HARD_SPI 425 426 #define CONFIG_SF_DEFAULT_SPEED 10000000 427 #define CONFIG_SF_DEFAULT_MODE 0 428 429 /* 430 * General PCI 431 * Memory space is mapped 1-1, but I/O space must start from 0. 432 */ 433 434 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 435 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 438 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 439 #else 440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 442 #endif 443 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 444 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 445 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 448 #else 449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 450 #endif 451 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 452 453 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 454 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 457 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 458 #else 459 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 460 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 461 #endif 462 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 463 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 464 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 465 #ifdef CONFIG_PHYS_64BIT 466 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 467 #else 468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 469 #endif 470 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 471 472 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 473 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 476 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 477 #else 478 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 479 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 480 #endif 481 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 482 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 483 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 484 #ifdef CONFIG_PHYS_64BIT 485 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 486 #else 487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 488 #endif 489 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 490 491 #ifdef CONFIG_PCI 492 #define CONFIG_PCI_INDIRECT_BRIDGE 493 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 494 #endif 495 496 /* SATA */ 497 #define CONFIG_LIBATA 498 #define CONFIG_FSL_SATA 499 #define CONFIG_FSL_SATA_V2 500 501 #define CONFIG_SYS_SATA_MAX_DEVICE 2 502 #define CONFIG_SATA1 503 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 504 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 505 #define CONFIG_SATA2 506 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 507 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 508 509 #ifdef CONFIG_FSL_SATA 510 #define CONFIG_LBA48 511 #define CONFIG_CMD_SATA 512 #define CONFIG_DOS_PARTITION 513 #endif 514 515 #define CONFIG_MMC 516 #ifdef CONFIG_MMC 517 #define CONFIG_FSL_ESDHC 518 #define CONFIG_GENERIC_MMC 519 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 520 #endif 521 522 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 523 #define CONFIG_DOS_PARTITION 524 #endif 525 526 #define CONFIG_TSEC_ENET 527 #ifdef CONFIG_TSEC_ENET 528 529 #define CONFIG_TSECV2 530 531 #define CONFIG_MII /* MII PHY management */ 532 #define CONFIG_TSEC1 1 533 #define CONFIG_TSEC1_NAME "eTSEC1" 534 #define CONFIG_TSEC2 1 535 #define CONFIG_TSEC2_NAME "eTSEC2" 536 537 #define TSEC1_PHY_ADDR 1 538 #define TSEC2_PHY_ADDR 2 539 540 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 541 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 542 543 #define TSEC1_PHYIDX 0 544 #define TSEC2_PHYIDX 0 545 546 #define CONFIG_ETHPRIME "eTSEC1" 547 548 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 549 #endif 550 551 /* 552 * Dynamic MTD Partition support with mtdparts 553 */ 554 #define CONFIG_MTD_DEVICE 555 #define CONFIG_MTD_PARTITIONS 556 #define CONFIG_CMD_MTDPARTS 557 #define CONFIG_FLASH_CFI_MTD 558 #ifdef CONFIG_PHYS_64BIT 559 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 560 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 561 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 562 "512k(dtb),768k(u-boot)" 563 #else 564 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 565 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 566 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 567 "512k(dtb),768k(u-boot)" 568 #endif 569 570 /* 571 * Environment 572 */ 573 #ifdef CONFIG_SPIFLASH 574 #define CONFIG_ENV_IS_IN_SPI_FLASH 575 #define CONFIG_ENV_SPI_BUS 0 576 #define CONFIG_ENV_SPI_CS 0 577 #define CONFIG_ENV_SPI_MAX_HZ 10000000 578 #define CONFIG_ENV_SPI_MODE 0 579 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 580 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 581 #define CONFIG_ENV_SECT_SIZE 0x10000 582 #elif defined(CONFIG_SDCARD) 583 #define CONFIG_ENV_IS_IN_MMC 584 #define CONFIG_FSL_FIXED_MMC_LOCATION 585 #define CONFIG_ENV_SIZE 0x2000 586 #define CONFIG_SYS_MMC_ENV_DEV 0 587 #elif defined(CONFIG_NAND) 588 #ifdef CONFIG_TPL_BUILD 589 #define CONFIG_ENV_SIZE 0x2000 590 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 591 #else 592 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 593 #endif 594 #define CONFIG_ENV_IS_IN_NAND 595 #define CONFIG_ENV_OFFSET (1024 * 1024) 596 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 597 #elif defined(CONFIG_SYS_RAMBOOT) 598 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 599 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 600 #define CONFIG_ENV_SIZE 0x2000 601 #else 602 #define CONFIG_ENV_IS_IN_FLASH 603 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 604 #define CONFIG_ENV_SIZE 0x2000 605 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 606 #endif 607 608 #define CONFIG_LOADS_ECHO 609 #define CONFIG_SYS_LOADS_BAUD_CHANGE 610 611 /* 612 * Command line configuration. 613 */ 614 #define CONFIG_CMD_ERRATA 615 #define CONFIG_CMD_IRQ 616 #define CONFIG_CMD_REGINFO 617 618 #ifdef CONFIG_PCI 619 #define CONFIG_CMD_PCI 620 #endif 621 622 /* 623 * USB 624 */ 625 #define CONFIG_HAS_FSL_DR_USB 626 #ifdef CONFIG_HAS_FSL_DR_USB 627 #define CONFIG_USB_EHCI 628 629 #ifdef CONFIG_USB_EHCI 630 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 631 #define CONFIG_USB_EHCI_FSL 632 #endif 633 #endif 634 635 /* 636 * Miscellaneous configurable options 637 */ 638 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 639 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 640 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 641 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 642 #ifdef CONFIG_CMD_KGDB 643 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 644 #else 645 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 646 #endif 647 /* Print Buffer Size */ 648 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 649 #define CONFIG_SYS_MAXARGS 16 650 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 651 652 /* 653 * For booting Linux, the board info and command line data 654 * have to be in the first 64 MB of memory, since this is 655 * the maximum mapped by the Linux kernel during initialization. 656 */ 657 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 658 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 659 660 #ifdef CONFIG_CMD_KGDB 661 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 662 #endif 663 664 /* 665 * Environment Configuration 666 */ 667 668 #define CONFIG_HOSTNAME p1022ds 669 #define CONFIG_ROOTPATH "/opt/nfsroot" 670 #define CONFIG_BOOTFILE "uImage" 671 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 672 673 #define CONFIG_LOADADDR 1000000 674 675 676 #define CONFIG_BAUDRATE 115200 677 678 #define CONFIG_EXTRA_ENV_SETTINGS \ 679 "netdev=eth0\0" \ 680 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 681 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 682 "tftpflash=tftpboot $loadaddr $uboot && " \ 683 "protect off $ubootaddr +$filesize && " \ 684 "erase $ubootaddr +$filesize && " \ 685 "cp.b $loadaddr $ubootaddr $filesize && " \ 686 "protect on $ubootaddr +$filesize && " \ 687 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 688 "consoledev=ttyS0\0" \ 689 "ramdiskaddr=2000000\0" \ 690 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 691 "fdtaddr=1e00000\0" \ 692 "fdtfile=p1022ds.dtb\0" \ 693 "bdev=sda3\0" \ 694 "hwconfig=esdhc;audclk:12\0" 695 696 #define CONFIG_HDBOOT \ 697 "setenv bootargs root=/dev/$bdev rw " \ 698 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 699 "tftp $loadaddr $bootfile;" \ 700 "tftp $fdtaddr $fdtfile;" \ 701 "bootm $loadaddr - $fdtaddr" 702 703 #define CONFIG_NFSBOOTCOMMAND \ 704 "setenv bootargs root=/dev/nfs rw " \ 705 "nfsroot=$serverip:$rootpath " \ 706 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 707 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 708 "tftp $loadaddr $bootfile;" \ 709 "tftp $fdtaddr $fdtfile;" \ 710 "bootm $loadaddr - $fdtaddr" 711 712 #define CONFIG_RAMBOOTCOMMAND \ 713 "setenv bootargs root=/dev/ram rw " \ 714 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 715 "tftp $ramdiskaddr $ramdiskfile;" \ 716 "tftp $loadaddr $bootfile;" \ 717 "tftp $fdtaddr $fdtfile;" \ 718 "bootm $loadaddr $ramdiskaddr $fdtaddr" 719 720 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 721 722 #endif 723