1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include "../board/freescale/common/ics307_clk.h" 16 17 #ifdef CONFIG_36BIT 18 #define CONFIG_PHYS_64BIT 19 #endif 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE /* BOOKE */ 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 25 #define CONFIG_P1022 26 #define CONFIG_P1022DS 27 #define CONFIG_MP /* support multiple processors */ 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff80000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 38 #define CONFIG_PCI /* Enable PCI/PCIE */ 39 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 44 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 45 46 #define CONFIG_ENABLE_36BIT_PHYS 47 48 #ifdef CONFIG_PHYS_64BIT 49 #define CONFIG_ADDR_MAP 50 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 51 #endif 52 53 #define CONFIG_FSL_LAW /* Use common FSL init code */ 54 55 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 56 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 57 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE 63 #define CONFIG_BTB 64 65 #define CONFIG_SYS_MEMTEST_START 0x00000000 66 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 67 68 #define CONFIG_SYS_CCSRBAR 0xffe00000 69 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 70 71 /* DDR Setup */ 72 #define CONFIG_DDR_SPD 73 #define CONFIG_VERY_BIG_RAM 74 #define CONFIG_FSL_DDR3 75 76 #ifdef CONFIG_DDR_ECC 77 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 78 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 79 #endif 80 81 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 82 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 83 84 #define CONFIG_NUM_DDR_CONTROLLERS 1 85 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 86 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 87 88 /* I2C addresses of SPD EEPROMs */ 89 #define CONFIG_SYS_SPD_BUS_NUM 1 90 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 91 92 /* 93 * Memory map 94 * 95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 96 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 97 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 98 * 99 * Localbus cacheable (TBD) 100 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 101 * 102 * Localbus non-cacheable 103 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 104 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 105 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 106 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 107 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 108 */ 109 110 /* 111 * Local Bus Definitions 112 */ 113 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 114 #ifdef CONFIG_PHYS_64BIT 115 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 116 #else 117 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 118 #endif 119 120 #define CONFIG_FLASH_BR_PRELIM \ 121 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 122 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 123 124 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 125 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 126 127 #define CONFIG_SYS_BR1_PRELIM \ 128 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 129 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM 130 131 #define CONFIG_SYS_FLASH_BANKS_LIST \ 132 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 133 #define CONFIG_SYS_FLASH_QUIET_TEST 134 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 135 136 #define CONFIG_SYS_MAX_FLASH_BANKS 2 137 #define CONFIG_SYS_MAX_FLASH_SECT 1024 138 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 140 141 #define CONFIG_FLASH_CFI_DRIVER 142 #define CONFIG_SYS_FLASH_CFI 143 #define CONFIG_SYS_FLASH_EMPTY_INFO 144 145 #define CONFIG_BOARD_EARLY_INIT_F 146 #define CONFIG_BOARD_EARLY_INIT_R 147 #define CONFIG_MISC_INIT_R 148 #define CONFIG_HWCONFIG 149 150 #define CONFIG_FSL_NGPIXIS 151 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 152 #ifdef CONFIG_PHYS_64BIT 153 #define PIXIS_BASE_PHYS 0xfffdf0000ull 154 #else 155 #define PIXIS_BASE_PHYS PIXIS_BASE 156 #endif 157 158 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 159 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 160 161 #define PIXIS_LBMAP_SWITCH 7 162 #define PIXIS_LBMAP_MASK 0xF0 163 #define PIXIS_LBMAP_ALTBANK 0x20 164 #define PIXIS_ELBC_SPI_MASK 0xc0 165 #define PIXIS_SPI 0x80 166 167 #define CONFIG_SYS_INIT_RAM_LOCK 168 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 169 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 170 171 #define CONFIG_SYS_GBL_DATA_OFFSET \ 172 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 173 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 174 175 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 176 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 177 178 /* 179 * Serial Port 180 */ 181 #define CONFIG_CONS_INDEX 1 182 #define CONFIG_SYS_NS16550 183 #define CONFIG_SYS_NS16550_SERIAL 184 #define CONFIG_SYS_NS16550_REG_SIZE 1 185 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 186 187 #define CONFIG_SYS_BAUDRATE_TABLE \ 188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 189 190 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 191 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 192 193 /* Use the HUSH parser */ 194 #define CONFIG_SYS_HUSH_PARSER 195 196 /* Video */ 197 #define CONFIG_FSL_DIU_FB 198 199 #ifdef CONFIG_FSL_DIU_FB 200 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 201 #define CONFIG_VIDEO 202 #define CONFIG_CMD_BMP 203 #define CONFIG_CFB_CONSOLE 204 #define CONFIG_VIDEO_SW_CURSOR 205 #define CONFIG_VGA_AS_SINGLE_DEVICE 206 #define CONFIG_VIDEO_LOGO 207 #define CONFIG_VIDEO_BMP_LOGO 208 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 209 /* 210 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 211 * disable empty flash sector detection, which is I/O-intensive. 212 */ 213 #undef CONFIG_SYS_FLASH_EMPTY_INFO 214 #endif 215 216 #ifndef CONFIG_FSL_DIU_FB 217 #define CONFIG_ATI 218 #endif 219 220 #ifdef CONFIG_ATI 221 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 222 #define CONFIG_VIDEO 223 #define CONFIG_BIOSEMU 224 #define CONFIG_VIDEO_SW_CURSOR 225 #define CONFIG_ATI_RADEON_FB 226 #define CONFIG_VIDEO_LOGO 227 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 228 #define CONFIG_CFB_CONSOLE 229 #define CONFIG_VGA_AS_SINGLE_DEVICE 230 #endif 231 232 /* 233 * Pass open firmware flat tree 234 */ 235 #define CONFIG_OF_LIBFDT 236 #define CONFIG_OF_BOARD_SETUP 237 #define CONFIG_OF_STDOUT_VIA_ALIAS 238 239 /* new uImage format support */ 240 #define CONFIG_FIT 241 #define CONFIG_FIT_VERBOSE 242 243 /* I2C */ 244 #define CONFIG_FSL_I2C 245 #define CONFIG_HARD_I2C 246 #define CONFIG_I2C_MULTI_BUS 247 #define CONFIG_SYS_I2C_SPEED 400000 248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 249 #define CONFIG_SYS_I2C_SLAVE 0x7F 250 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 251 #define CONFIG_SYS_I2C_OFFSET 0x3000 252 #define CONFIG_SYS_I2C2_OFFSET 0x3100 253 254 /* 255 * I2C2 EEPROM 256 */ 257 #define CONFIG_ID_EEPROM 258 #define CONFIG_SYS_I2C_EEPROM_NXID 259 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 260 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 261 #define CONFIG_SYS_EEPROM_BUS_NUM 1 262 263 /* 264 * eSPI - Enhanced SPI 265 */ 266 #define CONFIG_SPI_FLASH 267 #define CONFIG_SPI_FLASH_SPANSION 268 269 #define CONFIG_HARD_SPI 270 #define CONFIG_FSL_ESPI 271 272 #define CONFIG_CMD_SF 273 #define CONFIG_SF_DEFAULT_SPEED 10000000 274 #define CONFIG_SF_DEFAULT_MODE 0 275 276 /* 277 * General PCI 278 * Memory space is mapped 1-1, but I/O space must start from 0. 279 */ 280 281 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 282 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 283 #ifdef CONFIG_PHYS_64BIT 284 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 285 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 286 #else 287 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 288 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 289 #endif 290 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 291 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 292 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 295 #else 296 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 297 #endif 298 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 299 300 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 301 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 302 #ifdef CONFIG_PHYS_64BIT 303 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 304 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 305 #else 306 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 307 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 308 #endif 309 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 310 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 311 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 312 #ifdef CONFIG_PHYS_64BIT 313 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 314 #else 315 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 316 #endif 317 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 318 319 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 320 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 321 #ifdef CONFIG_PHYS_64BIT 322 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 323 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 324 #else 325 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 326 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 327 #endif 328 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 329 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 330 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 331 #ifdef CONFIG_PHYS_64BIT 332 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 333 #else 334 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 335 #endif 336 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 337 338 #ifdef CONFIG_PCI 339 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 340 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 341 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 342 #endif 343 344 /* SATA */ 345 #define CONFIG_LIBATA 346 #define CONFIG_FSL_SATA 347 348 #define CONFIG_SYS_SATA_MAX_DEVICE 2 349 #define CONFIG_SATA1 350 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 351 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 352 #define CONFIG_SATA2 353 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 354 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 355 356 #ifdef CONFIG_FSL_SATA 357 #define CONFIG_LBA48 358 #define CONFIG_CMD_SATA 359 #define CONFIG_DOS_PARTITION 360 #define CONFIG_CMD_EXT2 361 #endif 362 363 #define CONFIG_MMC 364 #ifdef CONFIG_MMC 365 #define CONFIG_CMD_MMC 366 #define CONFIG_FSL_ESDHC 367 #define CONFIG_GENERIC_MMC 368 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 369 #endif 370 371 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 372 #define CONFIG_CMD_EXT2 373 #define CONFIG_CMD_FAT 374 #define CONFIG_DOS_PARTITION 375 #endif 376 377 #define CONFIG_TSEC_ENET 378 #ifdef CONFIG_TSEC_ENET 379 380 #define CONFIG_TSECV2 381 382 #define CONFIG_MII /* MII PHY management */ 383 #define CONFIG_TSEC1 1 384 #define CONFIG_TSEC1_NAME "eTSEC1" 385 #define CONFIG_TSEC2 1 386 #define CONFIG_TSEC2_NAME "eTSEC2" 387 388 #define TSEC1_PHY_ADDR 1 389 #define TSEC2_PHY_ADDR 2 390 391 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 392 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 393 394 #define TSEC1_PHYIDX 0 395 #define TSEC2_PHYIDX 0 396 397 #define CONFIG_ETHPRIME "eTSEC1" 398 399 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 400 #endif 401 402 /* 403 * Environment 404 */ 405 #define CONFIG_ENV_IS_IN_FLASH 406 #define CONFIG_ENV_OVERWRITE 407 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 408 #define CONFIG_ENV_SIZE 0x2000 409 #define CONFIG_ENV_SECT_SIZE 0x20000 410 411 #define CONFIG_LOADS_ECHO 412 #define CONFIG_SYS_LOADS_BAUD_CHANGE 413 414 /* 415 * Command line configuration. 416 */ 417 #include <config_cmd_default.h> 418 419 #define CONFIG_CMD_ELF 420 #define CONFIG_CMD_ERRATA 421 #define CONFIG_CMD_IRQ 422 #define CONFIG_CMD_I2C 423 #define CONFIG_CMD_MII 424 #define CONFIG_CMD_PING 425 #define CONFIG_CMD_SETEXPR 426 #define CONFIG_CMD_REGINFO 427 428 #ifdef CONFIG_PCI 429 #define CONFIG_CMD_PCI 430 #define CONFIG_CMD_NET 431 #endif 432 433 /* 434 * USB 435 */ 436 #define CONFIG_USB_EHCI 437 438 #ifdef CONFIG_USB_EHCI 439 #define CONFIG_CMD_USB 440 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 441 #define CONFIG_USB_EHCI_FSL 442 #define CONFIG_USB_STORAGE 443 #define CONFIG_CMD_FAT 444 #endif 445 446 /* 447 * Miscellaneous configurable options 448 */ 449 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 450 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 451 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 452 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 453 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 454 #ifdef CONFIG_CMD_KGDB 455 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 456 #else 457 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 458 #endif 459 /* Print Buffer Size */ 460 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 461 #define CONFIG_SYS_MAXARGS 16 462 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 463 #define CONFIG_SYS_HZ 1000 464 465 /* 466 * For booting Linux, the board info and command line data 467 * have to be in the first 64 MB of memory, since this is 468 * the maximum mapped by the Linux kernel during initialization. 469 */ 470 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 471 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 472 473 #ifdef CONFIG_CMD_KGDB 474 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 475 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 476 #endif 477 478 /* 479 * Environment Configuration 480 */ 481 482 #define CONFIG_HOSTNAME p1022ds 483 #define CONFIG_ROOTPATH "/opt/nfsroot" 484 #define CONFIG_BOOTFILE "uImage" 485 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 486 487 #define CONFIG_LOADADDR 1000000 488 489 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 490 #define CONFIG_BOOTARGS 491 492 #define CONFIG_BAUDRATE 115200 493 494 #define CONFIG_EXTRA_ENV_SETTINGS \ 495 "perf_mode=stable\0" \ 496 "memctl_intlv_ctl=2\0" \ 497 "netdev=eth0\0" \ 498 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 499 "tftpflash=tftpboot $loadaddr $uboot; " \ 500 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 501 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 502 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 503 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 504 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 505 "consoledev=ttyS0\0" \ 506 "ramdiskaddr=2000000\0" \ 507 "ramdiskfile=uramdisk\0" \ 508 "fdtaddr=c00000\0" \ 509 "fdtfile=p1022ds.dtb\0" \ 510 "bdev=sda3\0" \ 511 "diuregs=md e002c000 1d\0" \ 512 "dium=mw e002c01c\0" \ 513 "diuerr=md e002c014 1\0" \ 514 "hwconfig=esdhc;audclk:12\0" 515 516 #define CONFIG_HDBOOT \ 517 "setenv bootargs root=/dev/$bdev rw " \ 518 "console=$consoledev,$baudrate $othbootargs;" \ 519 "tftp $loadaddr $bootfile;" \ 520 "tftp $fdtaddr $fdtfile;" \ 521 "bootm $loadaddr - $fdtaddr" 522 523 #define CONFIG_NFSBOOTCOMMAND \ 524 "setenv bootargs root=/dev/nfs rw " \ 525 "nfsroot=$serverip:$rootpath " \ 526 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 527 "console=$consoledev,$baudrate $othbootargs;" \ 528 "tftp $loadaddr $bootfile;" \ 529 "tftp $fdtaddr $fdtfile;" \ 530 "bootm $loadaddr - $fdtaddr" 531 532 #define CONFIG_RAMBOOTCOMMAND \ 533 "setenv bootargs root=/dev/ram rw " \ 534 "console=$consoledev,$baudrate $othbootargs;" \ 535 "tftp $ramdiskaddr $ramdiskfile;" \ 536 "tftp $loadaddr $bootfile;" \ 537 "tftp $fdtaddr $fdtfile;" \ 538 "bootm $loadaddr $ramdiskaddr $fdtaddr" 539 540 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 541 542 #endif 543