1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_SDCARD 15 #define CONFIG_SPL_MMC_MINIMAL 16 #define CONFIG_SPL_FLUSH_IMAGE 17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 18 #define CONFIG_SYS_TEXT_BASE 0x11001000 19 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 20 #define CONFIG_SPL_PAD_TO 0x20000 21 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 28 #define CONFIG_SPL_MMC_BOOT 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #endif 32 #endif 33 34 #ifdef CONFIG_SPIFLASH 35 #define CONFIG_SPL_SPI_FLASH_MINIMAL 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x11001000 39 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 40 #define CONFIG_SPL_PAD_TO 0x20000 41 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 48 #define CONFIG_SPL_SPI_BOOT 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #endif 52 #endif 53 54 #define CONFIG_NAND_FSL_ELBC 55 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 56 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 57 58 #ifdef CONFIG_NAND 59 #ifdef CONFIG_TPL_BUILD 60 #define CONFIG_SPL_NAND_BOOT 61 #define CONFIG_SPL_FLUSH_IMAGE 62 #define CONFIG_SPL_NAND_INIT 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SPL_MAX_SIZE (128 << 10) 65 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 67 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 68 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 69 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 70 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 71 #elif defined(CONFIG_SPL_BUILD) 72 #define CONFIG_SPL_INIT_MINIMAL 73 #define CONFIG_SPL_FLUSH_IMAGE 74 #define CONFIG_SPL_TEXT_BASE 0xff800000 75 #define CONFIG_SPL_MAX_SIZE 4096 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 77 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 78 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 80 #endif 81 #define CONFIG_SPL_PAD_TO 0x20000 82 #define CONFIG_TPL_PAD_TO 0x20000 83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 84 #define CONFIG_SYS_TEXT_BASE 0x11001000 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 86 #endif 87 88 /* High Level Configuration Options */ 89 #define CONFIG_BOOKE /* BOOKE */ 90 #define CONFIG_E500 /* BOOKE e500 family */ 91 #define CONFIG_MP /* support multiple processors */ 92 93 #ifndef CONFIG_SYS_TEXT_BASE 94 #define CONFIG_SYS_TEXT_BASE 0xeff40000 95 #endif 96 97 #ifndef CONFIG_RESET_VECTOR_ADDRESS 98 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 99 #endif 100 101 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 102 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 103 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 104 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 105 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 106 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 107 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 108 109 #define CONFIG_ENABLE_36BIT_PHYS 110 111 #ifdef CONFIG_PHYS_64BIT 112 #define CONFIG_ADDR_MAP 113 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 117 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 119 120 /* 121 * These can be toggled for performance analysis, otherwise use default. 122 */ 123 #define CONFIG_L2_CACHE 124 #define CONFIG_BTB 125 126 #define CONFIG_SYS_MEMTEST_START 0x00000000 127 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 128 129 #define CONFIG_SYS_CCSRBAR 0xffe00000 130 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 131 132 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 133 SPL code*/ 134 #ifdef CONFIG_SPL_BUILD 135 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 136 #endif 137 138 /* DDR Setup */ 139 #define CONFIG_DDR_SPD 140 #define CONFIG_VERY_BIG_RAM 141 #define CONFIG_SYS_FSL_DDR3 142 143 #ifdef CONFIG_DDR_ECC 144 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 145 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 146 #endif 147 148 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 149 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 150 151 #define CONFIG_NUM_DDR_CONTROLLERS 1 152 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 153 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 154 155 /* I2C addresses of SPD EEPROMs */ 156 #define CONFIG_SYS_SPD_BUS_NUM 1 157 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 158 159 /* These are used when DDR doesn't use SPD. */ 160 #define CONFIG_SYS_SDRAM_SIZE 2048 161 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 162 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 163 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 164 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 165 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 166 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 167 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 168 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 169 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 170 #define CONFIG_SYS_DDR_MODE_1 0x00441221 171 #define CONFIG_SYS_DDR_MODE_2 0x00000000 172 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 173 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 174 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 175 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 176 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 177 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 178 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 179 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 180 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 181 182 /* 183 * Memory map 184 * 185 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 186 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 187 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 188 * 189 * Localbus cacheable (TBD) 190 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 191 * 192 * Localbus non-cacheable 193 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 194 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 195 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 196 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 197 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 198 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 199 */ 200 201 /* 202 * Local Bus Definitions 203 */ 204 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 205 #ifdef CONFIG_PHYS_64BIT 206 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 207 #else 208 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 209 #endif 210 211 #define CONFIG_FLASH_BR_PRELIM \ 212 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 213 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 214 215 #ifdef CONFIG_NAND 216 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 217 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 218 #else 219 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 220 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 221 #endif 222 223 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 224 #define CONFIG_SYS_FLASH_QUIET_TEST 225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 226 227 #define CONFIG_SYS_MAX_FLASH_BANKS 1 228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 229 230 #ifndef CONFIG_SYS_MONITOR_BASE 231 #ifdef CONFIG_SPL_BUILD 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 233 #else 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 235 #endif 236 #endif 237 238 #define CONFIG_FLASH_CFI_DRIVER 239 #define CONFIG_SYS_FLASH_CFI 240 #define CONFIG_SYS_FLASH_EMPTY_INFO 241 242 /* Nand Flash */ 243 #if defined(CONFIG_NAND_FSL_ELBC) 244 #define CONFIG_SYS_NAND_BASE 0xff800000 245 #ifdef CONFIG_PHYS_64BIT 246 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 247 #else 248 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 249 #endif 250 251 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 252 #define CONFIG_SYS_MAX_NAND_DEVICE 1 253 #define CONFIG_CMD_NAND 1 254 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 255 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 256 257 /* NAND flash config */ 258 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 260 | BR_PS_8 /* Port Size = 8 bit */ \ 261 | BR_MS_FCM /* MSEL = FCM */ \ 262 | BR_V) /* valid */ 263 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 264 | OR_FCM_PGS /* Large Page*/ \ 265 | OR_FCM_CSCT \ 266 | OR_FCM_CST \ 267 | OR_FCM_CHT \ 268 | OR_FCM_SCY_1 \ 269 | OR_FCM_TRLX \ 270 | OR_FCM_EHTR) 271 #ifdef CONFIG_NAND 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 274 #else 275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 277 #endif 278 279 #endif /* CONFIG_NAND_FSL_ELBC */ 280 281 #define CONFIG_BOARD_EARLY_INIT_F 282 #define CONFIG_BOARD_EARLY_INIT_R 283 #define CONFIG_MISC_INIT_R 284 #define CONFIG_HWCONFIG 285 286 #define CONFIG_FSL_NGPIXIS 287 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 288 #ifdef CONFIG_PHYS_64BIT 289 #define PIXIS_BASE_PHYS 0xfffdf0000ull 290 #else 291 #define PIXIS_BASE_PHYS PIXIS_BASE 292 #endif 293 294 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 295 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 296 297 #define PIXIS_LBMAP_SWITCH 7 298 #define PIXIS_LBMAP_MASK 0xF0 299 #define PIXIS_LBMAP_ALTBANK 0x20 300 #define PIXIS_SPD 0x07 301 #define PIXIS_SPD_SYSCLK_MASK 0x07 302 #define PIXIS_ELBC_SPI_MASK 0xc0 303 #define PIXIS_SPI 0x80 304 305 #define CONFIG_SYS_INIT_RAM_LOCK 306 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 307 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 308 309 #define CONFIG_SYS_GBL_DATA_OFFSET \ 310 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 311 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 312 313 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 314 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 315 316 /* 317 * Config the L2 Cache as L2 SRAM 318 */ 319 #if defined(CONFIG_SPL_BUILD) 320 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 321 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 322 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 323 #define CONFIG_SYS_L2_SIZE (256 << 10) 324 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 325 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 326 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 327 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 328 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 329 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 330 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 331 #elif defined(CONFIG_NAND) 332 #ifdef CONFIG_TPL_BUILD 333 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 334 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 335 #define CONFIG_SYS_L2_SIZE (256 << 10) 336 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 337 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 338 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 339 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 340 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 341 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 342 #else 343 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 344 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 345 #define CONFIG_SYS_L2_SIZE (256 << 10) 346 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 347 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 348 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 349 #endif 350 #endif 351 #endif 352 353 /* 354 * Serial Port 355 */ 356 #define CONFIG_CONS_INDEX 1 357 #define CONFIG_SYS_NS16550_SERIAL 358 #define CONFIG_SYS_NS16550_REG_SIZE 1 359 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 360 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 361 #define CONFIG_NS16550_MIN_FUNCTIONS 362 #endif 363 364 #define CONFIG_SYS_BAUDRATE_TABLE \ 365 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 366 367 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 368 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 369 370 /* Video */ 371 372 #ifdef CONFIG_FSL_DIU_FB 373 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 374 #define CONFIG_CMD_BMP 375 #define CONFIG_VIDEO_LOGO 376 #define CONFIG_VIDEO_BMP_LOGO 377 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 378 /* 379 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 380 * disable empty flash sector detection, which is I/O-intensive. 381 */ 382 #undef CONFIG_SYS_FLASH_EMPTY_INFO 383 #endif 384 385 #ifndef CONFIG_FSL_DIU_FB 386 #endif 387 388 #ifdef CONFIG_ATI 389 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 390 #define CONFIG_BIOSEMU 391 #define CONFIG_ATI_RADEON_FB 392 #define CONFIG_VIDEO_LOGO 393 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 394 #endif 395 396 /* I2C */ 397 #define CONFIG_SYS_I2C 398 #define CONFIG_SYS_I2C_FSL 399 #define CONFIG_SYS_FSL_I2C_SPEED 400000 400 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 401 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 402 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 403 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 404 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 405 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 406 407 /* 408 * I2C2 EEPROM 409 */ 410 #define CONFIG_ID_EEPROM 411 #define CONFIG_SYS_I2C_EEPROM_NXID 412 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 413 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 414 #define CONFIG_SYS_EEPROM_BUS_NUM 1 415 416 /* 417 * eSPI - Enhanced SPI 418 */ 419 420 #define CONFIG_HARD_SPI 421 422 #define CONFIG_SF_DEFAULT_SPEED 10000000 423 #define CONFIG_SF_DEFAULT_MODE 0 424 425 /* 426 * General PCI 427 * Memory space is mapped 1-1, but I/O space must start from 0. 428 */ 429 430 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 431 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 434 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 435 #else 436 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 437 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 438 #endif 439 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 440 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 441 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 444 #else 445 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 446 #endif 447 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 448 449 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 450 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 453 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 454 #else 455 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 456 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 457 #endif 458 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 459 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 460 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 463 #else 464 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 465 #endif 466 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 467 468 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 469 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 472 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 473 #else 474 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 475 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 476 #endif 477 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 478 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 479 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 482 #else 483 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 484 #endif 485 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 486 487 #ifdef CONFIG_PCI 488 #define CONFIG_PCI_INDIRECT_BRIDGE 489 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 490 #endif 491 492 /* SATA */ 493 #define CONFIG_LIBATA 494 #define CONFIG_FSL_SATA 495 #define CONFIG_FSL_SATA_V2 496 497 #define CONFIG_SYS_SATA_MAX_DEVICE 2 498 #define CONFIG_SATA1 499 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 500 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 501 #define CONFIG_SATA2 502 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 503 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 504 505 #ifdef CONFIG_FSL_SATA 506 #define CONFIG_LBA48 507 #define CONFIG_CMD_SATA 508 #define CONFIG_DOS_PARTITION 509 #endif 510 511 #ifdef CONFIG_MMC 512 #define CONFIG_FSL_ESDHC 513 #define CONFIG_GENERIC_MMC 514 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 515 #endif 516 517 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 518 #define CONFIG_DOS_PARTITION 519 #endif 520 521 #define CONFIG_TSEC_ENET 522 #ifdef CONFIG_TSEC_ENET 523 524 #define CONFIG_TSECV2 525 526 #define CONFIG_MII /* MII PHY management */ 527 #define CONFIG_TSEC1 1 528 #define CONFIG_TSEC1_NAME "eTSEC1" 529 #define CONFIG_TSEC2 1 530 #define CONFIG_TSEC2_NAME "eTSEC2" 531 532 #define TSEC1_PHY_ADDR 1 533 #define TSEC2_PHY_ADDR 2 534 535 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 536 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 537 538 #define TSEC1_PHYIDX 0 539 #define TSEC2_PHYIDX 0 540 541 #define CONFIG_ETHPRIME "eTSEC1" 542 543 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 544 #endif 545 546 /* 547 * Dynamic MTD Partition support with mtdparts 548 */ 549 #define CONFIG_MTD_DEVICE 550 #define CONFIG_MTD_PARTITIONS 551 #define CONFIG_CMD_MTDPARTS 552 #define CONFIG_FLASH_CFI_MTD 553 #ifdef CONFIG_PHYS_64BIT 554 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 555 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 556 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 557 "512k(dtb),768k(u-boot)" 558 #else 559 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 560 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 561 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 562 "512k(dtb),768k(u-boot)" 563 #endif 564 565 /* 566 * Environment 567 */ 568 #ifdef CONFIG_SPIFLASH 569 #define CONFIG_ENV_IS_IN_SPI_FLASH 570 #define CONFIG_ENV_SPI_BUS 0 571 #define CONFIG_ENV_SPI_CS 0 572 #define CONFIG_ENV_SPI_MAX_HZ 10000000 573 #define CONFIG_ENV_SPI_MODE 0 574 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 575 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 576 #define CONFIG_ENV_SECT_SIZE 0x10000 577 #elif defined(CONFIG_SDCARD) 578 #define CONFIG_ENV_IS_IN_MMC 579 #define CONFIG_FSL_FIXED_MMC_LOCATION 580 #define CONFIG_ENV_SIZE 0x2000 581 #define CONFIG_SYS_MMC_ENV_DEV 0 582 #elif defined(CONFIG_NAND) 583 #ifdef CONFIG_TPL_BUILD 584 #define CONFIG_ENV_SIZE 0x2000 585 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 586 #else 587 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 588 #endif 589 #define CONFIG_ENV_IS_IN_NAND 590 #define CONFIG_ENV_OFFSET (1024 * 1024) 591 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 592 #elif defined(CONFIG_SYS_RAMBOOT) 593 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 594 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 595 #define CONFIG_ENV_SIZE 0x2000 596 #else 597 #define CONFIG_ENV_IS_IN_FLASH 598 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 599 #define CONFIG_ENV_SIZE 0x2000 600 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 601 #endif 602 603 #define CONFIG_LOADS_ECHO 604 #define CONFIG_SYS_LOADS_BAUD_CHANGE 605 606 /* 607 * Command line configuration. 608 */ 609 #define CONFIG_CMD_ERRATA 610 #define CONFIG_CMD_IRQ 611 #define CONFIG_CMD_REGINFO 612 613 #ifdef CONFIG_PCI 614 #define CONFIG_CMD_PCI 615 #endif 616 617 /* 618 * USB 619 */ 620 #define CONFIG_HAS_FSL_DR_USB 621 #ifdef CONFIG_HAS_FSL_DR_USB 622 #define CONFIG_USB_EHCI 623 624 #ifdef CONFIG_USB_EHCI 625 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 626 #define CONFIG_USB_EHCI_FSL 627 #endif 628 #endif 629 630 /* 631 * Miscellaneous configurable options 632 */ 633 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 634 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 635 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 636 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 637 #ifdef CONFIG_CMD_KGDB 638 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 639 #else 640 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 641 #endif 642 /* Print Buffer Size */ 643 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 644 #define CONFIG_SYS_MAXARGS 16 645 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 646 647 /* 648 * For booting Linux, the board info and command line data 649 * have to be in the first 64 MB of memory, since this is 650 * the maximum mapped by the Linux kernel during initialization. 651 */ 652 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 653 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 654 655 #ifdef CONFIG_CMD_KGDB 656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 657 #endif 658 659 /* 660 * Environment Configuration 661 */ 662 663 #define CONFIG_HOSTNAME p1022ds 664 #define CONFIG_ROOTPATH "/opt/nfsroot" 665 #define CONFIG_BOOTFILE "uImage" 666 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 667 668 #define CONFIG_LOADADDR 1000000 669 670 671 #define CONFIG_BAUDRATE 115200 672 673 #define CONFIG_EXTRA_ENV_SETTINGS \ 674 "netdev=eth0\0" \ 675 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 676 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 677 "tftpflash=tftpboot $loadaddr $uboot && " \ 678 "protect off $ubootaddr +$filesize && " \ 679 "erase $ubootaddr +$filesize && " \ 680 "cp.b $loadaddr $ubootaddr $filesize && " \ 681 "protect on $ubootaddr +$filesize && " \ 682 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 683 "consoledev=ttyS0\0" \ 684 "ramdiskaddr=2000000\0" \ 685 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 686 "fdtaddr=1e00000\0" \ 687 "fdtfile=p1022ds.dtb\0" \ 688 "bdev=sda3\0" \ 689 "hwconfig=esdhc;audclk:12\0" 690 691 #define CONFIG_HDBOOT \ 692 "setenv bootargs root=/dev/$bdev rw " \ 693 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 694 "tftp $loadaddr $bootfile;" \ 695 "tftp $fdtaddr $fdtfile;" \ 696 "bootm $loadaddr - $fdtaddr" 697 698 #define CONFIG_NFSBOOTCOMMAND \ 699 "setenv bootargs root=/dev/nfs rw " \ 700 "nfsroot=$serverip:$rootpath " \ 701 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 702 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 703 "tftp $loadaddr $bootfile;" \ 704 "tftp $fdtaddr $fdtfile;" \ 705 "bootm $loadaddr - $fdtaddr" 706 707 #define CONFIG_RAMBOOTCOMMAND \ 708 "setenv bootargs root=/dev/ram rw " \ 709 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 710 "tftp $ramdiskaddr $ramdiskfile;" \ 711 "tftp $loadaddr $bootfile;" \ 712 "tftp $fdtaddr $fdtfile;" \ 713 "bootm $loadaddr $ramdiskaddr $fdtaddr" 714 715 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 716 717 #endif 718