1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_SDCARD 15 #define CONFIG_SPL_FLUSH_IMAGE 16 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 17 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 18 #define CONFIG_SPL_PAD_TO 0x20000 19 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 20 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 21 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 22 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 23 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 24 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 25 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 26 #define CONFIG_SPL_MMC_BOOT 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_SPL_COMMON_INIT_DDR 29 #endif 30 #endif 31 32 #ifdef CONFIG_SPIFLASH 33 #define CONFIG_SPL_SPI_FLASH_MINIMAL 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 36 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 37 #define CONFIG_SPL_PAD_TO 0x20000 38 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 43 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 44 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 45 #define CONFIG_SPL_SPI_BOOT 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_SPL_COMMON_INIT_DDR 48 #endif 49 #endif 50 51 #define CONFIG_NAND_FSL_ELBC 52 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 53 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 54 55 #ifdef CONFIG_NAND 56 #ifdef CONFIG_TPL_BUILD 57 #define CONFIG_SPL_NAND_BOOT 58 #define CONFIG_SPL_FLUSH_IMAGE 59 #define CONFIG_SPL_NAND_INIT 60 #define CONFIG_SPL_COMMON_INIT_DDR 61 #define CONFIG_SPL_MAX_SIZE (128 << 10) 62 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 64 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 65 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 66 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 67 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 68 #elif defined(CONFIG_SPL_BUILD) 69 #define CONFIG_SPL_INIT_MINIMAL 70 #define CONFIG_SPL_FLUSH_IMAGE 71 #define CONFIG_SPL_TEXT_BASE 0xff800000 72 #define CONFIG_SPL_MAX_SIZE 4096 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 74 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 75 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 77 #endif 78 #define CONFIG_SPL_PAD_TO 0x20000 79 #define CONFIG_TPL_PAD_TO 0x20000 80 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 82 #endif 83 84 /* High Level Configuration Options */ 85 #define CONFIG_MP /* support multiple processors */ 86 87 #ifndef CONFIG_RESET_VECTOR_ADDRESS 88 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 89 #endif 90 91 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 92 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 93 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 94 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 95 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 96 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 97 98 #define CONFIG_ENABLE_36BIT_PHYS 99 100 #ifdef CONFIG_PHYS_64BIT 101 #define CONFIG_ADDR_MAP 102 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 103 #endif 104 105 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 106 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 107 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_L2_CACHE 113 #define CONFIG_BTB 114 115 #define CONFIG_SYS_MEMTEST_START 0x00000000 116 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 117 118 #define CONFIG_SYS_CCSRBAR 0xffe00000 119 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 120 121 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 122 SPL code*/ 123 #ifdef CONFIG_SPL_BUILD 124 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 125 #endif 126 127 /* DDR Setup */ 128 #define CONFIG_DDR_SPD 129 #define CONFIG_VERY_BIG_RAM 130 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 138 139 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 140 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 141 142 /* I2C addresses of SPD EEPROMs */ 143 #define CONFIG_SYS_SPD_BUS_NUM 1 144 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 145 146 /* These are used when DDR doesn't use SPD. */ 147 #define CONFIG_SYS_SDRAM_SIZE 2048 148 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 149 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 150 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 151 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 152 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 153 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 154 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 155 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 156 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 157 #define CONFIG_SYS_DDR_MODE_1 0x00441221 158 #define CONFIG_SYS_DDR_MODE_2 0x00000000 159 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 160 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 161 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 162 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 163 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 164 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 165 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 166 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 167 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 168 169 /* 170 * Memory map 171 * 172 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 173 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 174 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 175 * 176 * Localbus cacheable (TBD) 177 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 178 * 179 * Localbus non-cacheable 180 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 181 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 182 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 183 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 184 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 185 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 186 */ 187 188 /* 189 * Local Bus Definitions 190 */ 191 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 192 #ifdef CONFIG_PHYS_64BIT 193 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 194 #else 195 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 196 #endif 197 198 #define CONFIG_FLASH_BR_PRELIM \ 199 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 200 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 201 202 #ifdef CONFIG_NAND 203 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 204 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 205 #else 206 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 207 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 208 #endif 209 210 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 211 #define CONFIG_SYS_FLASH_QUIET_TEST 212 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 215 #define CONFIG_SYS_MAX_FLASH_SECT 1024 216 217 #ifndef CONFIG_SYS_MONITOR_BASE 218 #ifdef CONFIG_SPL_BUILD 219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 220 #else 221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 222 #endif 223 #endif 224 225 #define CONFIG_FLASH_CFI_DRIVER 226 #define CONFIG_SYS_FLASH_CFI 227 #define CONFIG_SYS_FLASH_EMPTY_INFO 228 229 /* Nand Flash */ 230 #if defined(CONFIG_NAND_FSL_ELBC) 231 #define CONFIG_SYS_NAND_BASE 0xff800000 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 234 #else 235 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 236 #endif 237 238 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 239 #define CONFIG_SYS_MAX_NAND_DEVICE 1 240 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 241 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 242 243 /* NAND flash config */ 244 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 245 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 246 | BR_PS_8 /* Port Size = 8 bit */ \ 247 | BR_MS_FCM /* MSEL = FCM */ \ 248 | BR_V) /* valid */ 249 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 250 | OR_FCM_PGS /* Large Page*/ \ 251 | OR_FCM_CSCT \ 252 | OR_FCM_CST \ 253 | OR_FCM_CHT \ 254 | OR_FCM_SCY_1 \ 255 | OR_FCM_TRLX \ 256 | OR_FCM_EHTR) 257 #ifdef CONFIG_NAND 258 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 259 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 260 #else 261 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 262 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 263 #endif 264 265 #endif /* CONFIG_NAND_FSL_ELBC */ 266 267 #define CONFIG_MISC_INIT_R 268 #define CONFIG_HWCONFIG 269 270 #define CONFIG_FSL_NGPIXIS 271 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 272 #ifdef CONFIG_PHYS_64BIT 273 #define PIXIS_BASE_PHYS 0xfffdf0000ull 274 #else 275 #define PIXIS_BASE_PHYS PIXIS_BASE 276 #endif 277 278 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 279 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 280 281 #define PIXIS_LBMAP_SWITCH 7 282 #define PIXIS_LBMAP_MASK 0xF0 283 #define PIXIS_LBMAP_ALTBANK 0x20 284 #define PIXIS_SPD 0x07 285 #define PIXIS_SPD_SYSCLK_MASK 0x07 286 #define PIXIS_ELBC_SPI_MASK 0xc0 287 #define PIXIS_SPI 0x80 288 289 #define CONFIG_SYS_INIT_RAM_LOCK 290 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 291 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 292 293 #define CONFIG_SYS_GBL_DATA_OFFSET \ 294 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 295 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 296 297 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 298 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 299 300 /* 301 * Config the L2 Cache as L2 SRAM 302 */ 303 #if defined(CONFIG_SPL_BUILD) 304 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 305 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 306 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 307 #define CONFIG_SYS_L2_SIZE (256 << 10) 308 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 309 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 310 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 311 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 312 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 313 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 314 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 315 #elif defined(CONFIG_NAND) 316 #ifdef CONFIG_TPL_BUILD 317 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 318 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 319 #define CONFIG_SYS_L2_SIZE (256 << 10) 320 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 321 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 322 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 323 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 324 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 325 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 326 #else 327 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 328 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 329 #define CONFIG_SYS_L2_SIZE (256 << 10) 330 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 331 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 332 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 333 #endif 334 #endif 335 #endif 336 337 /* 338 * Serial Port 339 */ 340 #define CONFIG_SYS_NS16550_SERIAL 341 #define CONFIG_SYS_NS16550_REG_SIZE 1 342 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 343 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 344 #define CONFIG_NS16550_MIN_FUNCTIONS 345 #endif 346 347 #define CONFIG_SYS_BAUDRATE_TABLE \ 348 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 349 350 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 351 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 352 353 /* Video */ 354 355 #ifdef CONFIG_FSL_DIU_FB 356 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 357 #define CONFIG_VIDEO_LOGO 358 #define CONFIG_VIDEO_BMP_LOGO 359 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 360 /* 361 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 362 * disable empty flash sector detection, which is I/O-intensive. 363 */ 364 #undef CONFIG_SYS_FLASH_EMPTY_INFO 365 #endif 366 367 #ifndef CONFIG_FSL_DIU_FB 368 #endif 369 370 #ifdef CONFIG_ATI 371 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 372 #define CONFIG_BIOSEMU 373 #define CONFIG_ATI_RADEON_FB 374 #define CONFIG_VIDEO_LOGO 375 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 376 #endif 377 378 /* I2C */ 379 #define CONFIG_SYS_I2C 380 #define CONFIG_SYS_I2C_FSL 381 #define CONFIG_SYS_FSL_I2C_SPEED 400000 382 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 383 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 384 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 385 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 386 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 387 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 388 389 /* 390 * I2C2 EEPROM 391 */ 392 #define CONFIG_ID_EEPROM 393 #define CONFIG_SYS_I2C_EEPROM_NXID 394 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 395 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 396 #define CONFIG_SYS_EEPROM_BUS_NUM 1 397 398 /* 399 * eSPI - Enhanced SPI 400 */ 401 402 #define CONFIG_HARD_SPI 403 404 #define CONFIG_SF_DEFAULT_SPEED 10000000 405 #define CONFIG_SF_DEFAULT_MODE 0 406 407 /* 408 * General PCI 409 * Memory space is mapped 1-1, but I/O space must start from 0. 410 */ 411 412 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 413 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 416 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 417 #else 418 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 419 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 420 #endif 421 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 422 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 423 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 426 #else 427 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 428 #endif 429 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 430 431 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 432 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 435 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 436 #else 437 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 438 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 439 #endif 440 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 441 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 442 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 445 #else 446 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 447 #endif 448 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 449 450 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 451 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 454 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 455 #else 456 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 457 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 458 #endif 459 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 460 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 461 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 464 #else 465 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 466 #endif 467 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 468 469 #ifdef CONFIG_PCI 470 #define CONFIG_PCI_INDIRECT_BRIDGE 471 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 472 #endif 473 474 /* SATA */ 475 #define CONFIG_FSL_SATA_V2 476 477 #define CONFIG_SYS_SATA_MAX_DEVICE 2 478 #define CONFIG_SATA1 479 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 480 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 481 #define CONFIG_SATA2 482 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 483 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 484 485 #ifdef CONFIG_FSL_SATA 486 #define CONFIG_LBA48 487 #endif 488 489 #ifdef CONFIG_MMC 490 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 491 #endif 492 493 #ifdef CONFIG_TSEC_ENET 494 495 #define CONFIG_TSECV2 496 497 #define CONFIG_MII /* MII PHY management */ 498 #define CONFIG_TSEC1 1 499 #define CONFIG_TSEC1_NAME "eTSEC1" 500 #define CONFIG_TSEC2 1 501 #define CONFIG_TSEC2_NAME "eTSEC2" 502 503 #define TSEC1_PHY_ADDR 1 504 #define TSEC2_PHY_ADDR 2 505 506 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 507 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 508 509 #define TSEC1_PHYIDX 0 510 #define TSEC2_PHYIDX 0 511 512 #define CONFIG_ETHPRIME "eTSEC1" 513 #endif 514 515 /* 516 * Dynamic MTD Partition support with mtdparts 517 */ 518 #define CONFIG_MTD_DEVICE 519 #define CONFIG_MTD_PARTITIONS 520 #define CONFIG_FLASH_CFI_MTD 521 522 /* 523 * Environment 524 */ 525 #ifdef CONFIG_SPIFLASH 526 #define CONFIG_ENV_SPI_BUS 0 527 #define CONFIG_ENV_SPI_CS 0 528 #define CONFIG_ENV_SPI_MAX_HZ 10000000 529 #define CONFIG_ENV_SPI_MODE 0 530 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 531 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 532 #define CONFIG_ENV_SECT_SIZE 0x10000 533 #elif defined(CONFIG_SDCARD) 534 #define CONFIG_FSL_FIXED_MMC_LOCATION 535 #define CONFIG_ENV_SIZE 0x2000 536 #define CONFIG_SYS_MMC_ENV_DEV 0 537 #elif defined(CONFIG_NAND) 538 #ifdef CONFIG_TPL_BUILD 539 #define CONFIG_ENV_SIZE 0x2000 540 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 541 #else 542 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 543 #endif 544 #define CONFIG_ENV_OFFSET (1024 * 1024) 545 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 546 #elif defined(CONFIG_SYS_RAMBOOT) 547 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 548 #define CONFIG_ENV_SIZE 0x2000 549 #else 550 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 551 #define CONFIG_ENV_SIZE 0x2000 552 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 553 #endif 554 555 #define CONFIG_LOADS_ECHO 556 #define CONFIG_SYS_LOADS_BAUD_CHANGE 557 558 /* 559 * USB 560 */ 561 #define CONFIG_HAS_FSL_DR_USB 562 #ifdef CONFIG_HAS_FSL_DR_USB 563 #ifdef CONFIG_USB_EHCI_HCD 564 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 565 #define CONFIG_USB_EHCI_FSL 566 #endif 567 #endif 568 569 /* 570 * Miscellaneous configurable options 571 */ 572 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 573 574 /* 575 * For booting Linux, the board info and command line data 576 * have to be in the first 64 MB of memory, since this is 577 * the maximum mapped by the Linux kernel during initialization. 578 */ 579 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 580 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 581 582 #ifdef CONFIG_CMD_KGDB 583 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 584 #endif 585 586 /* 587 * Environment Configuration 588 */ 589 590 #define CONFIG_HOSTNAME "p1022ds" 591 #define CONFIG_ROOTPATH "/opt/nfsroot" 592 #define CONFIG_BOOTFILE "uImage" 593 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 594 595 #define CONFIG_LOADADDR 1000000 596 597 #define CONFIG_EXTRA_ENV_SETTINGS \ 598 "netdev=eth0\0" \ 599 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 600 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 601 "tftpflash=tftpboot $loadaddr $uboot && " \ 602 "protect off $ubootaddr +$filesize && " \ 603 "erase $ubootaddr +$filesize && " \ 604 "cp.b $loadaddr $ubootaddr $filesize && " \ 605 "protect on $ubootaddr +$filesize && " \ 606 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 607 "consoledev=ttyS0\0" \ 608 "ramdiskaddr=2000000\0" \ 609 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 610 "fdtaddr=1e00000\0" \ 611 "fdtfile=p1022ds.dtb\0" \ 612 "bdev=sda3\0" \ 613 "hwconfig=esdhc;audclk:12\0" 614 615 #define CONFIG_HDBOOT \ 616 "setenv bootargs root=/dev/$bdev rw " \ 617 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 618 "tftp $loadaddr $bootfile;" \ 619 "tftp $fdtaddr $fdtfile;" \ 620 "bootm $loadaddr - $fdtaddr" 621 622 #define CONFIG_NFSBOOTCOMMAND \ 623 "setenv bootargs root=/dev/nfs rw " \ 624 "nfsroot=$serverip:$rootpath " \ 625 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 626 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 627 "tftp $loadaddr $bootfile;" \ 628 "tftp $fdtaddr $fdtfile;" \ 629 "bootm $loadaddr - $fdtaddr" 630 631 #define CONFIG_RAMBOOTCOMMAND \ 632 "setenv bootargs root=/dev/ram rw " \ 633 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 634 "tftp $ramdiskaddr $ramdiskfile;" \ 635 "tftp $loadaddr $bootfile;" \ 636 "tftp $fdtaddr $fdtfile;" \ 637 "bootm $loadaddr $ramdiskaddr $fdtaddr" 638 639 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 640 641 #endif 642