xref: /openbmc/u-boot/include/configs/P1022DS.h (revision 67cd4a63487400317f1586b130bc2475767a5315)
1 /*
2  * Copyright 2010-2012 Freescale Semiconductor, Inc.
3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4  *          Timur Tabi <timur@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the Free
8  * Software Foundation; either version 2 of the License, or (at your option)
9  * any later version.
10  */
11 
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14 
15 #include "../board/freescale/common/ics307_clk.h"
16 
17 #ifdef CONFIG_36BIT
18 #define CONFIG_PHYS_64BIT
19 #endif
20 
21 #ifdef CONFIG_SDCARD
22 #define CONFIG_RAMBOOT_SDCARD
23 #define CONFIG_SYS_RAMBOOT
24 #define CONFIG_SYS_EXTRA_ENV_RELOC
25 #define CONFIG_SYS_TEXT_BASE		0x11000000
26 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
27 #endif
28 
29 #ifdef CONFIG_SPIFLASH
30 #define CONFIG_RAMBOOT_SPIFLASH
31 #define CONFIG_SYS_RAMBOOT
32 #define CONFIG_SYS_EXTRA_ENV_RELOC
33 #define CONFIG_SYS_TEXT_BASE		0x11000000
34 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
35 #endif
36 
37 #define CONFIG_NAND_FSL_ELBC
38 
39 #ifdef CONFIG_NAND
40 #define CONFIG_SPL
41 #define CONFIG_SPL_INIT_MINIMAL
42 #define CONFIG_SPL_SERIAL_SUPPORT
43 #define CONFIG_SPL_NAND_SUPPORT
44 #define CONFIG_SPL_NAND_MINIMAL
45 #define CONFIG_SPL_FLUSH_IMAGE
46 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
47 
48 #define CONFIG_SYS_TEXT_BASE           0x00201000
49 #define CONFIG_SPL_TEXT_BASE           0xfffff000
50 #define CONFIG_SPL_MAX_SIZE            4096
51 #define CONFIG_SPL_RELOC_TEXT_BASE     0x00100000
52 #define CONFIG_SPL_RELOC_STACK         0x00100000
53 #define CONFIG_SYS_NAND_U_BOOT_SIZE    ((512 << 10) + CONFIG_SPL_MAX_SIZE)
54 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x00200000 - CONFIG_SPL_MAX_SIZE)
55 #define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
56 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0
57 #define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
58 #endif
59 
60 /* High Level Configuration Options */
61 #define CONFIG_BOOKE			/* BOOKE */
62 #define CONFIG_E500			/* BOOKE e500 family */
63 #define CONFIG_MPC85xx			/* MPC8540/60/55/41/48 */
64 #define CONFIG_P1022
65 #define CONFIG_P1022DS
66 #define CONFIG_MP			/* support multiple processors */
67 
68 #ifndef CONFIG_SYS_TEXT_BASE
69 #define CONFIG_SYS_TEXT_BASE	0xeff80000
70 #endif
71 
72 #ifndef CONFIG_RESET_VECTOR_ADDRESS
73 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
74 #endif
75 
76 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
77 #define CONFIG_PCI			/* Enable PCI/PCIE */
78 #define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
79 #define CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
80 #define CONFIG_PCIE3			/* PCIE controler 3 (ULI bridge) */
81 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
82 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
83 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
84 
85 #define CONFIG_ENABLE_36BIT_PHYS
86 
87 #ifdef CONFIG_PHYS_64BIT
88 #define CONFIG_ADDR_MAP
89 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
90 #endif
91 
92 #define CONFIG_FSL_LAW			/* Use common FSL init code */
93 
94 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
95 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
96 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
97 
98 /*
99  * These can be toggled for performance analysis, otherwise use default.
100  */
101 #define CONFIG_L2_CACHE
102 #define CONFIG_BTB
103 
104 #define CONFIG_SYS_MEMTEST_START	0x00000000
105 #define CONFIG_SYS_MEMTEST_END		0x7fffffff
106 
107 #define CONFIG_SYS_CCSRBAR		0xffe00000
108 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
109 
110 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
111        SPL code*/
112 #ifdef CONFIG_SPL_BUILD
113 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
114 #endif
115 
116 
117 /* DDR Setup */
118 #define CONFIG_DDR_SPD
119 #define CONFIG_VERY_BIG_RAM
120 #define CONFIG_FSL_DDR3
121 
122 #ifdef CONFIG_DDR_ECC
123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
124 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
125 #endif
126 
127 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
128 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
129 
130 #define CONFIG_NUM_DDR_CONTROLLERS	1
131 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
132 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
133 
134 /* I2C addresses of SPD EEPROMs */
135 #define CONFIG_SYS_SPD_BUS_NUM		1
136 #define SPD_EEPROM_ADDRESS		0x51	/* CTLR 0 DIMM 0 */
137 
138 /* These are used when DDR doesn't use SPD.  */
139 #define CONFIG_SYS_SDRAM_SIZE		2048
140 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
141 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
142 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
143 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007F
144 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014202
145 #define CONFIG_SYS_DDR_TIMING_3		0x00010000
146 #define CONFIG_SYS_DDR_TIMING_0		0x40110104
147 #define CONFIG_SYS_DDR_TIMING_1		0x5c5bd746
148 #define CONFIG_SYS_DDR_TIMING_2		0x0fa8d4ca
149 #define CONFIG_SYS_DDR_MODE_1		0x00441221
150 #define CONFIG_SYS_DDR_MODE_2		0x00000000
151 #define CONFIG_SYS_DDR_INTERVAL		0x0a280100
152 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
153 #define CONFIG_SYS_DDR_CLK_CTRL		0x02800000
154 #define CONFIG_SYS_DDR_CONTROL		0xc7000008
155 #define CONFIG_SYS_DDR_CONTROL_2	0x24401041
156 #define	CONFIG_SYS_DDR_TIMING_4		0x00220001
157 #define	CONFIG_SYS_DDR_TIMING_5		0x02401400
158 #define	CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
159 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
160 
161 
162 /*
163  * Memory map
164  *
165  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
166  * 0x8000_0000	0xdfff_ffff	PCI Express Mem		1.5G non-cacheable
167  * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
168  *
169  * Localbus cacheable (TBD)
170  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
171  *
172  * Localbus non-cacheable
173  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
174  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
175  * 0xff80_0000	0xff80_7fff	NAND			32K non-cacheable
176  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
177  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
178  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
179  */
180 
181 /*
182  * Local Bus Definitions
183  */
184 #define CONFIG_SYS_FLASH_BASE		0xe8000000 /* start of FLASH 128M */
185 #ifdef CONFIG_PHYS_64BIT
186 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe8000000ull
187 #else
188 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
189 #endif
190 
191 #define CONFIG_FLASH_BR_PRELIM  \
192 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
193 #define CONFIG_FLASH_OR_PRELIM	(OR_AM_128MB | 0xff7)
194 
195 #ifdef CONFIG_NAND
196 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
197 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
198 #else
199 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
200 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM  /* NOR Options */
201 #endif
202 
203 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
204 #define CONFIG_SYS_FLASH_QUIET_TEST
205 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
206 
207 #define CONFIG_SYS_MAX_FLASH_BANKS	1
208 #define CONFIG_SYS_MAX_FLASH_SECT	1024
209 
210 #ifndef CONFIG_SYS_MONITOR_BASE
211 #ifdef CONFIG_SPL_BUILD
212 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
213 #else
214 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
215 #endif
216 #endif
217 
218 #define CONFIG_FLASH_CFI_DRIVER
219 #define CONFIG_SYS_FLASH_CFI
220 #define CONFIG_SYS_FLASH_EMPTY_INFO
221 
222 /* Nand Flash */
223 #if defined(CONFIG_NAND_FSL_ELBC)
224 #define CONFIG_SYS_NAND_BASE		0xff800000
225 #ifdef CONFIG_PHYS_64BIT
226 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
227 #else
228 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
229 #endif
230 
231 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE, }
232 #define CONFIG_SYS_MAX_NAND_DEVICE	1
233 #define CONFIG_MTD_NAND_VERIFY_WRITE
234 #define CONFIG_CMD_NAND			1
235 #define CONFIG_SYS_NAND_BLOCK_SIZE    (256 * 1024)
236 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
237 
238 /* NAND flash config */
239 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
240 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
241 			       | BR_PS_8	       /* Port Size = 8 bit */ \
242 			       | BR_MS_FCM	       /* MSEL = FCM */ \
243 			       | BR_V)		       /* valid */
244 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB	       /* length 256K */ \
245 			       | OR_FCM_PGS	       /* Large Page*/ \
246 			       | OR_FCM_CSCT \
247 			       | OR_FCM_CST \
248 			       | OR_FCM_CHT \
249 			       | OR_FCM_SCY_1 \
250 			       | OR_FCM_TRLX \
251 			       | OR_FCM_EHTR)
252 #ifdef CONFIG_NAND
253 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
254 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
255 #else
256 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
257 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
258 #endif
259 
260 #endif /* CONFIG_NAND_FSL_ELBC */
261 
262 #define CONFIG_BOARD_EARLY_INIT_F
263 #define CONFIG_BOARD_EARLY_INIT_R
264 #define CONFIG_MISC_INIT_R
265 #define CONFIG_HWCONFIG
266 
267 #define CONFIG_FSL_NGPIXIS
268 #define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
269 #ifdef CONFIG_PHYS_64BIT
270 #define PIXIS_BASE_PHYS		0xfffdf0000ull
271 #else
272 #define PIXIS_BASE_PHYS		PIXIS_BASE
273 #endif
274 
275 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
276 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB | 0x6ff7)
277 
278 #define PIXIS_LBMAP_SWITCH	7
279 #define PIXIS_LBMAP_MASK	0xF0
280 #define PIXIS_LBMAP_ALTBANK	0x20
281 #define PIXIS_SPD		0x07
282 #define PIXIS_SPD_SYSCLK_MASK	0x07
283 #define PIXIS_ELBC_SPI_MASK	0xc0
284 #define PIXIS_SPI		0x80
285 
286 #define CONFIG_SYS_INIT_RAM_LOCK
287 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
288 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */
289 
290 #define CONFIG_SYS_GBL_DATA_OFFSET	\
291 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
292 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
293 
294 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
295 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
296 
297 /*
298  * Serial Port
299  */
300 #define CONFIG_CONS_INDEX		1
301 #define CONFIG_SYS_NS16550
302 #define CONFIG_SYS_NS16550_SERIAL
303 #define CONFIG_SYS_NS16550_REG_SIZE	1
304 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
305 #ifdef CONFIG_SPL_BUILD
306 #define CONFIG_NS16550_MIN_FUNCTIONS
307 #endif
308 
309 #define CONFIG_SYS_BAUDRATE_TABLE	\
310 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
311 
312 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
313 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
314 
315 /* Use the HUSH parser */
316 #define CONFIG_SYS_HUSH_PARSER
317 
318 /* Video */
319 
320 #ifdef CONFIG_FSL_DIU_FB
321 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
322 #define CONFIG_VIDEO
323 #define CONFIG_CMD_BMP
324 #define CONFIG_CFB_CONSOLE
325 #define CONFIG_VIDEO_SW_CURSOR
326 #define CONFIG_VGA_AS_SINGLE_DEVICE
327 #define CONFIG_VIDEO_LOGO
328 #define CONFIG_VIDEO_BMP_LOGO
329 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
330 /*
331  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
332  * disable empty flash sector detection, which is I/O-intensive.
333  */
334 #undef CONFIG_SYS_FLASH_EMPTY_INFO
335 #endif
336 
337 #ifndef CONFIG_FSL_DIU_FB
338 #endif
339 
340 #ifdef CONFIG_ATI
341 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
342 #define CONFIG_VIDEO
343 #define CONFIG_BIOSEMU
344 #define CONFIG_VIDEO_SW_CURSOR
345 #define CONFIG_ATI_RADEON_FB
346 #define CONFIG_VIDEO_LOGO
347 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
348 #define CONFIG_CFB_CONSOLE
349 #define CONFIG_VGA_AS_SINGLE_DEVICE
350 #endif
351 
352 /*
353  * Pass open firmware flat tree
354  */
355 #define CONFIG_OF_LIBFDT
356 #define CONFIG_OF_BOARD_SETUP
357 #define CONFIG_OF_STDOUT_VIA_ALIAS
358 
359 /* new uImage format support */
360 #define CONFIG_FIT
361 #define CONFIG_FIT_VERBOSE
362 
363 /* I2C */
364 #define CONFIG_FSL_I2C
365 #define CONFIG_HARD_I2C
366 #define CONFIG_I2C_MULTI_BUS
367 #define CONFIG_SYS_I2C_SPEED		400000
368 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
369 #define CONFIG_SYS_I2C_SLAVE		0x7F
370 #define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
371 #define CONFIG_SYS_I2C_OFFSET		0x3000
372 #define CONFIG_SYS_I2C2_OFFSET		0x3100
373 
374 /*
375  * I2C2 EEPROM
376  */
377 #define CONFIG_ID_EEPROM
378 #define CONFIG_SYS_I2C_EEPROM_NXID
379 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
380 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
381 #define CONFIG_SYS_EEPROM_BUS_NUM	1
382 
383 /*
384  * eSPI - Enhanced SPI
385  */
386 #define CONFIG_SPI_FLASH
387 #define CONFIG_SPI_FLASH_SPANSION
388 
389 #define CONFIG_HARD_SPI
390 #define CONFIG_FSL_ESPI
391 
392 #define CONFIG_CMD_SF
393 #define CONFIG_SF_DEFAULT_SPEED		10000000
394 #define CONFIG_SF_DEFAULT_MODE		0
395 
396 /*
397  * General PCI
398  * Memory space is mapped 1-1, but I/O space must start from 0.
399  */
400 
401 /* controller 1, Slot 2, tgtid 1, Base address a000 */
402 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
405 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
406 #else
407 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
408 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
409 #endif
410 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
411 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
412 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
415 #else
416 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
417 #endif
418 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
419 
420 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
421 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
422 #ifdef CONFIG_PHYS_64BIT
423 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
424 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
425 #else
426 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
427 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
428 #endif
429 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
430 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
431 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
432 #ifdef CONFIG_PHYS_64BIT
433 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
434 #else
435 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
436 #endif
437 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
438 
439 /* controller 3, Slot 1, tgtid 3, Base address b000 */
440 #define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
441 #ifdef CONFIG_PHYS_64BIT
442 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
443 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
444 #else
445 #define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
446 #define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
447 #endif
448 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
449 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
450 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
453 #else
454 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
455 #endif
456 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
457 
458 #ifdef CONFIG_PCI
459 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
460 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
461 #define CONFIG_E1000			/* Define e1000 pci Ethernet card */
462 #endif
463 
464 /* SATA */
465 #define CONFIG_LIBATA
466 #define CONFIG_FSL_SATA
467 #define CONFIG_FSL_SATA_V2
468 
469 #define CONFIG_SYS_SATA_MAX_DEVICE	2
470 #define CONFIG_SATA1
471 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
472 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
473 #define CONFIG_SATA2
474 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
475 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
476 
477 #ifdef CONFIG_FSL_SATA
478 #define CONFIG_LBA48
479 #define CONFIG_CMD_SATA
480 #define CONFIG_DOS_PARTITION
481 #define CONFIG_CMD_EXT2
482 #endif
483 
484 #define CONFIG_MMC
485 #ifdef CONFIG_MMC
486 #define CONFIG_CMD_MMC
487 #define CONFIG_FSL_ESDHC
488 #define CONFIG_GENERIC_MMC
489 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
490 #endif
491 
492 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
493 #define CONFIG_CMD_EXT2
494 #define CONFIG_CMD_FAT
495 #define CONFIG_DOS_PARTITION
496 #endif
497 
498 #define CONFIG_TSEC_ENET
499 #ifdef CONFIG_TSEC_ENET
500 
501 #define CONFIG_TSECV2
502 
503 #define CONFIG_MII			/* MII PHY management */
504 #define CONFIG_TSEC1		1
505 #define CONFIG_TSEC1_NAME	"eTSEC1"
506 #define CONFIG_TSEC2		1
507 #define CONFIG_TSEC2_NAME	"eTSEC2"
508 
509 #define TSEC1_PHY_ADDR		1
510 #define TSEC2_PHY_ADDR		2
511 
512 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
513 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
514 
515 #define TSEC1_PHYIDX		0
516 #define TSEC2_PHYIDX		0
517 
518 #define CONFIG_ETHPRIME		"eTSEC1"
519 
520 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
521 #endif
522 
523 /*
524  * Environment
525  */
526 #ifdef CONFIG_RAMBOOT_SPIFLASH
527 #define CONFIG_ENV_IS_IN_SPI_FLASH
528 #define CONFIG_ENV_SPI_BUS	0
529 #define CONFIG_ENV_SPI_CS	0
530 #define CONFIG_ENV_SPI_MAX_HZ	10000000
531 #define CONFIG_ENV_SPI_MODE	0
532 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
533 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
534 #define CONFIG_ENV_SECT_SIZE	0x10000
535 #elif defined(CONFIG_RAMBOOT_SDCARD)
536 #define CONFIG_ENV_IS_IN_MMC
537 #define CONFIG_ENV_SIZE		0x2000
538 #define CONFIG_SYS_MMC_ENV_DEV	0
539 #elif defined(CONFIG_NAND)
540 #define CONFIG_ENV_IS_IN_NAND
541 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
542 #define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
543 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
544 #elif defined(CONFIG_SYS_RAMBOOT)
545 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
546 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
547 #define CONFIG_ENV_SIZE		0x2000
548 #else
549 #define CONFIG_ENV_IS_IN_FLASH
550 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
551 #define CONFIG_ENV_ADDR	0xfff80000
552 #else
553 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
554 #endif
555 #define CONFIG_ENV_SIZE		0x2000
556 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
557 #endif
558 
559 #define CONFIG_LOADS_ECHO
560 #define CONFIG_SYS_LOADS_BAUD_CHANGE
561 
562 /*
563  * Command line configuration.
564  */
565 #include <config_cmd_default.h>
566 
567 #define CONFIG_CMD_ELF
568 #define CONFIG_CMD_ERRATA
569 #define CONFIG_CMD_IRQ
570 #define CONFIG_CMD_I2C
571 #define CONFIG_CMD_MII
572 #define CONFIG_CMD_PING
573 #define CONFIG_CMD_SETEXPR
574 #define CONFIG_CMD_REGINFO
575 
576 #ifdef CONFIG_PCI
577 #define CONFIG_CMD_PCI
578 #define CONFIG_CMD_NET
579 #endif
580 
581 /*
582  * USB
583  */
584 #define CONFIG_HAS_FSL_DR_USB
585 #ifdef CONFIG_HAS_FSL_DR_USB
586 #define CONFIG_USB_EHCI
587 
588 #ifdef CONFIG_USB_EHCI
589 #define CONFIG_CMD_USB
590 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
591 #define CONFIG_USB_EHCI_FSL
592 #define CONFIG_USB_STORAGE
593 #define CONFIG_CMD_FAT
594 #endif
595 #endif
596 
597 /*
598  * Miscellaneous configurable options
599  */
600 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
601 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
602 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
603 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
604 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
605 #ifdef CONFIG_CMD_KGDB
606 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
607 #else
608 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
609 #endif
610 /* Print Buffer Size */
611 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
612 #define CONFIG_SYS_MAXARGS	16
613 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
614 #define CONFIG_SYS_HZ		1000
615 
616 /*
617  * For booting Linux, the board info and command line data
618  * have to be in the first 64 MB of memory, since this is
619  * the maximum mapped by the Linux kernel during initialization.
620  */
621 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
622 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
623 
624 #ifdef CONFIG_CMD_KGDB
625 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
626 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
627 #endif
628 
629 /*
630  * Environment Configuration
631  */
632 
633 #define CONFIG_HOSTNAME		p1022ds
634 #define CONFIG_ROOTPATH		"/opt/nfsroot"
635 #define CONFIG_BOOTFILE		"uImage"
636 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
637 
638 #define CONFIG_LOADADDR		1000000
639 
640 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
641 
642 #define CONFIG_BAUDRATE	115200
643 
644 #define	CONFIG_EXTRA_ENV_SETTINGS				\
645 	"netdev=eth0\0"						\
646 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
647 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
648 	"tftpflash=tftpboot $loadaddr $uboot && "		\
649 		"protect off $ubootaddr +$filesize && "		\
650 		"erase $ubootaddr +$filesize && "		\
651 		"cp.b $loadaddr $ubootaddr $filesize && "	\
652 		"protect on $ubootaddr +$filesize && "		\
653 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
654 	"consoledev=ttyS0\0"					\
655 	"ramdiskaddr=2000000\0"					\
656 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
657 	"fdtaddr=c00000\0"	  			      	\
658 	"fdtfile=p1022ds.dtb\0"	  				\
659 	"bdev=sda3\0"		  			      	\
660 	"hwconfig=esdhc;audclk:12\0"
661 
662 #define CONFIG_HDBOOT					\
663 	"setenv bootargs root=/dev/$bdev rw "		\
664 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
665 	"tftp $loadaddr $bootfile;"			\
666 	"tftp $fdtaddr $fdtfile;"			\
667 	"bootm $loadaddr - $fdtaddr"
668 
669 #define CONFIG_NFSBOOTCOMMAND						\
670 	"setenv bootargs root=/dev/nfs rw "				\
671 	"nfsroot=$serverip:$rootpath "					\
672 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
673 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
674 	"tftp $loadaddr $bootfile;"					\
675 	"tftp $fdtaddr $fdtfile;"					\
676 	"bootm $loadaddr - $fdtaddr"
677 
678 #define CONFIG_RAMBOOTCOMMAND						\
679 	"setenv bootargs root=/dev/ram rw "				\
680 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
681 	"tftp $ramdiskaddr $ramdiskfile;"				\
682 	"tftp $loadaddr $bootfile;"					\
683 	"tftp $fdtaddr $fdtfile;"					\
684 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
685 
686 #define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
687 
688 #endif
689