1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_SDCARD 15 #define CONFIG_SPL_MMC_MINIMAL 16 #define CONFIG_SPL_FLUSH_IMAGE 17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 18 #define CONFIG_FSL_LAW /* Use common FSL init code */ 19 #define CONFIG_SYS_TEXT_BASE 0x11001000 20 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 21 #define CONFIG_SPL_PAD_TO 0x20000 22 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 28 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 29 #define CONFIG_SPL_MMC_BOOT 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_COMMON_INIT_DDR 32 #endif 33 #endif 34 35 #ifdef CONFIG_SPIFLASH 36 #define CONFIG_SPL_SPI_FLASH_MINIMAL 37 #define CONFIG_SPL_FLUSH_IMAGE 38 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 39 #define CONFIG_FSL_LAW /* Use common FSL init code */ 40 #define CONFIG_SYS_TEXT_BASE 0x11001000 41 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 42 #define CONFIG_SPL_PAD_TO 0x20000 43 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 50 #define CONFIG_SPL_SPI_BOOT 51 #ifdef CONFIG_SPL_BUILD 52 #define CONFIG_SPL_COMMON_INIT_DDR 53 #endif 54 #endif 55 56 #define CONFIG_NAND_FSL_ELBC 57 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 58 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 59 60 #ifdef CONFIG_NAND 61 #ifdef CONFIG_TPL_BUILD 62 #define CONFIG_SPL_NAND_BOOT 63 #define CONFIG_SPL_FLUSH_IMAGE 64 #define CONFIG_SPL_NAND_INIT 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #define CONFIG_SPL_MAX_SIZE (128 << 10) 67 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 70 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 71 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 73 #elif defined(CONFIG_SPL_BUILD) 74 #define CONFIG_SPL_INIT_MINIMAL 75 #define CONFIG_SPL_FLUSH_IMAGE 76 #define CONFIG_SPL_TEXT_BASE 0xff800000 77 #define CONFIG_SPL_MAX_SIZE 4096 78 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 79 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 80 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 81 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 82 #endif 83 #define CONFIG_SPL_PAD_TO 0x20000 84 #define CONFIG_TPL_PAD_TO 0x20000 85 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 86 #define CONFIG_SYS_TEXT_BASE 0x11001000 87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 88 #endif 89 90 /* High Level Configuration Options */ 91 #define CONFIG_BOOKE /* BOOKE */ 92 #define CONFIG_E500 /* BOOKE e500 family */ 93 #define CONFIG_P1022 94 #define CONFIG_P1022DS 95 #define CONFIG_MP /* support multiple processors */ 96 97 #ifndef CONFIG_SYS_TEXT_BASE 98 #define CONFIG_SYS_TEXT_BASE 0xeff40000 99 #endif 100 101 #ifndef CONFIG_RESET_VECTOR_ADDRESS 102 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 103 #endif 104 105 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 106 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 107 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 108 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 109 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 110 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 111 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 112 113 #define CONFIG_ENABLE_36BIT_PHYS 114 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_ADDR_MAP 117 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 118 #endif 119 120 #define CONFIG_FSL_LAW /* Use common FSL init code */ 121 122 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 123 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 124 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 125 126 /* 127 * These can be toggled for performance analysis, otherwise use default. 128 */ 129 #define CONFIG_L2_CACHE 130 #define CONFIG_BTB 131 132 #define CONFIG_SYS_MEMTEST_START 0x00000000 133 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 134 135 #define CONFIG_SYS_CCSRBAR 0xffe00000 136 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 137 138 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 139 SPL code*/ 140 #ifdef CONFIG_SPL_BUILD 141 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 142 #endif 143 144 /* DDR Setup */ 145 #define CONFIG_DDR_SPD 146 #define CONFIG_VERY_BIG_RAM 147 #define CONFIG_SYS_FSL_DDR3 148 149 #ifdef CONFIG_DDR_ECC 150 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 151 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 152 #endif 153 154 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 155 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 156 157 #define CONFIG_NUM_DDR_CONTROLLERS 1 158 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 159 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 160 161 /* I2C addresses of SPD EEPROMs */ 162 #define CONFIG_SYS_SPD_BUS_NUM 1 163 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 164 165 /* These are used when DDR doesn't use SPD. */ 166 #define CONFIG_SYS_SDRAM_SIZE 2048 167 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 168 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 169 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 170 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 171 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 172 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 173 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 174 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 175 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 176 #define CONFIG_SYS_DDR_MODE_1 0x00441221 177 #define CONFIG_SYS_DDR_MODE_2 0x00000000 178 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 179 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 180 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 181 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 182 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 183 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 184 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 185 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 186 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 187 188 /* 189 * Memory map 190 * 191 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 192 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 193 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 194 * 195 * Localbus cacheable (TBD) 196 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 197 * 198 * Localbus non-cacheable 199 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 200 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 201 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 202 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 203 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 204 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 205 */ 206 207 /* 208 * Local Bus Definitions 209 */ 210 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 211 #ifdef CONFIG_PHYS_64BIT 212 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 213 #else 214 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 215 #endif 216 217 #define CONFIG_FLASH_BR_PRELIM \ 218 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 219 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 220 221 #ifdef CONFIG_NAND 222 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 223 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 224 #else 225 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 226 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 227 #endif 228 229 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 230 #define CONFIG_SYS_FLASH_QUIET_TEST 231 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 232 233 #define CONFIG_SYS_MAX_FLASH_BANKS 1 234 #define CONFIG_SYS_MAX_FLASH_SECT 1024 235 236 #ifndef CONFIG_SYS_MONITOR_BASE 237 #ifdef CONFIG_SPL_BUILD 238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 239 #else 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 241 #endif 242 #endif 243 244 #define CONFIG_FLASH_CFI_DRIVER 245 #define CONFIG_SYS_FLASH_CFI 246 #define CONFIG_SYS_FLASH_EMPTY_INFO 247 248 /* Nand Flash */ 249 #if defined(CONFIG_NAND_FSL_ELBC) 250 #define CONFIG_SYS_NAND_BASE 0xff800000 251 #ifdef CONFIG_PHYS_64BIT 252 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 253 #else 254 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 255 #endif 256 257 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 258 #define CONFIG_SYS_MAX_NAND_DEVICE 1 259 #define CONFIG_CMD_NAND 1 260 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 261 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 262 263 /* NAND flash config */ 264 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 265 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 266 | BR_PS_8 /* Port Size = 8 bit */ \ 267 | BR_MS_FCM /* MSEL = FCM */ \ 268 | BR_V) /* valid */ 269 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 270 | OR_FCM_PGS /* Large Page*/ \ 271 | OR_FCM_CSCT \ 272 | OR_FCM_CST \ 273 | OR_FCM_CHT \ 274 | OR_FCM_SCY_1 \ 275 | OR_FCM_TRLX \ 276 | OR_FCM_EHTR) 277 #ifdef CONFIG_NAND 278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 280 #else 281 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 282 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 283 #endif 284 285 #endif /* CONFIG_NAND_FSL_ELBC */ 286 287 #define CONFIG_BOARD_EARLY_INIT_F 288 #define CONFIG_BOARD_EARLY_INIT_R 289 #define CONFIG_MISC_INIT_R 290 #define CONFIG_HWCONFIG 291 292 #define CONFIG_FSL_NGPIXIS 293 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 294 #ifdef CONFIG_PHYS_64BIT 295 #define PIXIS_BASE_PHYS 0xfffdf0000ull 296 #else 297 #define PIXIS_BASE_PHYS PIXIS_BASE 298 #endif 299 300 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 301 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 302 303 #define PIXIS_LBMAP_SWITCH 7 304 #define PIXIS_LBMAP_MASK 0xF0 305 #define PIXIS_LBMAP_ALTBANK 0x20 306 #define PIXIS_SPD 0x07 307 #define PIXIS_SPD_SYSCLK_MASK 0x07 308 #define PIXIS_ELBC_SPI_MASK 0xc0 309 #define PIXIS_SPI 0x80 310 311 #define CONFIG_SYS_INIT_RAM_LOCK 312 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 313 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 314 315 #define CONFIG_SYS_GBL_DATA_OFFSET \ 316 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 317 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 318 319 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 320 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 321 322 /* 323 * Config the L2 Cache as L2 SRAM 324 */ 325 #if defined(CONFIG_SPL_BUILD) 326 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 327 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 328 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 329 #define CONFIG_SYS_L2_SIZE (256 << 10) 330 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 331 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 332 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 333 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 334 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 335 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 336 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 337 #elif defined(CONFIG_NAND) 338 #ifdef CONFIG_TPL_BUILD 339 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 340 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 341 #define CONFIG_SYS_L2_SIZE (256 << 10) 342 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 343 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 344 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 345 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 346 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 347 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 348 #else 349 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 350 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 351 #define CONFIG_SYS_L2_SIZE (256 << 10) 352 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 353 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 354 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 355 #endif 356 #endif 357 #endif 358 359 /* 360 * Serial Port 361 */ 362 #define CONFIG_CONS_INDEX 1 363 #define CONFIG_SYS_NS16550_SERIAL 364 #define CONFIG_SYS_NS16550_REG_SIZE 1 365 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 366 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 367 #define CONFIG_NS16550_MIN_FUNCTIONS 368 #endif 369 370 #define CONFIG_SYS_BAUDRATE_TABLE \ 371 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 372 373 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 374 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 375 376 /* Video */ 377 378 #ifdef CONFIG_FSL_DIU_FB 379 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 380 #define CONFIG_CMD_BMP 381 #define CONFIG_VIDEO_LOGO 382 #define CONFIG_VIDEO_BMP_LOGO 383 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 384 /* 385 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 386 * disable empty flash sector detection, which is I/O-intensive. 387 */ 388 #undef CONFIG_SYS_FLASH_EMPTY_INFO 389 #endif 390 391 #ifndef CONFIG_FSL_DIU_FB 392 #endif 393 394 #ifdef CONFIG_ATI 395 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 396 #define CONFIG_BIOSEMU 397 #define CONFIG_ATI_RADEON_FB 398 #define CONFIG_VIDEO_LOGO 399 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 400 #endif 401 402 /* I2C */ 403 #define CONFIG_SYS_I2C 404 #define CONFIG_SYS_I2C_FSL 405 #define CONFIG_SYS_FSL_I2C_SPEED 400000 406 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 407 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 408 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 409 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 410 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 411 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 412 413 /* 414 * I2C2 EEPROM 415 */ 416 #define CONFIG_ID_EEPROM 417 #define CONFIG_SYS_I2C_EEPROM_NXID 418 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 419 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 420 #define CONFIG_SYS_EEPROM_BUS_NUM 1 421 422 /* 423 * eSPI - Enhanced SPI 424 */ 425 426 #define CONFIG_HARD_SPI 427 428 #define CONFIG_SF_DEFAULT_SPEED 10000000 429 #define CONFIG_SF_DEFAULT_MODE 0 430 431 /* 432 * General PCI 433 * Memory space is mapped 1-1, but I/O space must start from 0. 434 */ 435 436 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 437 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 441 #else 442 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 443 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 444 #endif 445 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 446 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 447 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 450 #else 451 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 452 #endif 453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 454 455 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 456 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 457 #ifdef CONFIG_PHYS_64BIT 458 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 459 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 460 #else 461 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 462 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 463 #endif 464 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 465 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 466 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 469 #else 470 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 471 #endif 472 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 473 474 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 475 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 479 #else 480 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 481 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 482 #endif 483 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 484 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 485 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 486 #ifdef CONFIG_PHYS_64BIT 487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 488 #else 489 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 490 #endif 491 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 492 493 #ifdef CONFIG_PCI 494 #define CONFIG_PCI_INDIRECT_BRIDGE 495 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 496 #endif 497 498 /* SATA */ 499 #define CONFIG_LIBATA 500 #define CONFIG_FSL_SATA 501 #define CONFIG_FSL_SATA_V2 502 503 #define CONFIG_SYS_SATA_MAX_DEVICE 2 504 #define CONFIG_SATA1 505 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 506 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 507 #define CONFIG_SATA2 508 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 509 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 510 511 #ifdef CONFIG_FSL_SATA 512 #define CONFIG_LBA48 513 #define CONFIG_CMD_SATA 514 #define CONFIG_DOS_PARTITION 515 #endif 516 517 #define CONFIG_MMC 518 #ifdef CONFIG_MMC 519 #define CONFIG_FSL_ESDHC 520 #define CONFIG_GENERIC_MMC 521 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 522 #endif 523 524 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 525 #define CONFIG_DOS_PARTITION 526 #endif 527 528 #define CONFIG_TSEC_ENET 529 #ifdef CONFIG_TSEC_ENET 530 531 #define CONFIG_TSECV2 532 533 #define CONFIG_MII /* MII PHY management */ 534 #define CONFIG_TSEC1 1 535 #define CONFIG_TSEC1_NAME "eTSEC1" 536 #define CONFIG_TSEC2 1 537 #define CONFIG_TSEC2_NAME "eTSEC2" 538 539 #define TSEC1_PHY_ADDR 1 540 #define TSEC2_PHY_ADDR 2 541 542 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 543 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 544 545 #define TSEC1_PHYIDX 0 546 #define TSEC2_PHYIDX 0 547 548 #define CONFIG_ETHPRIME "eTSEC1" 549 550 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 551 #endif 552 553 /* 554 * Dynamic MTD Partition support with mtdparts 555 */ 556 #define CONFIG_MTD_DEVICE 557 #define CONFIG_MTD_PARTITIONS 558 #define CONFIG_CMD_MTDPARTS 559 #define CONFIG_FLASH_CFI_MTD 560 #ifdef CONFIG_PHYS_64BIT 561 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 562 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 563 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 564 "512k(dtb),768k(u-boot)" 565 #else 566 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 567 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 568 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 569 "512k(dtb),768k(u-boot)" 570 #endif 571 572 /* 573 * Environment 574 */ 575 #ifdef CONFIG_SPIFLASH 576 #define CONFIG_ENV_IS_IN_SPI_FLASH 577 #define CONFIG_ENV_SPI_BUS 0 578 #define CONFIG_ENV_SPI_CS 0 579 #define CONFIG_ENV_SPI_MAX_HZ 10000000 580 #define CONFIG_ENV_SPI_MODE 0 581 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 582 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 583 #define CONFIG_ENV_SECT_SIZE 0x10000 584 #elif defined(CONFIG_SDCARD) 585 #define CONFIG_ENV_IS_IN_MMC 586 #define CONFIG_FSL_FIXED_MMC_LOCATION 587 #define CONFIG_ENV_SIZE 0x2000 588 #define CONFIG_SYS_MMC_ENV_DEV 0 589 #elif defined(CONFIG_NAND) 590 #ifdef CONFIG_TPL_BUILD 591 #define CONFIG_ENV_SIZE 0x2000 592 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 593 #else 594 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 595 #endif 596 #define CONFIG_ENV_IS_IN_NAND 597 #define CONFIG_ENV_OFFSET (1024 * 1024) 598 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 599 #elif defined(CONFIG_SYS_RAMBOOT) 600 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 601 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 602 #define CONFIG_ENV_SIZE 0x2000 603 #else 604 #define CONFIG_ENV_IS_IN_FLASH 605 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 606 #define CONFIG_ENV_SIZE 0x2000 607 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 608 #endif 609 610 #define CONFIG_LOADS_ECHO 611 #define CONFIG_SYS_LOADS_BAUD_CHANGE 612 613 /* 614 * Command line configuration. 615 */ 616 #define CONFIG_CMD_ERRATA 617 #define CONFIG_CMD_IRQ 618 #define CONFIG_CMD_REGINFO 619 620 #ifdef CONFIG_PCI 621 #define CONFIG_CMD_PCI 622 #endif 623 624 /* 625 * USB 626 */ 627 #define CONFIG_HAS_FSL_DR_USB 628 #ifdef CONFIG_HAS_FSL_DR_USB 629 #define CONFIG_USB_EHCI 630 631 #ifdef CONFIG_USB_EHCI 632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 633 #define CONFIG_USB_EHCI_FSL 634 #endif 635 #endif 636 637 /* 638 * Miscellaneous configurable options 639 */ 640 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 641 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 642 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 643 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 644 #ifdef CONFIG_CMD_KGDB 645 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 646 #else 647 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 648 #endif 649 /* Print Buffer Size */ 650 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 651 #define CONFIG_SYS_MAXARGS 16 652 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 653 654 /* 655 * For booting Linux, the board info and command line data 656 * have to be in the first 64 MB of memory, since this is 657 * the maximum mapped by the Linux kernel during initialization. 658 */ 659 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 660 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 661 662 #ifdef CONFIG_CMD_KGDB 663 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 664 #endif 665 666 /* 667 * Environment Configuration 668 */ 669 670 #define CONFIG_HOSTNAME p1022ds 671 #define CONFIG_ROOTPATH "/opt/nfsroot" 672 #define CONFIG_BOOTFILE "uImage" 673 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 674 675 #define CONFIG_LOADADDR 1000000 676 677 678 #define CONFIG_BAUDRATE 115200 679 680 #define CONFIG_EXTRA_ENV_SETTINGS \ 681 "netdev=eth0\0" \ 682 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 683 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 684 "tftpflash=tftpboot $loadaddr $uboot && " \ 685 "protect off $ubootaddr +$filesize && " \ 686 "erase $ubootaddr +$filesize && " \ 687 "cp.b $loadaddr $ubootaddr $filesize && " \ 688 "protect on $ubootaddr +$filesize && " \ 689 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 690 "consoledev=ttyS0\0" \ 691 "ramdiskaddr=2000000\0" \ 692 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 693 "fdtaddr=1e00000\0" \ 694 "fdtfile=p1022ds.dtb\0" \ 695 "bdev=sda3\0" \ 696 "hwconfig=esdhc;audclk:12\0" 697 698 #define CONFIG_HDBOOT \ 699 "setenv bootargs root=/dev/$bdev rw " \ 700 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 701 "tftp $loadaddr $bootfile;" \ 702 "tftp $fdtaddr $fdtfile;" \ 703 "bootm $loadaddr - $fdtaddr" 704 705 #define CONFIG_NFSBOOTCOMMAND \ 706 "setenv bootargs root=/dev/nfs rw " \ 707 "nfsroot=$serverip:$rootpath " \ 708 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 709 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 710 "tftp $loadaddr $bootfile;" \ 711 "tftp $fdtaddr $fdtfile;" \ 712 "bootm $loadaddr - $fdtaddr" 713 714 #define CONFIG_RAMBOOTCOMMAND \ 715 "setenv bootargs root=/dev/ram rw " \ 716 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 717 "tftp $ramdiskaddr $ramdiskfile;" \ 718 "tftp $loadaddr $bootfile;" \ 719 "tftp $fdtaddr $fdtfile;" \ 720 "bootm $loadaddr $ramdiskaddr $fdtaddr" 721 722 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 723 724 #endif 725