1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #ifdef CONFIG_SDCARD 19 #define CONFIG_SPL 20 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 21 #define CONFIG_SPL_ENV_SUPPORT 22 #define CONFIG_SPL_SERIAL_SUPPORT 23 #define CONFIG_SPL_MMC_SUPPORT 24 #define CONFIG_SPL_MMC_MINIMAL 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 27 #define CONFIG_SPL_LIBGENERIC_SUPPORT 28 #define CONFIG_SPL_LIBCOMMON_SUPPORT 29 #define CONFIG_SPL_I2C_SUPPORT 30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 31 #define CONFIG_SYS_TEXT_BASE 0x11001000 32 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 33 #define CONFIG_SPL_PAD_TO 0x20000 34 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 35 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 36 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 37 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 38 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 41 #define CONFIG_SPL_MMC_BOOT 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #endif 45 #endif 46 47 #ifdef CONFIG_SPIFLASH 48 #define CONFIG_SPL 49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 50 #define CONFIG_SPL_ENV_SUPPORT 51 #define CONFIG_SPL_SERIAL_SUPPORT 52 #define CONFIG_SPL_SPI_SUPPORT 53 #define CONFIG_SPL_SPI_FLASH_SUPPORT 54 #define CONFIG_SPL_SPI_FLASH_MINIMAL 55 #define CONFIG_SPL_FLUSH_IMAGE 56 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 57 #define CONFIG_SPL_LIBGENERIC_SUPPORT 58 #define CONFIG_SPL_LIBCOMMON_SUPPORT 59 #define CONFIG_SPL_I2C_SUPPORT 60 #define CONFIG_FSL_LAW /* Use common FSL init code */ 61 #define CONFIG_SYS_TEXT_BASE 0x11001000 62 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 63 #define CONFIG_SPL_PAD_TO 0x20000 64 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 71 #define CONFIG_SPL_SPI_BOOT 72 #ifdef CONFIG_SPL_BUILD 73 #define CONFIG_SPL_COMMON_INIT_DDR 74 #endif 75 #endif 76 77 #define CONFIG_NAND_FSL_ELBC 78 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 79 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 80 81 #ifdef CONFIG_NAND 82 #define CONFIG_SPL 83 #define CONFIG_TPL 84 #ifdef CONFIG_TPL_BUILD 85 #define CONFIG_SPL_NAND_BOOT 86 #define CONFIG_SPL_FLUSH_IMAGE 87 #define CONFIG_SPL_ENV_SUPPORT 88 #define CONFIG_SPL_NAND_INIT 89 #define CONFIG_SPL_SERIAL_SUPPORT 90 #define CONFIG_SPL_LIBGENERIC_SUPPORT 91 #define CONFIG_SPL_LIBCOMMON_SUPPORT 92 #define CONFIG_SPL_I2C_SUPPORT 93 #define CONFIG_SPL_NAND_SUPPORT 94 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 95 #define CONFIG_SPL_COMMON_INIT_DDR 96 #define CONFIG_SPL_MAX_SIZE (128 << 10) 97 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 99 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 100 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 101 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 103 #elif defined(CONFIG_SPL_BUILD) 104 #define CONFIG_SPL_INIT_MINIMAL 105 #define CONFIG_SPL_SERIAL_SUPPORT 106 #define CONFIG_SPL_NAND_SUPPORT 107 #define CONFIG_SPL_FLUSH_IMAGE 108 #define CONFIG_SPL_TEXT_BASE 0xff800000 109 #define CONFIG_SPL_MAX_SIZE 4096 110 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 111 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 112 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 113 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 114 #endif 115 #define CONFIG_SPL_PAD_TO 0x20000 116 #define CONFIG_TPL_PAD_TO 0x20000 117 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 118 #define CONFIG_SYS_TEXT_BASE 0x11001000 119 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 120 #endif 121 122 /* High Level Configuration Options */ 123 #define CONFIG_BOOKE /* BOOKE */ 124 #define CONFIG_E500 /* BOOKE e500 family */ 125 #define CONFIG_P1022 126 #define CONFIG_P1022DS 127 #define CONFIG_MP /* support multiple processors */ 128 129 #ifndef CONFIG_SYS_TEXT_BASE 130 #define CONFIG_SYS_TEXT_BASE 0xeff40000 131 #endif 132 133 #ifndef CONFIG_RESET_VECTOR_ADDRESS 134 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 135 #endif 136 137 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 138 #define CONFIG_PCI /* Enable PCI/PCIE */ 139 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 140 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 141 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 142 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 143 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 144 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 145 146 #define CONFIG_ENABLE_36BIT_PHYS 147 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_ADDR_MAP 150 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 151 #endif 152 153 #define CONFIG_FSL_LAW /* Use common FSL init code */ 154 155 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 156 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 157 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 158 159 /* 160 * These can be toggled for performance analysis, otherwise use default. 161 */ 162 #define CONFIG_L2_CACHE 163 #define CONFIG_BTB 164 165 #define CONFIG_SYS_MEMTEST_START 0x00000000 166 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 167 168 #define CONFIG_SYS_CCSRBAR 0xffe00000 169 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 170 171 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 172 SPL code*/ 173 #ifdef CONFIG_SPL_BUILD 174 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 175 #endif 176 177 178 /* DDR Setup */ 179 #define CONFIG_DDR_SPD 180 #define CONFIG_VERY_BIG_RAM 181 #define CONFIG_SYS_FSL_DDR3 182 183 #ifdef CONFIG_DDR_ECC 184 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 185 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 186 #endif 187 188 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 189 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 190 191 #define CONFIG_NUM_DDR_CONTROLLERS 1 192 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 193 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 194 195 /* I2C addresses of SPD EEPROMs */ 196 #define CONFIG_SYS_SPD_BUS_NUM 1 197 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 198 199 /* These are used when DDR doesn't use SPD. */ 200 #define CONFIG_SYS_SDRAM_SIZE 2048 201 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 202 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 203 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 204 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 205 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 206 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 207 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 208 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 209 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 210 #define CONFIG_SYS_DDR_MODE_1 0x00441221 211 #define CONFIG_SYS_DDR_MODE_2 0x00000000 212 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 213 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 214 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 215 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 216 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 217 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 218 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 219 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 220 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 221 222 223 /* 224 * Memory map 225 * 226 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 227 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 228 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 229 * 230 * Localbus cacheable (TBD) 231 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 232 * 233 * Localbus non-cacheable 234 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 235 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 236 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 237 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 238 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 239 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 240 */ 241 242 /* 243 * Local Bus Definitions 244 */ 245 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 246 #ifdef CONFIG_PHYS_64BIT 247 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 248 #else 249 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 250 #endif 251 252 #define CONFIG_FLASH_BR_PRELIM \ 253 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 254 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 255 256 #ifdef CONFIG_NAND 257 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 258 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 259 #else 260 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 261 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 262 #endif 263 264 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 265 #define CONFIG_SYS_FLASH_QUIET_TEST 266 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 267 268 #define CONFIG_SYS_MAX_FLASH_BANKS 1 269 #define CONFIG_SYS_MAX_FLASH_SECT 1024 270 271 #ifndef CONFIG_SYS_MONITOR_BASE 272 #ifdef CONFIG_SPL_BUILD 273 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 274 #else 275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 276 #endif 277 #endif 278 279 #define CONFIG_FLASH_CFI_DRIVER 280 #define CONFIG_SYS_FLASH_CFI 281 #define CONFIG_SYS_FLASH_EMPTY_INFO 282 283 /* Nand Flash */ 284 #if defined(CONFIG_NAND_FSL_ELBC) 285 #define CONFIG_SYS_NAND_BASE 0xff800000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 288 #else 289 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 290 #endif 291 292 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 293 #define CONFIG_SYS_MAX_NAND_DEVICE 1 294 #define CONFIG_MTD_NAND_VERIFY_WRITE 295 #define CONFIG_CMD_NAND 1 296 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 297 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 298 299 /* NAND flash config */ 300 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 301 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 302 | BR_PS_8 /* Port Size = 8 bit */ \ 303 | BR_MS_FCM /* MSEL = FCM */ \ 304 | BR_V) /* valid */ 305 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 306 | OR_FCM_PGS /* Large Page*/ \ 307 | OR_FCM_CSCT \ 308 | OR_FCM_CST \ 309 | OR_FCM_CHT \ 310 | OR_FCM_SCY_1 \ 311 | OR_FCM_TRLX \ 312 | OR_FCM_EHTR) 313 #ifdef CONFIG_NAND 314 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 315 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 316 #else 317 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 318 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 319 #endif 320 321 #endif /* CONFIG_NAND_FSL_ELBC */ 322 323 #define CONFIG_BOARD_EARLY_INIT_F 324 #define CONFIG_BOARD_EARLY_INIT_R 325 #define CONFIG_MISC_INIT_R 326 #define CONFIG_HWCONFIG 327 328 #define CONFIG_FSL_NGPIXIS 329 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 330 #ifdef CONFIG_PHYS_64BIT 331 #define PIXIS_BASE_PHYS 0xfffdf0000ull 332 #else 333 #define PIXIS_BASE_PHYS PIXIS_BASE 334 #endif 335 336 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 337 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 338 339 #define PIXIS_LBMAP_SWITCH 7 340 #define PIXIS_LBMAP_MASK 0xF0 341 #define PIXIS_LBMAP_ALTBANK 0x20 342 #define PIXIS_SPD 0x07 343 #define PIXIS_SPD_SYSCLK_MASK 0x07 344 #define PIXIS_ELBC_SPI_MASK 0xc0 345 #define PIXIS_SPI 0x80 346 347 #define CONFIG_SYS_INIT_RAM_LOCK 348 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 349 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 350 351 #define CONFIG_SYS_GBL_DATA_OFFSET \ 352 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 353 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 354 355 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 356 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 357 358 /* 359 * Config the L2 Cache as L2 SRAM 360 */ 361 #if defined(CONFIG_SPL_BUILD) 362 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 363 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 364 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 365 #define CONFIG_SYS_L2_SIZE (256 << 10) 366 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 367 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 368 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 369 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 370 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 371 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 372 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 373 #elif defined(CONFIG_NAND) 374 #ifdef CONFIG_TPL_BUILD 375 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 376 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 377 #define CONFIG_SYS_L2_SIZE (256 << 10) 378 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 379 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 380 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 381 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 382 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 383 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 384 #else 385 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 386 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 387 #define CONFIG_SYS_L2_SIZE (256 << 10) 388 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 389 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 390 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 391 #endif 392 #endif 393 #endif 394 395 /* 396 * Serial Port 397 */ 398 #define CONFIG_CONS_INDEX 1 399 #define CONFIG_SYS_NS16550 400 #define CONFIG_SYS_NS16550_SERIAL 401 #define CONFIG_SYS_NS16550_REG_SIZE 1 402 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 403 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 404 #define CONFIG_NS16550_MIN_FUNCTIONS 405 #endif 406 407 #define CONFIG_SYS_BAUDRATE_TABLE \ 408 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 409 410 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 411 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 412 413 /* Use the HUSH parser */ 414 #define CONFIG_SYS_HUSH_PARSER 415 416 /* Video */ 417 418 #ifdef CONFIG_FSL_DIU_FB 419 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 420 #define CONFIG_VIDEO 421 #define CONFIG_CMD_BMP 422 #define CONFIG_CFB_CONSOLE 423 #define CONFIG_VIDEO_SW_CURSOR 424 #define CONFIG_VGA_AS_SINGLE_DEVICE 425 #define CONFIG_VIDEO_LOGO 426 #define CONFIG_VIDEO_BMP_LOGO 427 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 428 /* 429 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 430 * disable empty flash sector detection, which is I/O-intensive. 431 */ 432 #undef CONFIG_SYS_FLASH_EMPTY_INFO 433 #endif 434 435 #ifndef CONFIG_FSL_DIU_FB 436 #endif 437 438 #ifdef CONFIG_ATI 439 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 440 #define CONFIG_VIDEO 441 #define CONFIG_BIOSEMU 442 #define CONFIG_VIDEO_SW_CURSOR 443 #define CONFIG_ATI_RADEON_FB 444 #define CONFIG_VIDEO_LOGO 445 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 446 #define CONFIG_CFB_CONSOLE 447 #define CONFIG_VGA_AS_SINGLE_DEVICE 448 #endif 449 450 /* 451 * Pass open firmware flat tree 452 */ 453 #define CONFIG_OF_LIBFDT 454 #define CONFIG_OF_BOARD_SETUP 455 #define CONFIG_OF_STDOUT_VIA_ALIAS 456 457 /* new uImage format support */ 458 #define CONFIG_FIT 459 #define CONFIG_FIT_VERBOSE 460 461 /* I2C */ 462 #define CONFIG_SYS_I2C 463 #define CONFIG_SYS_I2C_FSL 464 #define CONFIG_SYS_FSL_I2C_SPEED 400000 465 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 466 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 467 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 468 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 469 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 470 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 471 472 /* 473 * I2C2 EEPROM 474 */ 475 #define CONFIG_ID_EEPROM 476 #define CONFIG_SYS_I2C_EEPROM_NXID 477 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 478 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 479 #define CONFIG_SYS_EEPROM_BUS_NUM 1 480 481 /* 482 * eSPI - Enhanced SPI 483 */ 484 #define CONFIG_SPI_FLASH 485 #define CONFIG_SPI_FLASH_SPANSION 486 487 #define CONFIG_HARD_SPI 488 #define CONFIG_FSL_ESPI 489 490 #define CONFIG_CMD_SF 491 #define CONFIG_SF_DEFAULT_SPEED 10000000 492 #define CONFIG_SF_DEFAULT_MODE 0 493 494 /* 495 * General PCI 496 * Memory space is mapped 1-1, but I/O space must start from 0. 497 */ 498 499 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 500 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 501 #ifdef CONFIG_PHYS_64BIT 502 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 503 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 504 #else 505 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 506 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 507 #endif 508 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 509 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 510 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 511 #ifdef CONFIG_PHYS_64BIT 512 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 513 #else 514 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 515 #endif 516 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 517 518 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 519 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 522 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 523 #else 524 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 525 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 526 #endif 527 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 528 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 529 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 530 #ifdef CONFIG_PHYS_64BIT 531 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 532 #else 533 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 534 #endif 535 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 536 537 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 538 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 539 #ifdef CONFIG_PHYS_64BIT 540 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 541 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 542 #else 543 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 544 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 545 #endif 546 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 547 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 548 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 549 #ifdef CONFIG_PHYS_64BIT 550 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 551 #else 552 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 553 #endif 554 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 555 556 #ifdef CONFIG_PCI 557 #define CONFIG_PCI_INDIRECT_BRIDGE 558 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 559 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 560 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 561 #endif 562 563 /* SATA */ 564 #define CONFIG_LIBATA 565 #define CONFIG_FSL_SATA 566 #define CONFIG_FSL_SATA_V2 567 568 #define CONFIG_SYS_SATA_MAX_DEVICE 2 569 #define CONFIG_SATA1 570 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 571 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 572 #define CONFIG_SATA2 573 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 574 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 575 576 #ifdef CONFIG_FSL_SATA 577 #define CONFIG_LBA48 578 #define CONFIG_CMD_SATA 579 #define CONFIG_DOS_PARTITION 580 #define CONFIG_CMD_EXT2 581 #endif 582 583 #define CONFIG_MMC 584 #ifdef CONFIG_MMC 585 #define CONFIG_CMD_MMC 586 #define CONFIG_FSL_ESDHC 587 #define CONFIG_GENERIC_MMC 588 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 589 #endif 590 591 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 592 #define CONFIG_CMD_EXT2 593 #define CONFIG_CMD_FAT 594 #define CONFIG_DOS_PARTITION 595 #endif 596 597 #define CONFIG_TSEC_ENET 598 #ifdef CONFIG_TSEC_ENET 599 600 #define CONFIG_TSECV2 601 602 #define CONFIG_MII /* MII PHY management */ 603 #define CONFIG_TSEC1 1 604 #define CONFIG_TSEC1_NAME "eTSEC1" 605 #define CONFIG_TSEC2 1 606 #define CONFIG_TSEC2_NAME "eTSEC2" 607 608 #define TSEC1_PHY_ADDR 1 609 #define TSEC2_PHY_ADDR 2 610 611 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 612 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 613 614 #define TSEC1_PHYIDX 0 615 #define TSEC2_PHYIDX 0 616 617 #define CONFIG_ETHPRIME "eTSEC1" 618 619 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 620 #endif 621 622 /* 623 * Environment 624 */ 625 #ifdef CONFIG_SPIFLASH 626 #define CONFIG_ENV_IS_IN_SPI_FLASH 627 #define CONFIG_ENV_SPI_BUS 0 628 #define CONFIG_ENV_SPI_CS 0 629 #define CONFIG_ENV_SPI_MAX_HZ 10000000 630 #define CONFIG_ENV_SPI_MODE 0 631 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 632 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 633 #define CONFIG_ENV_SECT_SIZE 0x10000 634 #elif defined(CONFIG_SDCARD) 635 #define CONFIG_ENV_IS_IN_MMC 636 #define CONFIG_FSL_FIXED_MMC_LOCATION 637 #define CONFIG_ENV_SIZE 0x2000 638 #define CONFIG_SYS_MMC_ENV_DEV 0 639 #elif defined(CONFIG_NAND) 640 #ifdef CONFIG_TPL_BUILD 641 #define CONFIG_ENV_SIZE 0x2000 642 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 643 #else 644 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 645 #endif 646 #define CONFIG_ENV_IS_IN_NAND 647 #define CONFIG_ENV_OFFSET (1024 * 1024) 648 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 649 #elif defined(CONFIG_SYS_RAMBOOT) 650 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 651 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 652 #define CONFIG_ENV_SIZE 0x2000 653 #else 654 #define CONFIG_ENV_IS_IN_FLASH 655 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 656 #define CONFIG_ENV_SIZE 0x2000 657 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 658 #endif 659 660 #define CONFIG_LOADS_ECHO 661 #define CONFIG_SYS_LOADS_BAUD_CHANGE 662 663 /* 664 * Command line configuration. 665 */ 666 #include <config_cmd_default.h> 667 668 #define CONFIG_CMD_ELF 669 #define CONFIG_CMD_ERRATA 670 #define CONFIG_CMD_IRQ 671 #define CONFIG_CMD_I2C 672 #define CONFIG_CMD_MII 673 #define CONFIG_CMD_PING 674 #define CONFIG_CMD_SETEXPR 675 #define CONFIG_CMD_REGINFO 676 677 #ifdef CONFIG_PCI 678 #define CONFIG_CMD_PCI 679 #define CONFIG_CMD_NET 680 #endif 681 682 /* 683 * USB 684 */ 685 #define CONFIG_HAS_FSL_DR_USB 686 #ifdef CONFIG_HAS_FSL_DR_USB 687 #define CONFIG_USB_EHCI 688 689 #ifdef CONFIG_USB_EHCI 690 #define CONFIG_CMD_USB 691 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 692 #define CONFIG_USB_EHCI_FSL 693 #define CONFIG_USB_STORAGE 694 #define CONFIG_CMD_FAT 695 #endif 696 #endif 697 698 /* 699 * Miscellaneous configurable options 700 */ 701 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 702 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 703 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 704 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 705 #ifdef CONFIG_CMD_KGDB 706 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 707 #else 708 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 709 #endif 710 /* Print Buffer Size */ 711 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 712 #define CONFIG_SYS_MAXARGS 16 713 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 714 715 /* 716 * For booting Linux, the board info and command line data 717 * have to be in the first 64 MB of memory, since this is 718 * the maximum mapped by the Linux kernel during initialization. 719 */ 720 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 721 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 722 723 #ifdef CONFIG_CMD_KGDB 724 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 725 #endif 726 727 /* 728 * Environment Configuration 729 */ 730 731 #define CONFIG_HOSTNAME p1022ds 732 #define CONFIG_ROOTPATH "/opt/nfsroot" 733 #define CONFIG_BOOTFILE "uImage" 734 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 735 736 #define CONFIG_LOADADDR 1000000 737 738 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 739 740 #define CONFIG_BAUDRATE 115200 741 742 #define CONFIG_EXTRA_ENV_SETTINGS \ 743 "netdev=eth0\0" \ 744 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 745 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 746 "tftpflash=tftpboot $loadaddr $uboot && " \ 747 "protect off $ubootaddr +$filesize && " \ 748 "erase $ubootaddr +$filesize && " \ 749 "cp.b $loadaddr $ubootaddr $filesize && " \ 750 "protect on $ubootaddr +$filesize && " \ 751 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 752 "consoledev=ttyS0\0" \ 753 "ramdiskaddr=2000000\0" \ 754 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 755 "fdtaddr=c00000\0" \ 756 "fdtfile=p1022ds.dtb\0" \ 757 "bdev=sda3\0" \ 758 "hwconfig=esdhc;audclk:12\0" 759 760 #define CONFIG_HDBOOT \ 761 "setenv bootargs root=/dev/$bdev rw " \ 762 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 763 "tftp $loadaddr $bootfile;" \ 764 "tftp $fdtaddr $fdtfile;" \ 765 "bootm $loadaddr - $fdtaddr" 766 767 #define CONFIG_NFSBOOTCOMMAND \ 768 "setenv bootargs root=/dev/nfs rw " \ 769 "nfsroot=$serverip:$rootpath " \ 770 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 771 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 772 "tftp $loadaddr $bootfile;" \ 773 "tftp $fdtaddr $fdtfile;" \ 774 "bootm $loadaddr - $fdtaddr" 775 776 #define CONFIG_RAMBOOTCOMMAND \ 777 "setenv bootargs root=/dev/ram rw " \ 778 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 779 "tftp $ramdiskaddr $ramdiskfile;" \ 780 "tftp $loadaddr $bootfile;" \ 781 "tftp $fdtaddr $fdtfile;" \ 782 "bootm $loadaddr $ramdiskaddr $fdtaddr" 783 784 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 785 786 #endif 787