1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_SDCARD 15 #define CONFIG_SPL_MMC_MINIMAL 16 #define CONFIG_SPL_FLUSH_IMAGE 17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 18 #define CONFIG_SYS_TEXT_BASE 0x11001000 19 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 20 #define CONFIG_SPL_PAD_TO 0x20000 21 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 28 #define CONFIG_SPL_MMC_BOOT 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #endif 32 #endif 33 34 #ifdef CONFIG_SPIFLASH 35 #define CONFIG_SPL_SPI_FLASH_MINIMAL 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x11001000 39 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 40 #define CONFIG_SPL_PAD_TO 0x20000 41 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 48 #define CONFIG_SPL_SPI_BOOT 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #endif 52 #endif 53 54 #define CONFIG_NAND_FSL_ELBC 55 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 56 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 57 58 #ifdef CONFIG_NAND 59 #ifdef CONFIG_TPL_BUILD 60 #define CONFIG_SPL_NAND_BOOT 61 #define CONFIG_SPL_FLUSH_IMAGE 62 #define CONFIG_SPL_NAND_INIT 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SPL_MAX_SIZE (128 << 10) 65 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 67 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 68 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 69 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 70 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 71 #elif defined(CONFIG_SPL_BUILD) 72 #define CONFIG_SPL_INIT_MINIMAL 73 #define CONFIG_SPL_FLUSH_IMAGE 74 #define CONFIG_SPL_TEXT_BASE 0xff800000 75 #define CONFIG_SPL_MAX_SIZE 4096 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 77 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 78 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 80 #endif 81 #define CONFIG_SPL_PAD_TO 0x20000 82 #define CONFIG_TPL_PAD_TO 0x20000 83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 84 #define CONFIG_SYS_TEXT_BASE 0x11001000 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 86 #endif 87 88 /* High Level Configuration Options */ 89 #define CONFIG_MP /* support multiple processors */ 90 91 #ifndef CONFIG_SYS_TEXT_BASE 92 #define CONFIG_SYS_TEXT_BASE 0xeff40000 93 #endif 94 95 #ifndef CONFIG_RESET_VECTOR_ADDRESS 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 97 #endif 98 99 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 100 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 101 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 102 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 103 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 104 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 105 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 106 107 #define CONFIG_ENABLE_36BIT_PHYS 108 109 #ifdef CONFIG_PHYS_64BIT 110 #define CONFIG_ADDR_MAP 111 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 112 #endif 113 114 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 115 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 116 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 117 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_L2_CACHE 122 #define CONFIG_BTB 123 124 #define CONFIG_SYS_MEMTEST_START 0x00000000 125 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 126 127 #define CONFIG_SYS_CCSRBAR 0xffe00000 128 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 129 130 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 131 SPL code*/ 132 #ifdef CONFIG_SPL_BUILD 133 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 134 #endif 135 136 /* DDR Setup */ 137 #define CONFIG_DDR_SPD 138 #define CONFIG_VERY_BIG_RAM 139 140 #ifdef CONFIG_DDR_ECC 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 142 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 143 #endif 144 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 150 151 /* I2C addresses of SPD EEPROMs */ 152 #define CONFIG_SYS_SPD_BUS_NUM 1 153 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 154 155 /* These are used when DDR doesn't use SPD. */ 156 #define CONFIG_SYS_SDRAM_SIZE 2048 157 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 158 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 159 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 160 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 161 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 162 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 163 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 164 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 165 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 166 #define CONFIG_SYS_DDR_MODE_1 0x00441221 167 #define CONFIG_SYS_DDR_MODE_2 0x00000000 168 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 169 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 170 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 171 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 172 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 173 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 174 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 175 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 176 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 177 178 /* 179 * Memory map 180 * 181 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 182 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 183 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 184 * 185 * Localbus cacheable (TBD) 186 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 187 * 188 * Localbus non-cacheable 189 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 190 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 191 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 192 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 193 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 194 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 195 */ 196 197 /* 198 * Local Bus Definitions 199 */ 200 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 201 #ifdef CONFIG_PHYS_64BIT 202 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 203 #else 204 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 205 #endif 206 207 #define CONFIG_FLASH_BR_PRELIM \ 208 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 209 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 210 211 #ifdef CONFIG_NAND 212 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 213 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 214 #else 215 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 216 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 217 #endif 218 219 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 220 #define CONFIG_SYS_FLASH_QUIET_TEST 221 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 222 223 #define CONFIG_SYS_MAX_FLASH_BANKS 1 224 #define CONFIG_SYS_MAX_FLASH_SECT 1024 225 226 #ifndef CONFIG_SYS_MONITOR_BASE 227 #ifdef CONFIG_SPL_BUILD 228 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 229 #else 230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 231 #endif 232 #endif 233 234 #define CONFIG_FLASH_CFI_DRIVER 235 #define CONFIG_SYS_FLASH_CFI 236 #define CONFIG_SYS_FLASH_EMPTY_INFO 237 238 /* Nand Flash */ 239 #if defined(CONFIG_NAND_FSL_ELBC) 240 #define CONFIG_SYS_NAND_BASE 0xff800000 241 #ifdef CONFIG_PHYS_64BIT 242 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 243 #else 244 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 245 #endif 246 247 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 249 #define CONFIG_CMD_NAND 1 250 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 251 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 252 253 /* NAND flash config */ 254 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 255 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 256 | BR_PS_8 /* Port Size = 8 bit */ \ 257 | BR_MS_FCM /* MSEL = FCM */ \ 258 | BR_V) /* valid */ 259 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 260 | OR_FCM_PGS /* Large Page*/ \ 261 | OR_FCM_CSCT \ 262 | OR_FCM_CST \ 263 | OR_FCM_CHT \ 264 | OR_FCM_SCY_1 \ 265 | OR_FCM_TRLX \ 266 | OR_FCM_EHTR) 267 #ifdef CONFIG_NAND 268 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 269 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 270 #else 271 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 272 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 273 #endif 274 275 #endif /* CONFIG_NAND_FSL_ELBC */ 276 277 #define CONFIG_BOARD_EARLY_INIT_F 278 #define CONFIG_BOARD_EARLY_INIT_R 279 #define CONFIG_MISC_INIT_R 280 #define CONFIG_HWCONFIG 281 282 #define CONFIG_FSL_NGPIXIS 283 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 284 #ifdef CONFIG_PHYS_64BIT 285 #define PIXIS_BASE_PHYS 0xfffdf0000ull 286 #else 287 #define PIXIS_BASE_PHYS PIXIS_BASE 288 #endif 289 290 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 291 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 292 293 #define PIXIS_LBMAP_SWITCH 7 294 #define PIXIS_LBMAP_MASK 0xF0 295 #define PIXIS_LBMAP_ALTBANK 0x20 296 #define PIXIS_SPD 0x07 297 #define PIXIS_SPD_SYSCLK_MASK 0x07 298 #define PIXIS_ELBC_SPI_MASK 0xc0 299 #define PIXIS_SPI 0x80 300 301 #define CONFIG_SYS_INIT_RAM_LOCK 302 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 303 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 304 305 #define CONFIG_SYS_GBL_DATA_OFFSET \ 306 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 307 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 308 309 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 310 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 311 312 /* 313 * Config the L2 Cache as L2 SRAM 314 */ 315 #if defined(CONFIG_SPL_BUILD) 316 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 317 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 318 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 319 #define CONFIG_SYS_L2_SIZE (256 << 10) 320 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 321 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 322 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 323 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 324 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 325 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 326 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 327 #elif defined(CONFIG_NAND) 328 #ifdef CONFIG_TPL_BUILD 329 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 330 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 331 #define CONFIG_SYS_L2_SIZE (256 << 10) 332 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 333 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 334 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 335 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 336 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 337 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 338 #else 339 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 340 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 341 #define CONFIG_SYS_L2_SIZE (256 << 10) 342 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 343 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 344 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 345 #endif 346 #endif 347 #endif 348 349 /* 350 * Serial Port 351 */ 352 #define CONFIG_CONS_INDEX 1 353 #define CONFIG_SYS_NS16550_SERIAL 354 #define CONFIG_SYS_NS16550_REG_SIZE 1 355 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 356 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 357 #define CONFIG_NS16550_MIN_FUNCTIONS 358 #endif 359 360 #define CONFIG_SYS_BAUDRATE_TABLE \ 361 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 362 363 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 364 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 365 366 /* Video */ 367 368 #ifdef CONFIG_FSL_DIU_FB 369 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 370 #define CONFIG_CMD_BMP 371 #define CONFIG_VIDEO_LOGO 372 #define CONFIG_VIDEO_BMP_LOGO 373 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 374 /* 375 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 376 * disable empty flash sector detection, which is I/O-intensive. 377 */ 378 #undef CONFIG_SYS_FLASH_EMPTY_INFO 379 #endif 380 381 #ifndef CONFIG_FSL_DIU_FB 382 #endif 383 384 #ifdef CONFIG_ATI 385 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 386 #define CONFIG_BIOSEMU 387 #define CONFIG_ATI_RADEON_FB 388 #define CONFIG_VIDEO_LOGO 389 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 390 #endif 391 392 /* I2C */ 393 #define CONFIG_SYS_I2C 394 #define CONFIG_SYS_I2C_FSL 395 #define CONFIG_SYS_FSL_I2C_SPEED 400000 396 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 397 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 398 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 399 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 400 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 401 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 402 403 /* 404 * I2C2 EEPROM 405 */ 406 #define CONFIG_ID_EEPROM 407 #define CONFIG_SYS_I2C_EEPROM_NXID 408 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 409 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 410 #define CONFIG_SYS_EEPROM_BUS_NUM 1 411 412 /* 413 * eSPI - Enhanced SPI 414 */ 415 416 #define CONFIG_HARD_SPI 417 418 #define CONFIG_SF_DEFAULT_SPEED 10000000 419 #define CONFIG_SF_DEFAULT_MODE 0 420 421 /* 422 * General PCI 423 * Memory space is mapped 1-1, but I/O space must start from 0. 424 */ 425 426 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 427 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 430 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 431 #else 432 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 433 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 434 #endif 435 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 436 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 437 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 440 #else 441 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 442 #endif 443 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 444 445 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 446 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 449 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 450 #else 451 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 452 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 453 #endif 454 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 455 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 456 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 457 #ifdef CONFIG_PHYS_64BIT 458 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 459 #else 460 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 461 #endif 462 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 463 464 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 465 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 466 #ifdef CONFIG_PHYS_64BIT 467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 469 #else 470 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 471 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 472 #endif 473 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 474 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 475 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 478 #else 479 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 480 #endif 481 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 482 483 #ifdef CONFIG_PCI 484 #define CONFIG_PCI_INDIRECT_BRIDGE 485 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 486 #endif 487 488 /* SATA */ 489 #define CONFIG_LIBATA 490 #define CONFIG_FSL_SATA 491 #define CONFIG_FSL_SATA_V2 492 493 #define CONFIG_SYS_SATA_MAX_DEVICE 2 494 #define CONFIG_SATA1 495 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 496 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 497 #define CONFIG_SATA2 498 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 499 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 500 501 #ifdef CONFIG_FSL_SATA 502 #define CONFIG_LBA48 503 #define CONFIG_CMD_SATA 504 #define CONFIG_DOS_PARTITION 505 #endif 506 507 #ifdef CONFIG_MMC 508 #define CONFIG_FSL_ESDHC 509 #define CONFIG_GENERIC_MMC 510 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 511 #endif 512 513 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 514 #define CONFIG_DOS_PARTITION 515 #endif 516 517 #define CONFIG_TSEC_ENET 518 #ifdef CONFIG_TSEC_ENET 519 520 #define CONFIG_TSECV2 521 522 #define CONFIG_MII /* MII PHY management */ 523 #define CONFIG_TSEC1 1 524 #define CONFIG_TSEC1_NAME "eTSEC1" 525 #define CONFIG_TSEC2 1 526 #define CONFIG_TSEC2_NAME "eTSEC2" 527 528 #define TSEC1_PHY_ADDR 1 529 #define TSEC2_PHY_ADDR 2 530 531 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 532 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 533 534 #define TSEC1_PHYIDX 0 535 #define TSEC2_PHYIDX 0 536 537 #define CONFIG_ETHPRIME "eTSEC1" 538 539 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 540 #endif 541 542 /* 543 * Dynamic MTD Partition support with mtdparts 544 */ 545 #define CONFIG_MTD_DEVICE 546 #define CONFIG_MTD_PARTITIONS 547 #define CONFIG_CMD_MTDPARTS 548 #define CONFIG_FLASH_CFI_MTD 549 #ifdef CONFIG_PHYS_64BIT 550 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 551 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 552 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 553 "512k(dtb),768k(u-boot)" 554 #else 555 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 556 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 557 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 558 "512k(dtb),768k(u-boot)" 559 #endif 560 561 /* 562 * Environment 563 */ 564 #ifdef CONFIG_SPIFLASH 565 #define CONFIG_ENV_IS_IN_SPI_FLASH 566 #define CONFIG_ENV_SPI_BUS 0 567 #define CONFIG_ENV_SPI_CS 0 568 #define CONFIG_ENV_SPI_MAX_HZ 10000000 569 #define CONFIG_ENV_SPI_MODE 0 570 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 571 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 572 #define CONFIG_ENV_SECT_SIZE 0x10000 573 #elif defined(CONFIG_SDCARD) 574 #define CONFIG_ENV_IS_IN_MMC 575 #define CONFIG_FSL_FIXED_MMC_LOCATION 576 #define CONFIG_ENV_SIZE 0x2000 577 #define CONFIG_SYS_MMC_ENV_DEV 0 578 #elif defined(CONFIG_NAND) 579 #ifdef CONFIG_TPL_BUILD 580 #define CONFIG_ENV_SIZE 0x2000 581 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 582 #else 583 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 584 #endif 585 #define CONFIG_ENV_IS_IN_NAND 586 #define CONFIG_ENV_OFFSET (1024 * 1024) 587 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 588 #elif defined(CONFIG_SYS_RAMBOOT) 589 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 590 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 591 #define CONFIG_ENV_SIZE 0x2000 592 #else 593 #define CONFIG_ENV_IS_IN_FLASH 594 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 595 #define CONFIG_ENV_SIZE 0x2000 596 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 597 #endif 598 599 #define CONFIG_LOADS_ECHO 600 #define CONFIG_SYS_LOADS_BAUD_CHANGE 601 602 /* 603 * Command line configuration. 604 */ 605 #define CONFIG_CMD_ERRATA 606 #define CONFIG_CMD_IRQ 607 #define CONFIG_CMD_REGINFO 608 609 #ifdef CONFIG_PCI 610 #define CONFIG_CMD_PCI 611 #endif 612 613 /* 614 * USB 615 */ 616 #define CONFIG_HAS_FSL_DR_USB 617 #ifdef CONFIG_HAS_FSL_DR_USB 618 #define CONFIG_USB_EHCI 619 620 #ifdef CONFIG_USB_EHCI 621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 622 #define CONFIG_USB_EHCI_FSL 623 #endif 624 #endif 625 626 /* 627 * Miscellaneous configurable options 628 */ 629 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 630 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 631 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 632 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 633 #ifdef CONFIG_CMD_KGDB 634 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 635 #else 636 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 637 #endif 638 /* Print Buffer Size */ 639 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 640 #define CONFIG_SYS_MAXARGS 16 641 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 642 643 /* 644 * For booting Linux, the board info and command line data 645 * have to be in the first 64 MB of memory, since this is 646 * the maximum mapped by the Linux kernel during initialization. 647 */ 648 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 649 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 650 651 #ifdef CONFIG_CMD_KGDB 652 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 653 #endif 654 655 /* 656 * Environment Configuration 657 */ 658 659 #define CONFIG_HOSTNAME p1022ds 660 #define CONFIG_ROOTPATH "/opt/nfsroot" 661 #define CONFIG_BOOTFILE "uImage" 662 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 663 664 #define CONFIG_LOADADDR 1000000 665 666 667 #define CONFIG_BAUDRATE 115200 668 669 #define CONFIG_EXTRA_ENV_SETTINGS \ 670 "netdev=eth0\0" \ 671 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 672 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 673 "tftpflash=tftpboot $loadaddr $uboot && " \ 674 "protect off $ubootaddr +$filesize && " \ 675 "erase $ubootaddr +$filesize && " \ 676 "cp.b $loadaddr $ubootaddr $filesize && " \ 677 "protect on $ubootaddr +$filesize && " \ 678 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 679 "consoledev=ttyS0\0" \ 680 "ramdiskaddr=2000000\0" \ 681 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 682 "fdtaddr=1e00000\0" \ 683 "fdtfile=p1022ds.dtb\0" \ 684 "bdev=sda3\0" \ 685 "hwconfig=esdhc;audclk:12\0" 686 687 #define CONFIG_HDBOOT \ 688 "setenv bootargs root=/dev/$bdev rw " \ 689 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr - $fdtaddr" 693 694 #define CONFIG_NFSBOOTCOMMAND \ 695 "setenv bootargs root=/dev/nfs rw " \ 696 "nfsroot=$serverip:$rootpath " \ 697 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 698 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 699 "tftp $loadaddr $bootfile;" \ 700 "tftp $fdtaddr $fdtfile;" \ 701 "bootm $loadaddr - $fdtaddr" 702 703 #define CONFIG_RAMBOOTCOMMAND \ 704 "setenv bootargs root=/dev/ram rw " \ 705 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 706 "tftp $ramdiskaddr $ramdiskfile;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr $ramdiskaddr $fdtaddr" 710 711 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 712 713 #endif 714