1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #ifdef CONFIG_SDCARD 19 #define CONFIG_SPL 20 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 21 #define CONFIG_SPL_ENV_SUPPORT 22 #define CONFIG_SPL_SERIAL_SUPPORT 23 #define CONFIG_SPL_MMC_SUPPORT 24 #define CONFIG_SPL_MMC_MINIMAL 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 27 #define CONFIG_SPL_LIBGENERIC_SUPPORT 28 #define CONFIG_SPL_LIBCOMMON_SUPPORT 29 #define CONFIG_SPL_I2C_SUPPORT 30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 31 #define CONFIG_SYS_TEXT_BASE 0x11001000 32 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 33 #define CONFIG_SPL_PAD_TO 0x18000 34 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 35 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 36 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 37 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 38 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 41 #define CONFIG_SPL_MMC_BOOT 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #endif 45 #endif 46 47 #ifdef CONFIG_SPIFLASH 48 #define CONFIG_SPL 49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 50 #define CONFIG_SPL_ENV_SUPPORT 51 #define CONFIG_SPL_SERIAL_SUPPORT 52 #define CONFIG_SPL_SPI_SUPPORT 53 #define CONFIG_SPL_SPI_FLASH_SUPPORT 54 #define CONFIG_SPL_SPI_FLASH_MINIMAL 55 #define CONFIG_SPL_FLUSH_IMAGE 56 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 57 #define CONFIG_SPL_LIBGENERIC_SUPPORT 58 #define CONFIG_SPL_LIBCOMMON_SUPPORT 59 #define CONFIG_SPL_I2C_SUPPORT 60 #define CONFIG_FSL_LAW /* Use common FSL init code */ 61 #define CONFIG_SYS_TEXT_BASE 0x11001000 62 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 63 #define CONFIG_SPL_PAD_TO 0x18000 64 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 71 #define CONFIG_SPL_SPI_BOOT 72 #ifdef CONFIG_SPL_BUILD 73 #define CONFIG_SPL_COMMON_INIT_DDR 74 #endif 75 #endif 76 77 #define CONFIG_NAND_FSL_ELBC 78 79 #ifdef CONFIG_NAND 80 #define CONFIG_SPL 81 #define CONFIG_TPL 82 #ifdef CONFIG_TPL_BUILD 83 #define CONFIG_SPL_NAND_BOOT 84 #define CONFIG_SPL_FLUSH_IMAGE 85 #define CONFIG_SPL_ENV_SUPPORT 86 #define CONFIG_SPL_NAND_INIT 87 #define CONFIG_SPL_SERIAL_SUPPORT 88 #define CONFIG_SPL_LIBGENERIC_SUPPORT 89 #define CONFIG_SPL_LIBCOMMON_SUPPORT 90 #define CONFIG_SPL_I2C_SUPPORT 91 #define CONFIG_SPL_NAND_SUPPORT 92 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 93 #define CONFIG_SPL_COMMON_INIT_DDR 94 #define CONFIG_SPL_MAX_SIZE (128 << 10) 95 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 98 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 99 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 100 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 101 #elif defined(CONFIG_SPL_BUILD) 102 #define CONFIG_SPL_INIT_MINIMAL 103 #define CONFIG_SPL_SERIAL_SUPPORT 104 #define CONFIG_SPL_NAND_SUPPORT 105 #define CONFIG_SPL_FLUSH_IMAGE 106 #define CONFIG_SPL_TEXT_BASE 0xff800000 107 #define CONFIG_SPL_MAX_SIZE 4096 108 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 109 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 110 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 111 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 112 #endif 113 #define CONFIG_SPL_PAD_TO 0x20000 114 #define CONFIG_TPL_PAD_TO 0x20000 115 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 116 #define CONFIG_SYS_TEXT_BASE 0x11001000 117 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 118 #endif 119 120 /* High Level Configuration Options */ 121 #define CONFIG_BOOKE /* BOOKE */ 122 #define CONFIG_E500 /* BOOKE e500 family */ 123 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ 124 #define CONFIG_P1022 125 #define CONFIG_P1022DS 126 #define CONFIG_MP /* support multiple processors */ 127 128 #ifndef CONFIG_SYS_TEXT_BASE 129 #define CONFIG_SYS_TEXT_BASE 0xeff80000 130 #endif 131 132 #ifndef CONFIG_RESET_VECTOR_ADDRESS 133 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 134 #endif 135 136 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 137 #define CONFIG_PCI /* Enable PCI/PCIE */ 138 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 139 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 140 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ 141 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 142 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 143 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 144 145 #define CONFIG_ENABLE_36BIT_PHYS 146 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_ADDR_MAP 149 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 150 #endif 151 152 #define CONFIG_FSL_LAW /* Use common FSL init code */ 153 154 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 155 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 156 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 157 158 /* 159 * These can be toggled for performance analysis, otherwise use default. 160 */ 161 #define CONFIG_L2_CACHE 162 #define CONFIG_BTB 163 164 #define CONFIG_SYS_MEMTEST_START 0x00000000 165 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 166 167 #define CONFIG_SYS_CCSRBAR 0xffe00000 168 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 169 170 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 171 SPL code*/ 172 #ifdef CONFIG_SPL_BUILD 173 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 174 #endif 175 176 177 /* DDR Setup */ 178 #define CONFIG_DDR_SPD 179 #define CONFIG_VERY_BIG_RAM 180 #define CONFIG_FSL_DDR3 181 182 #ifdef CONFIG_DDR_ECC 183 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 184 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 185 #endif 186 187 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 189 190 #define CONFIG_NUM_DDR_CONTROLLERS 1 191 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 192 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 193 194 /* I2C addresses of SPD EEPROMs */ 195 #define CONFIG_SYS_SPD_BUS_NUM 1 196 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 197 198 /* These are used when DDR doesn't use SPD. */ 199 #define CONFIG_SYS_SDRAM_SIZE 2048 200 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 201 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 202 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 203 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 204 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 205 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 206 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 207 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 208 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 209 #define CONFIG_SYS_DDR_MODE_1 0x00441221 210 #define CONFIG_SYS_DDR_MODE_2 0x00000000 211 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 212 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 213 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 214 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 215 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 216 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 217 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 218 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 219 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 220 221 222 /* 223 * Memory map 224 * 225 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 226 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 227 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 228 * 229 * Localbus cacheable (TBD) 230 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 231 * 232 * Localbus non-cacheable 233 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 234 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 235 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 236 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 237 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 238 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 239 */ 240 241 /* 242 * Local Bus Definitions 243 */ 244 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 245 #ifdef CONFIG_PHYS_64BIT 246 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 247 #else 248 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 249 #endif 250 251 #define CONFIG_FLASH_BR_PRELIM \ 252 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 253 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 254 255 #ifdef CONFIG_NAND 256 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 257 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 258 #else 259 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 260 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 261 #endif 262 263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 264 #define CONFIG_SYS_FLASH_QUIET_TEST 265 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 266 267 #define CONFIG_SYS_MAX_FLASH_BANKS 1 268 #define CONFIG_SYS_MAX_FLASH_SECT 1024 269 270 #ifndef CONFIG_SYS_MONITOR_BASE 271 #ifdef CONFIG_SPL_BUILD 272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 273 #else 274 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 275 #endif 276 #endif 277 278 #define CONFIG_FLASH_CFI_DRIVER 279 #define CONFIG_SYS_FLASH_CFI 280 #define CONFIG_SYS_FLASH_EMPTY_INFO 281 282 /* Nand Flash */ 283 #if defined(CONFIG_NAND_FSL_ELBC) 284 #define CONFIG_SYS_NAND_BASE 0xff800000 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 287 #else 288 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 289 #endif 290 291 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 293 #define CONFIG_MTD_NAND_VERIFY_WRITE 294 #define CONFIG_CMD_NAND 1 295 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 296 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 297 298 /* NAND flash config */ 299 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 300 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 301 | BR_PS_8 /* Port Size = 8 bit */ \ 302 | BR_MS_FCM /* MSEL = FCM */ \ 303 | BR_V) /* valid */ 304 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 305 | OR_FCM_PGS /* Large Page*/ \ 306 | OR_FCM_CSCT \ 307 | OR_FCM_CST \ 308 | OR_FCM_CHT \ 309 | OR_FCM_SCY_1 \ 310 | OR_FCM_TRLX \ 311 | OR_FCM_EHTR) 312 #ifdef CONFIG_NAND 313 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 314 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 315 #else 316 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 317 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 318 #endif 319 320 #endif /* CONFIG_NAND_FSL_ELBC */ 321 322 #define CONFIG_BOARD_EARLY_INIT_F 323 #define CONFIG_BOARD_EARLY_INIT_R 324 #define CONFIG_MISC_INIT_R 325 #define CONFIG_HWCONFIG 326 327 #define CONFIG_FSL_NGPIXIS 328 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 329 #ifdef CONFIG_PHYS_64BIT 330 #define PIXIS_BASE_PHYS 0xfffdf0000ull 331 #else 332 #define PIXIS_BASE_PHYS PIXIS_BASE 333 #endif 334 335 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 336 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 337 338 #define PIXIS_LBMAP_SWITCH 7 339 #define PIXIS_LBMAP_MASK 0xF0 340 #define PIXIS_LBMAP_ALTBANK 0x20 341 #define PIXIS_SPD 0x07 342 #define PIXIS_SPD_SYSCLK_MASK 0x07 343 #define PIXIS_ELBC_SPI_MASK 0xc0 344 #define PIXIS_SPI 0x80 345 346 #define CONFIG_SYS_INIT_RAM_LOCK 347 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 348 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 349 350 #define CONFIG_SYS_GBL_DATA_OFFSET \ 351 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 352 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 353 354 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 355 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 356 357 /* 358 * Config the L2 Cache as L2 SRAM 359 */ 360 #if defined(CONFIG_SPL_BUILD) 361 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 362 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 363 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 364 #define CONFIG_SYS_L2_SIZE (256 << 10) 365 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 366 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 367 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 368 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 369 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 370 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 371 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 372 #elif defined(CONFIG_NAND) 373 #ifdef CONFIG_TPL_BUILD 374 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 375 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 376 #define CONFIG_SYS_L2_SIZE (256 << 10) 377 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 378 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 379 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 380 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 381 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 382 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 383 #else 384 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 385 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 386 #define CONFIG_SYS_L2_SIZE (256 << 10) 387 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 388 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 389 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 390 #endif 391 #endif 392 #endif 393 394 /* 395 * Serial Port 396 */ 397 #define CONFIG_CONS_INDEX 1 398 #define CONFIG_SYS_NS16550 399 #define CONFIG_SYS_NS16550_SERIAL 400 #define CONFIG_SYS_NS16550_REG_SIZE 1 401 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 402 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 403 #define CONFIG_NS16550_MIN_FUNCTIONS 404 #endif 405 406 #define CONFIG_SYS_BAUDRATE_TABLE \ 407 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 408 409 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 410 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 411 412 /* Use the HUSH parser */ 413 #define CONFIG_SYS_HUSH_PARSER 414 415 /* Video */ 416 417 #ifdef CONFIG_FSL_DIU_FB 418 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 419 #define CONFIG_VIDEO 420 #define CONFIG_CMD_BMP 421 #define CONFIG_CFB_CONSOLE 422 #define CONFIG_VIDEO_SW_CURSOR 423 #define CONFIG_VGA_AS_SINGLE_DEVICE 424 #define CONFIG_VIDEO_LOGO 425 #define CONFIG_VIDEO_BMP_LOGO 426 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 427 /* 428 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 429 * disable empty flash sector detection, which is I/O-intensive. 430 */ 431 #undef CONFIG_SYS_FLASH_EMPTY_INFO 432 #endif 433 434 #ifndef CONFIG_FSL_DIU_FB 435 #endif 436 437 #ifdef CONFIG_ATI 438 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 439 #define CONFIG_VIDEO 440 #define CONFIG_BIOSEMU 441 #define CONFIG_VIDEO_SW_CURSOR 442 #define CONFIG_ATI_RADEON_FB 443 #define CONFIG_VIDEO_LOGO 444 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 445 #define CONFIG_CFB_CONSOLE 446 #define CONFIG_VGA_AS_SINGLE_DEVICE 447 #endif 448 449 /* 450 * Pass open firmware flat tree 451 */ 452 #define CONFIG_OF_LIBFDT 453 #define CONFIG_OF_BOARD_SETUP 454 #define CONFIG_OF_STDOUT_VIA_ALIAS 455 456 /* new uImage format support */ 457 #define CONFIG_FIT 458 #define CONFIG_FIT_VERBOSE 459 460 /* I2C */ 461 #define CONFIG_SYS_I2C 462 #define CONFIG_SYS_I2C_FSL 463 #define CONFIG_SYS_FSL_I2C_SPEED 400000 464 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 465 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 466 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 467 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 468 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 469 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 470 471 /* 472 * I2C2 EEPROM 473 */ 474 #define CONFIG_ID_EEPROM 475 #define CONFIG_SYS_I2C_EEPROM_NXID 476 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 477 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 478 #define CONFIG_SYS_EEPROM_BUS_NUM 1 479 480 /* 481 * eSPI - Enhanced SPI 482 */ 483 #define CONFIG_SPI_FLASH 484 #define CONFIG_SPI_FLASH_SPANSION 485 486 #define CONFIG_HARD_SPI 487 #define CONFIG_FSL_ESPI 488 489 #define CONFIG_CMD_SF 490 #define CONFIG_SF_DEFAULT_SPEED 10000000 491 #define CONFIG_SF_DEFAULT_MODE 0 492 493 /* 494 * General PCI 495 * Memory space is mapped 1-1, but I/O space must start from 0. 496 */ 497 498 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 499 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 500 #ifdef CONFIG_PHYS_64BIT 501 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 502 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 503 #else 504 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 505 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 506 #endif 507 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 508 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 509 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 510 #ifdef CONFIG_PHYS_64BIT 511 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 512 #else 513 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 514 #endif 515 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 516 517 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 518 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 519 #ifdef CONFIG_PHYS_64BIT 520 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 521 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 522 #else 523 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 524 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 525 #endif 526 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 527 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 528 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 529 #ifdef CONFIG_PHYS_64BIT 530 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 531 #else 532 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 533 #endif 534 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 535 536 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 537 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 540 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 541 #else 542 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 543 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 544 #endif 545 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 546 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 547 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 550 #else 551 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 552 #endif 553 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 554 555 #ifdef CONFIG_PCI 556 #define CONFIG_PCI_INDIRECT_BRIDGE 557 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 559 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 560 #endif 561 562 /* SATA */ 563 #define CONFIG_LIBATA 564 #define CONFIG_FSL_SATA 565 #define CONFIG_FSL_SATA_V2 566 567 #define CONFIG_SYS_SATA_MAX_DEVICE 2 568 #define CONFIG_SATA1 569 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 570 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 571 #define CONFIG_SATA2 572 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 573 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 574 575 #ifdef CONFIG_FSL_SATA 576 #define CONFIG_LBA48 577 #define CONFIG_CMD_SATA 578 #define CONFIG_DOS_PARTITION 579 #define CONFIG_CMD_EXT2 580 #endif 581 582 #define CONFIG_MMC 583 #ifdef CONFIG_MMC 584 #define CONFIG_CMD_MMC 585 #define CONFIG_FSL_ESDHC 586 #define CONFIG_GENERIC_MMC 587 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 588 #endif 589 590 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 591 #define CONFIG_CMD_EXT2 592 #define CONFIG_CMD_FAT 593 #define CONFIG_DOS_PARTITION 594 #endif 595 596 #define CONFIG_TSEC_ENET 597 #ifdef CONFIG_TSEC_ENET 598 599 #define CONFIG_TSECV2 600 601 #define CONFIG_MII /* MII PHY management */ 602 #define CONFIG_TSEC1 1 603 #define CONFIG_TSEC1_NAME "eTSEC1" 604 #define CONFIG_TSEC2 1 605 #define CONFIG_TSEC2_NAME "eTSEC2" 606 607 #define TSEC1_PHY_ADDR 1 608 #define TSEC2_PHY_ADDR 2 609 610 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 611 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 612 613 #define TSEC1_PHYIDX 0 614 #define TSEC2_PHYIDX 0 615 616 #define CONFIG_ETHPRIME "eTSEC1" 617 618 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 619 #endif 620 621 /* 622 * Environment 623 */ 624 #ifdef CONFIG_SPIFLASH 625 #define CONFIG_ENV_IS_IN_SPI_FLASH 626 #define CONFIG_ENV_SPI_BUS 0 627 #define CONFIG_ENV_SPI_CS 0 628 #define CONFIG_ENV_SPI_MAX_HZ 10000000 629 #define CONFIG_ENV_SPI_MODE 0 630 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 631 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 632 #define CONFIG_ENV_SECT_SIZE 0x10000 633 #elif defined(CONFIG_SDCARD) 634 #define CONFIG_ENV_IS_IN_MMC 635 #define CONFIG_FSL_FIXED_MMC_LOCATION 636 #define CONFIG_ENV_SIZE 0x2000 637 #define CONFIG_SYS_MMC_ENV_DEV 0 638 #elif defined(CONFIG_NAND) 639 #ifdef CONFIG_TPL_BUILD 640 #define CONFIG_ENV_SIZE 0x2000 641 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 642 #else 643 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 644 #endif 645 #define CONFIG_ENV_IS_IN_NAND 646 #define CONFIG_ENV_OFFSET (1024 * 1024) 647 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 648 #elif defined(CONFIG_SYS_RAMBOOT) 649 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 650 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 651 #define CONFIG_ENV_SIZE 0x2000 652 #else 653 #define CONFIG_ENV_IS_IN_FLASH 654 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 655 #define CONFIG_ENV_ADDR 0xfff80000 656 #else 657 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 658 #endif 659 #define CONFIG_ENV_SIZE 0x2000 660 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 661 #endif 662 663 #define CONFIG_LOADS_ECHO 664 #define CONFIG_SYS_LOADS_BAUD_CHANGE 665 666 /* 667 * Command line configuration. 668 */ 669 #include <config_cmd_default.h> 670 671 #define CONFIG_CMD_ELF 672 #define CONFIG_CMD_ERRATA 673 #define CONFIG_CMD_IRQ 674 #define CONFIG_CMD_I2C 675 #define CONFIG_CMD_MII 676 #define CONFIG_CMD_PING 677 #define CONFIG_CMD_SETEXPR 678 #define CONFIG_CMD_REGINFO 679 680 #ifdef CONFIG_PCI 681 #define CONFIG_CMD_PCI 682 #define CONFIG_CMD_NET 683 #endif 684 685 /* 686 * USB 687 */ 688 #define CONFIG_HAS_FSL_DR_USB 689 #ifdef CONFIG_HAS_FSL_DR_USB 690 #define CONFIG_USB_EHCI 691 692 #ifdef CONFIG_USB_EHCI 693 #define CONFIG_CMD_USB 694 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 695 #define CONFIG_USB_EHCI_FSL 696 #define CONFIG_USB_STORAGE 697 #define CONFIG_CMD_FAT 698 #endif 699 #endif 700 701 /* 702 * Miscellaneous configurable options 703 */ 704 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 705 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 706 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 707 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 708 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 709 #ifdef CONFIG_CMD_KGDB 710 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 711 #else 712 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 713 #endif 714 /* Print Buffer Size */ 715 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 716 #define CONFIG_SYS_MAXARGS 16 717 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 718 #define CONFIG_SYS_HZ 1000 719 720 /* 721 * For booting Linux, the board info and command line data 722 * have to be in the first 64 MB of memory, since this is 723 * the maximum mapped by the Linux kernel during initialization. 724 */ 725 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 726 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 727 728 #ifdef CONFIG_CMD_KGDB 729 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 730 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 731 #endif 732 733 /* 734 * Environment Configuration 735 */ 736 737 #define CONFIG_HOSTNAME p1022ds 738 #define CONFIG_ROOTPATH "/opt/nfsroot" 739 #define CONFIG_BOOTFILE "uImage" 740 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 741 742 #define CONFIG_LOADADDR 1000000 743 744 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 745 746 #define CONFIG_BAUDRATE 115200 747 748 #define CONFIG_EXTRA_ENV_SETTINGS \ 749 "netdev=eth0\0" \ 750 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 751 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 752 "tftpflash=tftpboot $loadaddr $uboot && " \ 753 "protect off $ubootaddr +$filesize && " \ 754 "erase $ubootaddr +$filesize && " \ 755 "cp.b $loadaddr $ubootaddr $filesize && " \ 756 "protect on $ubootaddr +$filesize && " \ 757 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 758 "consoledev=ttyS0\0" \ 759 "ramdiskaddr=2000000\0" \ 760 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 761 "fdtaddr=c00000\0" \ 762 "fdtfile=p1022ds.dtb\0" \ 763 "bdev=sda3\0" \ 764 "hwconfig=esdhc;audclk:12\0" 765 766 #define CONFIG_HDBOOT \ 767 "setenv bootargs root=/dev/$bdev rw " \ 768 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 769 "tftp $loadaddr $bootfile;" \ 770 "tftp $fdtaddr $fdtfile;" \ 771 "bootm $loadaddr - $fdtaddr" 772 773 #define CONFIG_NFSBOOTCOMMAND \ 774 "setenv bootargs root=/dev/nfs rw " \ 775 "nfsroot=$serverip:$rootpath " \ 776 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 777 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 778 "tftp $loadaddr $bootfile;" \ 779 "tftp $fdtaddr $fdtfile;" \ 780 "bootm $loadaddr - $fdtaddr" 781 782 #define CONFIG_RAMBOOTCOMMAND \ 783 "setenv bootargs root=/dev/ram rw " \ 784 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 785 "tftp $ramdiskaddr $ramdiskfile;" \ 786 "tftp $loadaddr $bootfile;" \ 787 "tftp $fdtaddr $fdtfile;" \ 788 "bootm $loadaddr $ramdiskaddr $fdtaddr" 789 790 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 791 792 #endif 793