1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2012 Freescale Semiconductor, Inc. 4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 5 * Timur Tabi <timur@freescale.com> 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include "../board/freescale/common/ics307_clk.h" 12 13 #ifdef CONFIG_SDCARD 14 #define CONFIG_SPL_FLUSH_IMAGE 15 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 16 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 17 #define CONFIG_SPL_PAD_TO 0x20000 18 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 19 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 20 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 21 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 22 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 23 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 24 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 25 #define CONFIG_SPL_MMC_BOOT 26 #ifdef CONFIG_SPL_BUILD 27 #define CONFIG_SPL_COMMON_INIT_DDR 28 #endif 29 #endif 30 31 #ifdef CONFIG_SPIFLASH 32 #define CONFIG_SPL_SPI_FLASH_MINIMAL 33 #define CONFIG_SPL_FLUSH_IMAGE 34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 35 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 36 #define CONFIG_SPL_PAD_TO 0x20000 37 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 42 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SPL_SPI_BOOT 45 #ifdef CONFIG_SPL_BUILD 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #endif 48 #endif 49 50 #define CONFIG_NAND_FSL_ELBC 51 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 52 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 53 54 #ifdef CONFIG_NAND 55 #ifdef CONFIG_TPL_BUILD 56 #define CONFIG_SPL_NAND_BOOT 57 #define CONFIG_SPL_FLUSH_IMAGE 58 #define CONFIG_SPL_NAND_INIT 59 #define CONFIG_SPL_COMMON_INIT_DDR 60 #define CONFIG_SPL_MAX_SIZE (128 << 10) 61 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 62 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 63 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 64 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 65 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 66 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 67 #elif defined(CONFIG_SPL_BUILD) 68 #define CONFIG_SPL_INIT_MINIMAL 69 #define CONFIG_SPL_FLUSH_IMAGE 70 #define CONFIG_SPL_TEXT_BASE 0xff800000 71 #define CONFIG_SPL_MAX_SIZE 4096 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 73 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 74 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 75 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 76 #endif 77 #define CONFIG_SPL_PAD_TO 0x20000 78 #define CONFIG_TPL_PAD_TO 0x20000 79 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 81 #endif 82 83 /* High Level Configuration Options */ 84 85 #ifndef CONFIG_RESET_VECTOR_ADDRESS 86 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 87 #endif 88 89 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 90 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 91 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 92 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 93 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 94 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 95 96 #define CONFIG_ENABLE_36BIT_PHYS 97 98 #ifdef CONFIG_PHYS_64BIT 99 #define CONFIG_ADDR_MAP 100 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 101 #endif 102 103 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 104 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 105 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 106 107 /* 108 * These can be toggled for performance analysis, otherwise use default. 109 */ 110 #define CONFIG_L2_CACHE 111 #define CONFIG_BTB 112 113 #define CONFIG_SYS_MEMTEST_START 0x00000000 114 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 115 116 #define CONFIG_SYS_CCSRBAR 0xffe00000 117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 118 119 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 120 SPL code*/ 121 #ifdef CONFIG_SPL_BUILD 122 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 123 #endif 124 125 /* DDR Setup */ 126 #define CONFIG_DDR_SPD 127 #define CONFIG_VERY_BIG_RAM 128 129 #ifdef CONFIG_DDR_ECC 130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 132 #endif 133 134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 137 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 138 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 139 140 /* I2C addresses of SPD EEPROMs */ 141 #define CONFIG_SYS_SPD_BUS_NUM 1 142 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 143 144 /* These are used when DDR doesn't use SPD. */ 145 #define CONFIG_SYS_SDRAM_SIZE 2048 146 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 148 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 149 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 150 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 151 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 152 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 153 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 154 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 155 #define CONFIG_SYS_DDR_MODE_1 0x00441221 156 #define CONFIG_SYS_DDR_MODE_2 0x00000000 157 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 158 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 159 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 160 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 161 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 162 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 163 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 164 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 165 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 166 167 /* 168 * Memory map 169 * 170 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 171 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 172 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 173 * 174 * Localbus cacheable (TBD) 175 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 176 * 177 * Localbus non-cacheable 178 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 179 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 180 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 181 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 182 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 183 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 184 */ 185 186 /* 187 * Local Bus Definitions 188 */ 189 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 190 #ifdef CONFIG_PHYS_64BIT 191 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 192 #else 193 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 194 #endif 195 196 #define CONFIG_FLASH_BR_PRELIM \ 197 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 198 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 199 200 #ifdef CONFIG_NAND 201 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 202 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 203 #else 204 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 205 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 206 #endif 207 208 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 209 #define CONFIG_SYS_FLASH_QUIET_TEST 210 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 211 212 #define CONFIG_SYS_MAX_FLASH_BANKS 1 213 #define CONFIG_SYS_MAX_FLASH_SECT 1024 214 215 #ifndef CONFIG_SYS_MONITOR_BASE 216 #ifdef CONFIG_SPL_BUILD 217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 218 #else 219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 220 #endif 221 #endif 222 223 #define CONFIG_FLASH_CFI_DRIVER 224 #define CONFIG_SYS_FLASH_CFI 225 #define CONFIG_SYS_FLASH_EMPTY_INFO 226 227 /* Nand Flash */ 228 #if defined(CONFIG_NAND_FSL_ELBC) 229 #define CONFIG_SYS_NAND_BASE 0xff800000 230 #ifdef CONFIG_PHYS_64BIT 231 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 232 #else 233 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 234 #endif 235 236 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 237 #define CONFIG_SYS_MAX_NAND_DEVICE 1 238 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 239 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 240 241 /* NAND flash config */ 242 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 243 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 244 | BR_PS_8 /* Port Size = 8 bit */ \ 245 | BR_MS_FCM /* MSEL = FCM */ \ 246 | BR_V) /* valid */ 247 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 248 | OR_FCM_PGS /* Large Page*/ \ 249 | OR_FCM_CSCT \ 250 | OR_FCM_CST \ 251 | OR_FCM_CHT \ 252 | OR_FCM_SCY_1 \ 253 | OR_FCM_TRLX \ 254 | OR_FCM_EHTR) 255 #ifdef CONFIG_NAND 256 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 257 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 258 #else 259 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 260 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 261 #endif 262 263 #endif /* CONFIG_NAND_FSL_ELBC */ 264 265 #define CONFIG_MISC_INIT_R 266 #define CONFIG_HWCONFIG 267 268 #define CONFIG_FSL_NGPIXIS 269 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 270 #ifdef CONFIG_PHYS_64BIT 271 #define PIXIS_BASE_PHYS 0xfffdf0000ull 272 #else 273 #define PIXIS_BASE_PHYS PIXIS_BASE 274 #endif 275 276 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 277 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 278 279 #define PIXIS_LBMAP_SWITCH 7 280 #define PIXIS_LBMAP_MASK 0xF0 281 #define PIXIS_LBMAP_ALTBANK 0x20 282 #define PIXIS_SPD 0x07 283 #define PIXIS_SPD_SYSCLK_MASK 0x07 284 #define PIXIS_ELBC_SPI_MASK 0xc0 285 #define PIXIS_SPI 0x80 286 287 #define CONFIG_SYS_INIT_RAM_LOCK 288 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 289 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 290 291 #define CONFIG_SYS_GBL_DATA_OFFSET \ 292 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 293 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 294 295 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 296 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 297 298 /* 299 * Config the L2 Cache as L2 SRAM 300 */ 301 #if defined(CONFIG_SPL_BUILD) 302 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 303 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 304 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 305 #define CONFIG_SYS_L2_SIZE (256 << 10) 306 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 307 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 308 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 309 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 310 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 311 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 312 #elif defined(CONFIG_NAND) 313 #ifdef CONFIG_TPL_BUILD 314 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 315 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 316 #define CONFIG_SYS_L2_SIZE (256 << 10) 317 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 318 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 319 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 320 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 321 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 322 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 323 #else 324 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 325 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 326 #define CONFIG_SYS_L2_SIZE (256 << 10) 327 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 328 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 329 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 330 #endif 331 #endif 332 #endif 333 334 /* 335 * Serial Port 336 */ 337 #define CONFIG_SYS_NS16550_SERIAL 338 #define CONFIG_SYS_NS16550_REG_SIZE 1 339 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 340 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 341 #define CONFIG_NS16550_MIN_FUNCTIONS 342 #endif 343 344 #define CONFIG_SYS_BAUDRATE_TABLE \ 345 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 346 347 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 348 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 349 350 /* Video */ 351 352 #ifdef CONFIG_FSL_DIU_FB 353 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 354 #define CONFIG_VIDEO_LOGO 355 #define CONFIG_VIDEO_BMP_LOGO 356 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 357 /* 358 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 359 * disable empty flash sector detection, which is I/O-intensive. 360 */ 361 #undef CONFIG_SYS_FLASH_EMPTY_INFO 362 #endif 363 364 #ifdef CONFIG_ATI 365 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 366 #define CONFIG_BIOSEMU 367 #define CONFIG_ATI_RADEON_FB 368 #define CONFIG_VIDEO_LOGO 369 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 370 #endif 371 372 /* I2C */ 373 #define CONFIG_SYS_I2C 374 #define CONFIG_SYS_I2C_FSL 375 #define CONFIG_SYS_FSL_I2C_SPEED 400000 376 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 377 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 378 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 379 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 380 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 381 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 382 383 /* 384 * I2C2 EEPROM 385 */ 386 #define CONFIG_ID_EEPROM 387 #define CONFIG_SYS_I2C_EEPROM_NXID 388 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 389 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 390 #define CONFIG_SYS_EEPROM_BUS_NUM 1 391 392 /* 393 * eSPI - Enhanced SPI 394 */ 395 396 #define CONFIG_HARD_SPI 397 398 #define CONFIG_SF_DEFAULT_SPEED 10000000 399 #define CONFIG_SF_DEFAULT_MODE 0 400 401 /* 402 * General PCI 403 * Memory space is mapped 1-1, but I/O space must start from 0. 404 */ 405 406 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 407 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 410 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 411 #else 412 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 413 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 414 #endif 415 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 416 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 417 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 420 #else 421 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 422 #endif 423 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 424 425 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 426 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 429 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 430 #else 431 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 432 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 433 #endif 434 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 435 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 436 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 439 #else 440 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 441 #endif 442 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 443 444 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 445 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 448 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 449 #else 450 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 451 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 452 #endif 453 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 454 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 455 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 456 #ifdef CONFIG_PHYS_64BIT 457 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 458 #else 459 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 460 #endif 461 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 462 463 #ifdef CONFIG_PCI 464 #define CONFIG_PCI_INDIRECT_BRIDGE 465 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 466 #endif 467 468 /* SATA */ 469 #define CONFIG_FSL_SATA_V2 470 471 #define CONFIG_SYS_SATA_MAX_DEVICE 2 472 #define CONFIG_SATA1 473 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 474 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 475 #define CONFIG_SATA2 476 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 477 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 478 479 #ifdef CONFIG_FSL_SATA 480 #define CONFIG_LBA48 481 #endif 482 483 #ifdef CONFIG_MMC 484 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 485 #endif 486 487 #ifdef CONFIG_TSEC_ENET 488 489 #define CONFIG_TSECV2 490 491 #define CONFIG_MII /* MII PHY management */ 492 #define CONFIG_TSEC1 1 493 #define CONFIG_TSEC1_NAME "eTSEC1" 494 #define CONFIG_TSEC2 1 495 #define CONFIG_TSEC2_NAME "eTSEC2" 496 497 #define TSEC1_PHY_ADDR 1 498 #define TSEC2_PHY_ADDR 2 499 500 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 501 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 502 503 #define TSEC1_PHYIDX 0 504 #define TSEC2_PHYIDX 0 505 506 #define CONFIG_ETHPRIME "eTSEC1" 507 #endif 508 509 /* 510 * Dynamic MTD Partition support with mtdparts 511 */ 512 #define CONFIG_FLASH_CFI_MTD 513 514 /* 515 * Environment 516 */ 517 #ifdef CONFIG_SPIFLASH 518 #define CONFIG_ENV_SPI_BUS 0 519 #define CONFIG_ENV_SPI_CS 0 520 #define CONFIG_ENV_SPI_MAX_HZ 10000000 521 #define CONFIG_ENV_SPI_MODE 0 522 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 523 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 524 #define CONFIG_ENV_SECT_SIZE 0x10000 525 #elif defined(CONFIG_SDCARD) 526 #define CONFIG_FSL_FIXED_MMC_LOCATION 527 #define CONFIG_ENV_SIZE 0x2000 528 #define CONFIG_SYS_MMC_ENV_DEV 0 529 #elif defined(CONFIG_NAND) 530 #ifdef CONFIG_TPL_BUILD 531 #define CONFIG_ENV_SIZE 0x2000 532 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 533 #else 534 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 535 #endif 536 #define CONFIG_ENV_OFFSET (1024 * 1024) 537 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 538 #elif defined(CONFIG_SYS_RAMBOOT) 539 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 540 #define CONFIG_ENV_SIZE 0x2000 541 #else 542 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 543 #define CONFIG_ENV_SIZE 0x2000 544 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 545 #endif 546 547 #define CONFIG_LOADS_ECHO 548 #define CONFIG_SYS_LOADS_BAUD_CHANGE 549 550 /* 551 * USB 552 */ 553 #define CONFIG_HAS_FSL_DR_USB 554 #ifdef CONFIG_HAS_FSL_DR_USB 555 #ifdef CONFIG_USB_EHCI_HCD 556 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 557 #define CONFIG_USB_EHCI_FSL 558 #endif 559 #endif 560 561 /* 562 * Miscellaneous configurable options 563 */ 564 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 565 566 /* 567 * For booting Linux, the board info and command line data 568 * have to be in the first 64 MB of memory, since this is 569 * the maximum mapped by the Linux kernel during initialization. 570 */ 571 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 572 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 573 574 #ifdef CONFIG_CMD_KGDB 575 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 576 #endif 577 578 /* 579 * Environment Configuration 580 */ 581 582 #define CONFIG_HOSTNAME "p1022ds" 583 #define CONFIG_ROOTPATH "/opt/nfsroot" 584 #define CONFIG_BOOTFILE "uImage" 585 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 586 587 #define CONFIG_LOADADDR 1000000 588 589 #define CONFIG_EXTRA_ENV_SETTINGS \ 590 "netdev=eth0\0" \ 591 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 592 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 593 "tftpflash=tftpboot $loadaddr $uboot && " \ 594 "protect off $ubootaddr +$filesize && " \ 595 "erase $ubootaddr +$filesize && " \ 596 "cp.b $loadaddr $ubootaddr $filesize && " \ 597 "protect on $ubootaddr +$filesize && " \ 598 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 599 "consoledev=ttyS0\0" \ 600 "ramdiskaddr=2000000\0" \ 601 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 602 "fdtaddr=1e00000\0" \ 603 "fdtfile=p1022ds.dtb\0" \ 604 "bdev=sda3\0" \ 605 "hwconfig=esdhc;audclk:12\0" 606 607 #define CONFIG_HDBOOT \ 608 "setenv bootargs root=/dev/$bdev rw " \ 609 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 610 "tftp $loadaddr $bootfile;" \ 611 "tftp $fdtaddr $fdtfile;" \ 612 "bootm $loadaddr - $fdtaddr" 613 614 #define CONFIG_NFSBOOTCOMMAND \ 615 "setenv bootargs root=/dev/nfs rw " \ 616 "nfsroot=$serverip:$rootpath " \ 617 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 618 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 619 "tftp $loadaddr $bootfile;" \ 620 "tftp $fdtaddr $fdtfile;" \ 621 "bootm $loadaddr - $fdtaddr" 622 623 #define CONFIG_RAMBOOTCOMMAND \ 624 "setenv bootargs root=/dev/ram rw " \ 625 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 626 "tftp $ramdiskaddr $ramdiskfile;" \ 627 "tftp $loadaddr $bootfile;" \ 628 "tftp $fdtaddr $fdtfile;" \ 629 "bootm $loadaddr $ramdiskaddr $fdtaddr" 630 631 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 632 633 #endif 634