1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_MMC_MINIMAL 18 #define CONFIG_SPL_FLUSH_IMAGE 19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 20 #define CONFIG_FSL_LAW /* Use common FSL init code */ 21 #define CONFIG_SYS_TEXT_BASE 0x11001000 22 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 23 #define CONFIG_SPL_PAD_TO 0x20000 24 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 31 #define CONFIG_SPL_MMC_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #endif 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #define CONFIG_SPL_SPI_FLASH_MINIMAL 39 #define CONFIG_SPL_FLUSH_IMAGE 40 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 41 #define CONFIG_FSL_LAW /* Use common FSL init code */ 42 #define CONFIG_SYS_TEXT_BASE 0x11001000 43 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 44 #define CONFIG_SPL_PAD_TO 0x20000 45 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 50 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 52 #define CONFIG_SPL_SPI_BOOT 53 #ifdef CONFIG_SPL_BUILD 54 #define CONFIG_SPL_COMMON_INIT_DDR 55 #endif 56 #endif 57 58 #define CONFIG_NAND_FSL_ELBC 59 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 60 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 61 62 #ifdef CONFIG_NAND 63 #ifdef CONFIG_TPL_BUILD 64 #define CONFIG_SPL_NAND_BOOT 65 #define CONFIG_SPL_FLUSH_IMAGE 66 #define CONFIG_SPL_NAND_INIT 67 #define CONFIG_SPL_COMMON_INIT_DDR 68 #define CONFIG_SPL_MAX_SIZE (128 << 10) 69 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 71 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 72 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 73 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 74 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 75 #elif defined(CONFIG_SPL_BUILD) 76 #define CONFIG_SPL_INIT_MINIMAL 77 #define CONFIG_SPL_FLUSH_IMAGE 78 #define CONFIG_SPL_TEXT_BASE 0xff800000 79 #define CONFIG_SPL_MAX_SIZE 4096 80 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 81 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 82 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 83 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 84 #endif 85 #define CONFIG_SPL_PAD_TO 0x20000 86 #define CONFIG_TPL_PAD_TO 0x20000 87 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 88 #define CONFIG_SYS_TEXT_BASE 0x11001000 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 90 #endif 91 92 /* High Level Configuration Options */ 93 #define CONFIG_BOOKE /* BOOKE */ 94 #define CONFIG_E500 /* BOOKE e500 family */ 95 #define CONFIG_P1022 96 #define CONFIG_P1022DS 97 #define CONFIG_MP /* support multiple processors */ 98 99 #ifndef CONFIG_SYS_TEXT_BASE 100 #define CONFIG_SYS_TEXT_BASE 0xeff40000 101 #endif 102 103 #ifndef CONFIG_RESET_VECTOR_ADDRESS 104 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 105 #endif 106 107 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 108 #define CONFIG_PCI /* Enable PCI/PCIE */ 109 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 110 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 111 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 112 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 113 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 114 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 115 116 #define CONFIG_ENABLE_36BIT_PHYS 117 118 #ifdef CONFIG_PHYS_64BIT 119 #define CONFIG_ADDR_MAP 120 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 121 #endif 122 123 #define CONFIG_FSL_LAW /* Use common FSL init code */ 124 125 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 126 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 127 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 128 129 /* 130 * These can be toggled for performance analysis, otherwise use default. 131 */ 132 #define CONFIG_L2_CACHE 133 #define CONFIG_BTB 134 135 #define CONFIG_SYS_MEMTEST_START 0x00000000 136 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 137 138 #define CONFIG_SYS_CCSRBAR 0xffe00000 139 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 140 141 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 142 SPL code*/ 143 #ifdef CONFIG_SPL_BUILD 144 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 145 #endif 146 147 /* DDR Setup */ 148 #define CONFIG_DDR_SPD 149 #define CONFIG_VERY_BIG_RAM 150 #define CONFIG_SYS_FSL_DDR3 151 152 #ifdef CONFIG_DDR_ECC 153 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 154 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 155 #endif 156 157 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 159 160 #define CONFIG_NUM_DDR_CONTROLLERS 1 161 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 162 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 163 164 /* I2C addresses of SPD EEPROMs */ 165 #define CONFIG_SYS_SPD_BUS_NUM 1 166 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 167 168 /* These are used when DDR doesn't use SPD. */ 169 #define CONFIG_SYS_SDRAM_SIZE 2048 170 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 171 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 172 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 173 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 174 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 175 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 176 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 177 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 178 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 179 #define CONFIG_SYS_DDR_MODE_1 0x00441221 180 #define CONFIG_SYS_DDR_MODE_2 0x00000000 181 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 182 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 183 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 184 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 185 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 186 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 187 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 188 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 189 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 190 191 /* 192 * Memory map 193 * 194 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 195 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 196 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 197 * 198 * Localbus cacheable (TBD) 199 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 200 * 201 * Localbus non-cacheable 202 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 203 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 204 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 205 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 206 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 207 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 208 */ 209 210 /* 211 * Local Bus Definitions 212 */ 213 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 214 #ifdef CONFIG_PHYS_64BIT 215 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 216 #else 217 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 218 #endif 219 220 #define CONFIG_FLASH_BR_PRELIM \ 221 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 222 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 223 224 #ifdef CONFIG_NAND 225 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 226 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 227 #else 228 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 229 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 230 #endif 231 232 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 233 #define CONFIG_SYS_FLASH_QUIET_TEST 234 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 235 236 #define CONFIG_SYS_MAX_FLASH_BANKS 1 237 #define CONFIG_SYS_MAX_FLASH_SECT 1024 238 239 #ifndef CONFIG_SYS_MONITOR_BASE 240 #ifdef CONFIG_SPL_BUILD 241 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 242 #else 243 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 244 #endif 245 #endif 246 247 #define CONFIG_FLASH_CFI_DRIVER 248 #define CONFIG_SYS_FLASH_CFI 249 #define CONFIG_SYS_FLASH_EMPTY_INFO 250 251 /* Nand Flash */ 252 #if defined(CONFIG_NAND_FSL_ELBC) 253 #define CONFIG_SYS_NAND_BASE 0xff800000 254 #ifdef CONFIG_PHYS_64BIT 255 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 256 #else 257 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 258 #endif 259 260 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 261 #define CONFIG_SYS_MAX_NAND_DEVICE 1 262 #define CONFIG_CMD_NAND 1 263 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 264 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 265 266 /* NAND flash config */ 267 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 268 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 269 | BR_PS_8 /* Port Size = 8 bit */ \ 270 | BR_MS_FCM /* MSEL = FCM */ \ 271 | BR_V) /* valid */ 272 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 273 | OR_FCM_PGS /* Large Page*/ \ 274 | OR_FCM_CSCT \ 275 | OR_FCM_CST \ 276 | OR_FCM_CHT \ 277 | OR_FCM_SCY_1 \ 278 | OR_FCM_TRLX \ 279 | OR_FCM_EHTR) 280 #ifdef CONFIG_NAND 281 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 282 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 283 #else 284 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 285 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 286 #endif 287 288 #endif /* CONFIG_NAND_FSL_ELBC */ 289 290 #define CONFIG_BOARD_EARLY_INIT_F 291 #define CONFIG_BOARD_EARLY_INIT_R 292 #define CONFIG_MISC_INIT_R 293 #define CONFIG_HWCONFIG 294 295 #define CONFIG_FSL_NGPIXIS 296 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 297 #ifdef CONFIG_PHYS_64BIT 298 #define PIXIS_BASE_PHYS 0xfffdf0000ull 299 #else 300 #define PIXIS_BASE_PHYS PIXIS_BASE 301 #endif 302 303 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 304 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 305 306 #define PIXIS_LBMAP_SWITCH 7 307 #define PIXIS_LBMAP_MASK 0xF0 308 #define PIXIS_LBMAP_ALTBANK 0x20 309 #define PIXIS_SPD 0x07 310 #define PIXIS_SPD_SYSCLK_MASK 0x07 311 #define PIXIS_ELBC_SPI_MASK 0xc0 312 #define PIXIS_SPI 0x80 313 314 #define CONFIG_SYS_INIT_RAM_LOCK 315 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 316 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 317 318 #define CONFIG_SYS_GBL_DATA_OFFSET \ 319 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 320 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 321 322 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 323 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 324 325 /* 326 * Config the L2 Cache as L2 SRAM 327 */ 328 #if defined(CONFIG_SPL_BUILD) 329 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 330 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 331 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 332 #define CONFIG_SYS_L2_SIZE (256 << 10) 333 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 334 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 335 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 336 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 337 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 338 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 339 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 340 #elif defined(CONFIG_NAND) 341 #ifdef CONFIG_TPL_BUILD 342 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 343 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 344 #define CONFIG_SYS_L2_SIZE (256 << 10) 345 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 346 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 347 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 348 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 349 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 350 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 351 #else 352 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 353 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 354 #define CONFIG_SYS_L2_SIZE (256 << 10) 355 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 356 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 357 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 358 #endif 359 #endif 360 #endif 361 362 /* 363 * Serial Port 364 */ 365 #define CONFIG_CONS_INDEX 1 366 #define CONFIG_SYS_NS16550_SERIAL 367 #define CONFIG_SYS_NS16550_REG_SIZE 1 368 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 369 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 370 #define CONFIG_NS16550_MIN_FUNCTIONS 371 #endif 372 373 #define CONFIG_SYS_BAUDRATE_TABLE \ 374 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 375 376 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 377 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 378 379 /* Video */ 380 381 #ifdef CONFIG_FSL_DIU_FB 382 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 383 #define CONFIG_VIDEO 384 #define CONFIG_CMD_BMP 385 #define CONFIG_CFB_CONSOLE 386 #define CONFIG_VIDEO_SW_CURSOR 387 #define CONFIG_VGA_AS_SINGLE_DEVICE 388 #define CONFIG_VIDEO_LOGO 389 #define CONFIG_VIDEO_BMP_LOGO 390 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 391 /* 392 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 393 * disable empty flash sector detection, which is I/O-intensive. 394 */ 395 #undef CONFIG_SYS_FLASH_EMPTY_INFO 396 #endif 397 398 #ifndef CONFIG_FSL_DIU_FB 399 #endif 400 401 #ifdef CONFIG_ATI 402 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 403 #define CONFIG_VIDEO 404 #define CONFIG_BIOSEMU 405 #define CONFIG_VIDEO_SW_CURSOR 406 #define CONFIG_ATI_RADEON_FB 407 #define CONFIG_VIDEO_LOGO 408 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 409 #define CONFIG_CFB_CONSOLE 410 #define CONFIG_VGA_AS_SINGLE_DEVICE 411 #endif 412 413 /* I2C */ 414 #define CONFIG_SYS_I2C 415 #define CONFIG_SYS_I2C_FSL 416 #define CONFIG_SYS_FSL_I2C_SPEED 400000 417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 419 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 420 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 422 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 423 424 /* 425 * I2C2 EEPROM 426 */ 427 #define CONFIG_ID_EEPROM 428 #define CONFIG_SYS_I2C_EEPROM_NXID 429 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 430 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 431 #define CONFIG_SYS_EEPROM_BUS_NUM 1 432 433 /* 434 * eSPI - Enhanced SPI 435 */ 436 437 #define CONFIG_HARD_SPI 438 439 #define CONFIG_SF_DEFAULT_SPEED 10000000 440 #define CONFIG_SF_DEFAULT_MODE 0 441 442 /* 443 * General PCI 444 * Memory space is mapped 1-1, but I/O space must start from 0. 445 */ 446 447 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 448 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 451 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 452 #else 453 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 454 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 455 #endif 456 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 457 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 458 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 461 #else 462 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 463 #endif 464 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 465 466 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 467 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 470 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 471 #else 472 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 473 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 474 #endif 475 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 476 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 477 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 480 #else 481 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 482 #endif 483 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 484 485 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 486 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 487 #ifdef CONFIG_PHYS_64BIT 488 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 489 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 490 #else 491 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 492 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 493 #endif 494 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 495 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 496 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 497 #ifdef CONFIG_PHYS_64BIT 498 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 499 #else 500 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 501 #endif 502 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 503 504 #ifdef CONFIG_PCI 505 #define CONFIG_PCI_INDIRECT_BRIDGE 506 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 507 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 508 #endif 509 510 /* SATA */ 511 #define CONFIG_LIBATA 512 #define CONFIG_FSL_SATA 513 #define CONFIG_FSL_SATA_V2 514 515 #define CONFIG_SYS_SATA_MAX_DEVICE 2 516 #define CONFIG_SATA1 517 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 518 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 519 #define CONFIG_SATA2 520 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 521 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 522 523 #ifdef CONFIG_FSL_SATA 524 #define CONFIG_LBA48 525 #define CONFIG_CMD_SATA 526 #define CONFIG_DOS_PARTITION 527 #endif 528 529 #define CONFIG_MMC 530 #ifdef CONFIG_MMC 531 #define CONFIG_FSL_ESDHC 532 #define CONFIG_GENERIC_MMC 533 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 534 #endif 535 536 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 537 #define CONFIG_DOS_PARTITION 538 #endif 539 540 #define CONFIG_TSEC_ENET 541 #ifdef CONFIG_TSEC_ENET 542 543 #define CONFIG_TSECV2 544 545 #define CONFIG_MII /* MII PHY management */ 546 #define CONFIG_TSEC1 1 547 #define CONFIG_TSEC1_NAME "eTSEC1" 548 #define CONFIG_TSEC2 1 549 #define CONFIG_TSEC2_NAME "eTSEC2" 550 551 #define TSEC1_PHY_ADDR 1 552 #define TSEC2_PHY_ADDR 2 553 554 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 555 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 556 557 #define TSEC1_PHYIDX 0 558 #define TSEC2_PHYIDX 0 559 560 #define CONFIG_ETHPRIME "eTSEC1" 561 562 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 563 #endif 564 565 /* 566 * Dynamic MTD Partition support with mtdparts 567 */ 568 #define CONFIG_MTD_DEVICE 569 #define CONFIG_MTD_PARTITIONS 570 #define CONFIG_CMD_MTDPARTS 571 #define CONFIG_FLASH_CFI_MTD 572 #ifdef CONFIG_PHYS_64BIT 573 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 574 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 575 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 576 "512k(dtb),768k(u-boot)" 577 #else 578 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 579 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 580 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 581 "512k(dtb),768k(u-boot)" 582 #endif 583 584 /* 585 * Environment 586 */ 587 #ifdef CONFIG_SPIFLASH 588 #define CONFIG_ENV_IS_IN_SPI_FLASH 589 #define CONFIG_ENV_SPI_BUS 0 590 #define CONFIG_ENV_SPI_CS 0 591 #define CONFIG_ENV_SPI_MAX_HZ 10000000 592 #define CONFIG_ENV_SPI_MODE 0 593 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 594 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 595 #define CONFIG_ENV_SECT_SIZE 0x10000 596 #elif defined(CONFIG_SDCARD) 597 #define CONFIG_ENV_IS_IN_MMC 598 #define CONFIG_FSL_FIXED_MMC_LOCATION 599 #define CONFIG_ENV_SIZE 0x2000 600 #define CONFIG_SYS_MMC_ENV_DEV 0 601 #elif defined(CONFIG_NAND) 602 #ifdef CONFIG_TPL_BUILD 603 #define CONFIG_ENV_SIZE 0x2000 604 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 605 #else 606 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 607 #endif 608 #define CONFIG_ENV_IS_IN_NAND 609 #define CONFIG_ENV_OFFSET (1024 * 1024) 610 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 611 #elif defined(CONFIG_SYS_RAMBOOT) 612 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 613 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 614 #define CONFIG_ENV_SIZE 0x2000 615 #else 616 #define CONFIG_ENV_IS_IN_FLASH 617 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 618 #define CONFIG_ENV_SIZE 0x2000 619 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 620 #endif 621 622 #define CONFIG_LOADS_ECHO 623 #define CONFIG_SYS_LOADS_BAUD_CHANGE 624 625 /* 626 * Command line configuration. 627 */ 628 #define CONFIG_CMD_ERRATA 629 #define CONFIG_CMD_IRQ 630 #define CONFIG_CMD_REGINFO 631 632 #ifdef CONFIG_PCI 633 #define CONFIG_CMD_PCI 634 #endif 635 636 /* 637 * USB 638 */ 639 #define CONFIG_HAS_FSL_DR_USB 640 #ifdef CONFIG_HAS_FSL_DR_USB 641 #define CONFIG_USB_EHCI 642 643 #ifdef CONFIG_USB_EHCI 644 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 645 #define CONFIG_USB_EHCI_FSL 646 #endif 647 #endif 648 649 /* 650 * Miscellaneous configurable options 651 */ 652 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 653 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 654 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 655 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 656 #ifdef CONFIG_CMD_KGDB 657 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 658 #else 659 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 660 #endif 661 /* Print Buffer Size */ 662 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 663 #define CONFIG_SYS_MAXARGS 16 664 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 665 666 /* 667 * For booting Linux, the board info and command line data 668 * have to be in the first 64 MB of memory, since this is 669 * the maximum mapped by the Linux kernel during initialization. 670 */ 671 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 672 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 673 674 #ifdef CONFIG_CMD_KGDB 675 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 676 #endif 677 678 /* 679 * Environment Configuration 680 */ 681 682 #define CONFIG_HOSTNAME p1022ds 683 #define CONFIG_ROOTPATH "/opt/nfsroot" 684 #define CONFIG_BOOTFILE "uImage" 685 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 686 687 #define CONFIG_LOADADDR 1000000 688 689 690 #define CONFIG_BAUDRATE 115200 691 692 #define CONFIG_EXTRA_ENV_SETTINGS \ 693 "netdev=eth0\0" \ 694 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 695 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 696 "tftpflash=tftpboot $loadaddr $uboot && " \ 697 "protect off $ubootaddr +$filesize && " \ 698 "erase $ubootaddr +$filesize && " \ 699 "cp.b $loadaddr $ubootaddr $filesize && " \ 700 "protect on $ubootaddr +$filesize && " \ 701 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 702 "consoledev=ttyS0\0" \ 703 "ramdiskaddr=2000000\0" \ 704 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 705 "fdtaddr=1e00000\0" \ 706 "fdtfile=p1022ds.dtb\0" \ 707 "bdev=sda3\0" \ 708 "hwconfig=esdhc;audclk:12\0" 709 710 #define CONFIG_HDBOOT \ 711 "setenv bootargs root=/dev/$bdev rw " \ 712 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr - $fdtaddr" 716 717 #define CONFIG_NFSBOOTCOMMAND \ 718 "setenv bootargs root=/dev/nfs rw " \ 719 "nfsroot=$serverip:$rootpath " \ 720 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 721 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 722 "tftp $loadaddr $bootfile;" \ 723 "tftp $fdtaddr $fdtfile;" \ 724 "bootm $loadaddr - $fdtaddr" 725 726 #define CONFIG_RAMBOOTCOMMAND \ 727 "setenv bootargs root=/dev/ram rw " \ 728 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 729 "tftp $ramdiskaddr $ramdiskfile;" \ 730 "tftp $loadaddr $bootfile;" \ 731 "tftp $fdtaddr $fdtfile;" \ 732 "bootm $loadaddr $ramdiskaddr $fdtaddr" 733 734 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 735 736 #endif 737